December 1994

Order Number 271327-001

SPECIAL ENVIRONMENT 80960CA-25 -16

32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

Two Instructions Clock Sustained Execution

Four 59 Mbytes s DMA Channels with Data Chaining

Demultiplexed 32-bit Burst Bus with Pipelining

32-bit Parallel Architecture

Two Instructions clock Execution
Load Store Architecture
Sixteen 32-bit Global Registers
Sixteen 32-bit Local Registers
Manipulates 64-bit Bit Fields
11 Addressing Modes
Full Parallel Fault Model
Supervisor Protection Model

Fast Procedure Call Return Model

Full Procedure Call in 4 Clocks

On-Chip Register Cache

Caches Registers on Call Ret
Minimum of 6 Frames Provided
Up to 15 Programmable Frames

On-Chip instruction Cache

1 Kbyte Two-Way Set Associative
128-bit Path to instruction Sequencer
Cache-Lock Modes
Cache-Off Mode

High Bandwidth On-Chip Data RAM

1 Kbyte On-Chip Data RAM
Sustains 128 bits per Clock Access

Four On-Chip DMA Channels

59 Mbytes s Fly-by Transfers
32 Mbytes s Two-Cycle Transfers
Data Chaining
Data Packing Unpacking
Programmable Priority Method

32-Bit Demultiplexed Burst Bus

128-bit internal Data Paths to

and

from Registers
Burst Bus for DRAM Interfacing
Address Pipelining Option
Fully Programmable Wait States
Supports 8- 16- or 32-bit Bus Widths
Supports Unaligned Accesses
Supervisor Protection Pin

Selectable Big or Little Endian Byte
Ordering

High-Speed Interrupt Controller

Up to 248 External interrupts
32 Fully Programmable Priorities
Multi-mode 8-bit Interrupt Port
Four internal DMA Interrupts
Separate Non-maskable interrupt Pin
Context Switch in 750 ns Typical

Product Grades Available

SE3

40 C to

110 C

SPECIAL ENVIRONMENT 80960CA-25 -16

32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

CONTENTS

PAGE

1 0 PURPOSE

2 0 80960CA OVERVIEW

2 1 The C-Series Core

2 2 Pipelined Burst Bus

2 3 Flexible DMA Controller

2 4 Priority Interrupt Controller

2 5 Instruction Set Summary

3 0 PACKAGE INFORMATION

3 1 Package Introduction

3 2 Pin Descriptions

3 3 80960CA Mechanical Data

3 3 1 80960CA PGA Pinout

3 4 Package Thermal Specifications

3 5 Stepping Register Information

3 6 Suggested Sources for 80960CA Accessories

4 0 ELECTRICAL SPECIFICATIONS

4 1 Absolute Maximum Ratings

4 2 Operating Conditions

4 3 Recommended Connections

4 4 DC Specifications

4 5 AC Specifications

4 5 1 AC Test Conditions

4 5 2 AC Timing Waveforms

4 5 3 Derating Curves

5 0 RESET BACKOFF AND HOLD ACKNOWLEDGE

6 0 BUS WAVEFORMS

7 0 REVISION HISTORY

CONTENTS

PAGE

LIST OF FIGURES

Figure 1

80960CA Block Diagram

Figure 2

80960CA PGA Pinout

View from Top (Pins Facing Down)

Figure 3

80960CA PGA Pinout

View from Bottom (Pins Facing Up)

Figure 4

Measuring 80960CA PGA Case Temperature

Figure 5

Figure 6

AC Test Load

Figure 7

Input and Output Clocks Waveform

Figure 8

CLKIN Waveform

Figure 9

Output Delay and Float Waveform

Figure 10 Input Setup and Hold Waveform

Figure 11 NMI XINT7 0 Input Setup and Hold Waveform

Figure 12 Hold Acknowledge Timings

Figure 13 Bus Backoff (BOFF) Timings

Figure 14 Relative Timings Waveforms

Figure 15 Output Delay or Hold vs Load Capacitance

Figure 16 Rise and Fall Time Derating at Highest Operating Temperature

and Minimum V

Figure 17 I

vs Frequency and Temperature

Figure 18 Cold Reset Waveform

Figure 19 Warm Reset Waveform

Figure 20 Entering the ONCE State

Figure 21 Clock Synchronization in the 2-x Clock Mode

Figure 22 Clock Synchronization in the 1-x Clock Mode

Figure 23 Non-Burst Non-Pipelined Requests without Wait States

Figure 24 Non-Burst Non-Pipelined Read Request with Wait States

Figure 25 Non-Burst Non-Pipelined Write Request with Wait States

Figure 26 Burst Non-Pipelined Read Request without Wait States 32-Bit Bus

Figure 27 Burst Non-Pipelined Read Request with Wait States 32-Bit Bus

Figure 28 Burst Non-Pipelined Write Request without Wait States 32-Bit Bus

Figure 29 Burst Non-Pipelined Write Request with Wait States 32-Bit Bus

Figure 30 Burst Non-Pipelined Read Request with Wait States 16-Bit Bus

Figure 31 Burst Non-Pipelined Read Request with Wait States 8-Bit Bus

Figure 32 Non-Burst Pipelined Read Request without Wait States 32-Bit Bus

Figure 33 Non-Burst Pipelined Read Request with Wait States 32-Bit Bus

Figure 34 Burst Pipelined Read Request without Wait States 32-Bit Bus

Figure 35 Burst Pipelined Read Request with Wait States 32-Bit Bus

Figure 36 Burst Pipelined Read Request with Wait States 16-Bit Bus

Figure 37 Burst Pipelined Read Request with Wait States 8-Bit Bus

CONTENTS

PAGE

LIST OF FIGURES

(Continued)

Figure 38 Using External READY

Figure 39 Terminating a Burst with BTERM

Figure 40 BOFF Functional Timing

Figure 41 HOLD Functional Timing

Figure 42 DREQ and DACK Functional Timing

Figure 43 EOP Functional Timing

Figure 44 Terminal Count Functional Timing

Figure 45 FAIL Functional Timing

Figure 46 A Summary of Aligned and Unaligned Transfers for Little Endian Regions

Figure 47 A Summary of Aligned and Unaligned Transfers for Little Endian Regions

(Continued)

Figure 48 Idle Bus Operation

LIST OF TABLES

Table 1

80960CA Instruction Set

Table 2

Pin Description Nomenclature

Table 3

80960CA Pin Description

External Bus Signals

Table 4

80960CA Pin Description

Processor Control Signals

Table 5

80960CA Pin Description

DMA and Interrupt Unit Control Signals

Table 6

80960CA PGA Pinout

In Signal Order

Table 7

80960CA PGA Pinout

In Pin Order

Table 8

Maximum T

at Various Airflows in C

Table 9

80960CA PGA Package Thermal Characteristics

Table 10 Die Stepping Cross Reference

Table 11 Operating Conditions (80960CA-25 -16)

Table 12 DC Characteristics

Table 13 80960CA AC Characteristics (25 MHz)

Table 14 80960CA AC Characteristics (16 MHz)

Table 15 Reset Conditions

Table 16 Hold Acknowledge and Backoff Conditions

SPECIAL ENVIRONMENT 80960CA-25 -16

1 0 PURPOSE

This document provides electrical characteristics for
the 25 and 16 MHz versions of the 80960CA For a
detailed description of any 80960CA functional
topic

other than parametric performance

consult

the

80960CA Product Overview

(Order No 270669)

or the

i960

CA Microprocessor User's Manual

(Or-

der No 270710) To obtain data sheet updates and
errata please call Intel's FaxBACK

data-on-de-

mand system (1-800-628-2283 or 916-356-3105)
Other information can be obtained from Intel's tech-
nical BBS (916-356-3600)

2 0 80960CA OVERVIEW

The 80960CA is the second-generation member of
the 80960 family of embedded processors The
80960CA is object code compatible with the 32-bit
80960 Core Architecture while including Special
Function Register extensions to control on-chip pe-
ripherals and instruction set extensions to shift
64-bit operands and configure on-chip hardware
Multiple 128-bit internal buses on-chip instruction
caching and a sophisticated instruction scheduler al-
low the processor to sustain execution of two in-
structions every clock and peak at execution of
three instructions per clock

A 32-bit demultiplexed and pipelined burst bus pro-
vides a 132 Mbyte s bandwidth to a system's high-
speed external memory sub-system In addition the
80960CA's on-chip caching of instructions proce-
dure context and critical program data substantially
decouple system performance from the wait states
associated with accesses to the system's slower
cost sensitive main memory subsystem

The 80960CA bus controller integrates full wait state
and bus width control for highest system perform-
ance with minimal system design complexity Un-
aligned access and Big Endian byte order support
reduces the cost of porting existing applications to
the 80960CA

The processor also integrates four complete data-
chaining DMA channels and a high-speed interrupt
controller on-chip DMA channels perform single-
cycle or two-cycle transfers data packing and un-
packing and data chaining Block transfers

in addi-

tion to source or destination synchronized trans-
fers

are provided

The interrupt controller provides full programmability
of 248 interrupt sources into 32 priority levels with a
typical interrupt task switch (``latency'') time of
750 ns

271327 � 1

Figure 1 80960CA Block Diagram

SPECIAL ENVIRONMENT 80960CA-25 -16

2 1 The C-Series Core

The C-Series core is a very high performance micro-
architectural implementation of the 80960 Core Ar-
chitecture The C-Series core can sustain execution
of two instructions per clock (50 MIPs at 25 MHz)
To achieve this level of performance Intel has incor-
porated state-of-the-art silicon technology and inno-
vative microarchitectural constructs into the imple-
mentation of the C-Series core Factors that contrib-
ute to the core's performance include

Parallel instruction decoding allows issuance of
up to three instructions per clock

Single-clock execution of most instructions

Parallel instruction decode allows sustained
simultaneous execution of two single-clock in-
structions every clock cycle

Efficient instruction pipeline minimizes pipeline
break losses

Branch look-ahead and prediction allows many
branches to execute with no pipeline break

Local Register Cache integrated on-chip caches
Call Return context

Two-way set associative 1 Kbyte integrated in-
struction cache

1 Kbyte integrated Data RAM sustains a four-
word (128-bit) access every clock cycle

2 2 Pipelined Burst Bus

A 32-bit high performance bus controller interfaces
the 80960CA to external memory and peripherals
The Bus Control Unit features a maximum transfer
rate of 100 Mbytes per second (at 25 MHz) Internal-
ly programmable wait states and 16 separately con-
figurable memory regions allow the processor to in-
terface with a variety of memory subsystems with a
minimum of system complexity and a maximum of
performance The Bus Controller's main features in-
clude

Demultiplexed Burst Bus to exploit most efficient
DRAM access modes

Address Pipelining to reduce memory cost while
maintaining performance

32- 16- and 8-bit modes for I O interfacing ease

Full internal wait state generation to reduce sys-
tem cost

Little and Big Endian support to ease application
development

Unaligned access support for code portability

Three-deep request queue to decouple the bus
from the core

2 3 Flexible DMA Controller

A four-channel DMA controller provides high speed
DMA control for data transfers involving peripherals
and memory The DMA provides advanced features
such as data chaining byte assembly and disassem-
bly and a high performance fly-by mode capable of
transfer speeds of up to 45 Mbytes per second at
25 MHz The DMA controller features a performance
and flexibility which is only possible by integrating
the DMA controller and the 80960CA core

2 4 Priority interrupt Controller

A programmable-priority interrupt controller man-
ages up to 248 external sources through the 8-bit
external interrupt port The interrupt Unit also han-
dles the four internal sources from the DMA control-
ler and a single non-maskable interrupt input The
8-bit interrupt port can also be configured to provide
individual interrupt sources that are level or edge
triggered

Interrupts in the 80960CA are prioritized and sig-
naled within 270 ns of the request If the interrupt is
of higher priority than the processor priority the con-
text switch to the interrupt routine typically is com-
plete in another 480 ns The interrupt unit provides
the mechanism for the low latency and high through-
put interrupt service which is essential for embedded
applications

SPECIAL ENVIRONMENT 80960CA-25 -16

2 5 Instruction Set Summary

Table 1 summarizes the 80960CA instruction set by logical groupings See the

i960

CA Microprocessor

User's Manual

for a complete description of the instruction set

Table 1 80960CA Instruction Set

Data

Arithmetic

Logical

Bit and Bit Field

Movement

and Byte

Load

Add

And

Set Bit

Store

Subtract

Not And

Clear Bit

Move

Multiply

And Not

Not Bit

Load Address

Divide

Alter Bit

Remainder

Exclusive Or

Scan For Bit

Modulo

Not Or

Span Over Bit

Shift

Or Not

Extract

Extended Shift

Nor

Modify

Extended Multiply

Exclusive Nor

Scan Byte for Equal

Extended Divide

Not

Add with Carry

Nand

Subtract with Carry
Rotate

Comparison

Branch

Call Return

Fault

Compare

Unconditional Branch

Call

Conditional Fault

Conditional Compare

Conditional Branch

Call Extended

Synchronize Faults

Compare and Increment

Compare and Branch

Call System

Compare and Decrement

Return

Test Condition Code

Branch and Link

Check Bit

Debug

Processor

Atomic

Management

Modify Trace Controls

Flush Local Registers

Atomic Add

Mark

Modify Arithmetic Controls

Atomic Modify

Force Mark

Modify Process Controls

System Control
DMA Control

NOTES
Instructions marked by ( ) are 80960CA extensions to the 80960 instruction set

SPECIAL ENVIRONMENT 80960CA-25 -16

3 0 PACKAGE INFORMATION

3 1 Package Introduction

This section describes the pins pinouts and thermal
characteristics for the 80960CA in the 168-pin Ce-
ramic Pin Grid Array (PGA) package For complete
package specifications and information

see the

Packaging

Handbook (Order No 240800)

3 2 Pin Descriptions

The 80960CA pins are described in this section Ta-
ble 2 presents the legend for interpreting the pin de-
scriptions in the following tables Pins associated
with the 32-bit demultiplexed processor bus are de-
scribed in Table 3 Pins associated with basic proc-
essor configuration and control are described in Ta-
ble 4 Pins associated with the 80960CA DMA Con-
troller and Interrupt Unit are described in Table 5

All pins float while the processor is in the ONCE
mode

Table 2 Pin Description Nomenclature

Symbol

Description

Input only pin

Output only pin

I O

Pin can be either an input or output

Pins ``must be'' connected as described

S( )

Synchronous Inputs must meet setup
and hold times relative to PCLK2 1 for
proper operation All outputs are
synchronous to PCLK2 1

S(E)

Edge sensitive input

S(L)

Level sensitive input

A( )

Asynchronous Inputs may be
asynchronous to PCLK2 1

A(E)

Edge sensitive input

A(L)

Level sensitive input

H( )

While the processor's bus is in the Hold
Acknowledge or Bus Backoff state the
pin

H(1)

is driven to V

H(0)

is driven to V

H(Z)

floats

H(Q) continues to be a valid input

R( )

While the processor's RESET pin is low
the pin

R(1)

is driven to V

R(0)

is driven to V

R(Z)

floats

R(Q) continues to be a valid output

SPECIAL ENVIRONMENT 80960CA-25 -16

Table 3 80960CA Pin Description

External Bus Signals

Name

Type

Description

A31 2

ADDRESS BUS

carries the physical address' upper 30 bits A31 is the most

significant address bit A2 is the least significant During a bus access A31 2

identify all external addresses to word (4-byte) boundaries The byte enable signals

H(Z)

indicate the selected byte in each word During burst accesses A3 2 increment to

R(Z)

indicate successive data cycles

D31 0

I O

DATA BUS

carries 32- 16- or 8-bit data quantities depending on bus width

configuration The least significant bit of the data is carried on D0 and the most

S(L)

significant on D31 When the bus is configured for 8-bit data the lower 8 data lines

H(Z)

D7 0 are used For 16-bit data bus widths D15 0 are used For 32 bit bus widths the

R(Z)

full data bus is used

BE3 0

BYTE ENABLES

select which of the four bytes addressed by A31 2 are active

during an access to a memory region configured for a 32-bit data-bus width BE3

applies to D31 24 BE2 applies to D23 16 BE1 applies to D15 8 BE0 applies to

H(Z)

D7 0

R(1)

32-bit bus

BE3

Byte Enable 3

enable D31 24

BE2

Byte Enable 2

enable D23 16

BE1

Byte Enable 1

enable D15 8

BE0

Byte Enable 0

enable D7 0

For accesses to a memory region configured for a 16-bit data-bus width the
processor uses the BE3 BE1 and BE0 pins as BHE A1 and BLE respectively

16-bit bus

BE3

Byte High Enable (BHE)

enable D15 8

BE2

Not used (driven high or low)

BE1

Address Bit 1 (A1)

BE0

Byte Low Enable (BLE)

enable D7 0

For accesses to a memory region configured for an 8-bit data-bus width the
processor uses the BE1 and BE0 pins as A1 and A0 respectively

8-bit bus

BE3

Not used (driven high or low)

BE2

Not used (driven high or low)

BE1

Address Bit 1 (A1)

BE0

Address Bit 0 (A0)

W R

WRITE READ

is asserted for read requests and deasserted for write requests The

W R signal changes in the same clock cycle as ADS It remains valid for the entire

access in non-pipelined regions In pipelined regions W R is not guaranteed to be

H(Z)

valid in the last cycle of a read access

R(0)

ADS

ADDRESS STROBE

indicates a valid address and the start of a new bus access

ADS is asserted for the first clock of a bus access

H(Z)

R(1)

SPECIAL ENVIRONMENT 80960CA-25 -16

Table 3 80960CA Pin Description

External Bus Signals

(Continued)

Name

Type

Description

READY

is an input which signals the termination of a data transfer READY is

used to indicate that read data on the bus is valid or that a write-data transfer

S(L)

has completed The READY signal works in conjunction with the internally

H(Z)

programmed wait-state generator If READY is enabled in a region the pin is

R(Z)

sampled after the programmed number of wait-states has expired If the
READY pin is deasserted wait states continue to be inserted until READY
becomes asserted This is true for the N

RAD

RDD

WAD

and N

WDD

wait

states The N

XDA

wait states cannot be extended

BTERM

BURST TERMINATE

is an input which breaks up a burst access and causes

another address cycle to occur The BTERM signal works in conjunction with

S(L)

the internally programmed wait-state generator If READY and BTERM are

H(Z)

enabled in a region the BTERM pin is sampled after the programmed number

R(Z)

of wait states has expired When BTERM is asserted a new ADS signal is
generated and the access is completed The READY input is ignored when
BTERM is asserted BTERM must be externally synchronized to satisfy
BTERM setup and hold times

WAIT

indicates internal wait state generator status WAIT is asserted when

wait states are being caused by the internal wait state generator and not by

the READY or BTERM inputs WAIT can be used to derive a write-data

H(Z)

strobe WAIT can also be thought of as a READY output that the processor

R(1)

provides when it is inserting wait states

BLAST

BURST LAST

indicates the last transfer in a bus access BLAST is asserted

in the last data transfer of burst and non-burst accesses after the wait state

counter reaches zero BLAST remains asserted until the clock following the

H(Z)

last cycle of the last data transfer of a bus access If the READY or BTERM

R(0)

input is used to extend wait states the BLAST signal remains asserted until
READY or BTERM terminates the access

DT R

DATA TRANSMIT RECEIVE

indicates direction for data transceivers DT R

is used in conjunction with DEN to provide control for data transceivers

attached to the external bus When DT R is asserted the signal indicates that

H(Z)

the processor receives data Conversely when deasserted the processor

R(0)

sends data DT R changes only while DEN is high

DEN

DATA ENABLE

indicates data cycles in a bus request DEN is asserted at the

start of the bus request first data cycle and is deasserted at the end of the last

data cycle DEN is used in conjunction with DT R to provide control for data

H(Z)

transceivers attached to the external bus DEN remains asserted for

R(1)

sequential reads from pipelined memory regions DEN is deasserted when
DT R changes

LOCK

BUS LOCK

indicates that an atomic read-modify-write operation is in

progress LOCK may be used to prevent external agents from accessing

memory which is currently involved in an atomic operation LOCK is asserted

H(Z)

in the first clock of an atomic operation and deasserted in the clock cycle

R(1)

following the last bus access for the atomic operation To allow the most
flexibility for memory system enforcement of locked accesses the processor
acknowledges a bus hold request when LOCK is asserted The processor
performs DMA transfers while LOCK is active

HOLD

HOLD REQUEST

signals that an external agent requests access to the

external bus The processor asserts HOLDA after completing the current bus

S(L)

request HOLD HOLDA and BREQ are used together to arbitrate access to

H(Z)

the processor's external bus by external bus agents

R(Z)

SPECIAL ENVIRONMENT 80960CA-25 -16

Table 3 80960CA Pin Description

External Bus Signals

(Continued)

Name

Type

Description

BOFF

BUS BACKOFF

when asserted suspends the current access and causes

the bus pins to float When BOFF is deasserted the ADS signal is asserted

S(L)

on the next clock cycle and the access is resumed

H(Z)
R(Z)

HOLDA

HOLD ACKNOWLEDGE

indicates to a bus requestor that the processor has

relinquished control of the external bus When HOLDA is asserted the

external address bus data bus and bus control signals are floated HOLD

H(1)

BOFF HOLDA and BREQ are used together to arbitrate access to the

R(Q)

processor's external bus by external bus agents Since the processor grants
HOLD requests and enters the Hold Acknowledge state even while RESET is
asserted the state of the HOLDA pin is independent of the RESET pin

BREQ

BUS REQUEST

is asserted when the bus controller has a request pending

BREQ can be used by external bus arbitration logic in conjunction with HOLD

and HOLDA to determine when to return mastership of the external bus to the

H(Q)

processor

R(0)

D C

DATA OR CODE

is asserted for a data request and deasserted for instruction

requests D C has the same timing as W R

H(Z)
R(Z)

DMA

DMA ACCESS

indicates whether the bus request was initiated by the DMA

controller DMA is asserted for any DMA request DMA is deasserted for all

other requests

H(Z)
R(Z)

SUP

SUPERVISOR ACCESS

indicates whether the bus request is issued while in

supervisor mode SUP is asserted when the request has supervisor privileges

and is deasserted otherwise SUP can be used to isolate supervisor code and

H(Z)

data structures from non-supervisor requests

R(Z)

SPECIAL ENVIRONMENT 80960CA-25 -16

Table 4 80960CA Pin Description

Processor Control Signals

Name

Type

Description

RESET

causes the chip to reset When RESET is asserted all external signals return to

the reset state When RESET is deasserted initialization begins When the 2-x clock

A(L)

mode is selected RESET must remain asserted for 32 CLKIN cycles before being

H(Z)

deasserted to guarantee correct processor initialization When the 1-x clock mode is

R(Z)

selected RESET must remain asserted for 10 000 CLKIN cycles before being deasserted
to guarantee correct processor initialization The CLKMODE pin selects 1-x or 2-x input
clock division of the CLKIN pin
The processor's Hold Acknowledge bus state functions while the chip is reset If the
processor's bus is in the Hold Acknowledge state when RESET is asserted the processor
will internally reset but maintains the Hold Acknowledge state on external pins until the
Hold request is removed If a Hold request is made while the processor is in the reset
state the processor bus will grant HOLDA and enter the Hold Acknowledge state

FAIL

indicates failure of the processor's self-test performed at initialization When RESET

is deasserted and the processor begins initialization the FAIL pin is asserted An internal

self-test is performed as part of the initialization process If this self-test passes the FAIL

H(Q)

pin is deasserted otherwise it remains asserted The FAIL pin is reasserted while the

R(0)

processor performs an external bus self-confidence test If this self-test passes the
processor deasserts the FAIL pin and branches to the user's initialization routine
otherwise the FAIL pin remains asserted Internal self-test and the use of the FAIL pin can
be disabled with the STEST pin

STEST

SELF TEST

causes the processor's internal self-test feature to be enabled or disabled at

initialization STEST is read on the rising edge of RESET When asserted the processor's

S(L)

internal self-test and external bus confidence tests are performed during processor

H(Z)

initialization When deasserted only the bus confidence tests are performed during

R(Z)

initialization

ONCE

ON CIRCUIT EMULATION

when asserted causes all outputs to be floated ONCE is

continuously sampled while RESET is low and is latched on the rising edge of RESET To

A(L)

place the processor in the ONCE state

H(Z)

(1) assert RESET and ONCE (order does not matter)

R(Z)

(2) wait for at least 16 CLKIN periods in 2-x mode

or 10 000 CLKIN periods in 1-x

mode

after V

and CLKIN are within operating specifications

(3) deassert RESET
(4) wait at least 32 CLKIN periods

(The processor will now be latched in the ONCE state as long as RESET is high )
To exit the ONCE state bring V

and CLKIN to operating conditions then assert RESET

and bring ONCE high prior to deasserting RESET
CLKIN must operate within the specified operating conditions of the processor until Step 4
above has been completed CLKIN may then be changed to DC to achieve the lowest
possible ONCE mode leakage current
ONCE can be used by emulator products or for board testers to effectively make an
installed processor transparent in the board

SPECIAL ENVIRONMENT 80960CA-25 -16

Table 4 80960CA Pin Description

Processor Control Signals

(Continued)

Name

Type

Description

CLKIN

CLOCK INPUT

is an input for the external clock needed to run the processor The

external clock is internally divided as prescribed by the CLKMODE pin to produce

A(E)

PCLK2 1

H(Z)
R(Z)

CLKMODE

CLOCK MODE

selects the division factor applied to the external clock input (CLKIN)

When CLKMODE is high CLKIN is divided by one to create PCLK2 1 and the

A(L)

processor's internal clock When CLKMODE is low CLKIN is divided by two to create

H(Z)

PCLK2 1 and the processor's internal clock CLKMODE should be tied high or low in a

R(Z)

system as the clock mode is not latched by the processor If left unconnected the
processor will internally pull the CLKMODE pin low enabling the 2-x clock mode

PCLK2 1

PROCESSOR OUTPUT CLOCKS

provide a timing reference for all processor inputs

and outputs All input and output timings are specified in relation to PCLK2 and

PCLK1 PCLK2 and PCLK1 are identical signals Two output pins are provided to allow

H(Q)

flexibility in the system's allocation of capacitive loading on the clock PCLK2 1 may

R(Q)

also be connected at the processor to form a single clock signal

GROUND

connections must be connected externally to a V

board plane

POWER

connections must be connected externally to a V

board pane

CCPLL

is a separate V

supply pin for the phase lock loop used in 1-x clock mode

Connecting a simple lowpass filter to V

CCPLL

may help reduce clock jitter (T

) in

noisy environments Otherwise V

CCPLL

should be connected to V

This pin is

implemented starting with the D-stepping See Table 13 for die stepping information

NO CONNECT

pins must not be connected in a system

SPECIAL ENVIRONMENT 80960CA-25 -16

Table 5 80960CA Pin Description

DMA and Interrupt Unit Control Signals

Name

Type

Description

DREQ3 0

DMA REQUEST

causes a DMA transfer to be requested Each of the four

signals requests a transfer on a single channel DREQ0 requests channel 0

A(L)

DREQ1 requests channel 1 etc When two or more channels are requested

H(Z)

simultaneously the channel with the highest priority is serviced first The

R(Z)

channel priority mode is programmable

DACK3 0

DMA ACKNOWLEDGE

indicates that a DMA transfer is being executed

Each of the four signals acknowledges a transfer for a single channel DACK0

acknowledges channel 0 DACK1 acknowledges channel 1 etc DACK3 0 are

H(1)

asserted when the requesting device of a DMA is accessed

R(1)

EOP TC3 0

I O

END OF PROCESS TERMINAL COUNT

can be programmed as either an

input (EOP3 0) or as an output (TC3 0) but not both Each pin is individually

A(L)

programmable When programmed as an input EOPx causes the termination

H(Z Q)

of a current DMA transfer for the channel corresponding to the EOPx pin

R(Z)

EOP0 corresponds to channel 0 EOP1 corresponds to channel 1 etc When
a channel is configured for source

and

destination chaining the EOP pin for

that channel causes termination of only the current buffer transferred and
causes the next buffer to be transferred EOP3 0 are asynchronous inputs
When programmed as an output the channel's TCx pin indicates that the
channel byte count has reached 0 and a DMA has terminated TCx is driven
with the same timing as DACKx during the last DMA transfer for a buffer If the
last bus request is executed as multiple bus accesses TCx will stay asserted
for the entire bus request

XINT7 0

EXTERNAL INTERRUPT PINS

cause interrupts to be requested These pins

can be configured in three modes

A(E L)

Dedicated Mode

each pin is a dedicated external interrupt source

H(Z)

Dedicated inputs can be individually programmed to

R(Z)

be level (low) or edge (falling) activated

Expanded Mode

the eight pins act together as an 8-bit vectored
interrupt source The interrupt pins in this mode are
level activated Since the interrupt pins are active low
the vector number requested is the one's
complement of the positive logic value place on the
port This eliminates glue logic to interface to
combinational priority encoders which output
negative logic

Mixed Mode

XINT7 5 are dedicated sources and XINT4 0 act as
the five most significant bits of an expanded mode
vector The least significant bits are set to 010
internally

NMI

NON-MASKABLE INTERRUPT

causes a non-maskable interrupt event to

occur NMI is the highest priority interrupt recognized NMI is an edge (falling)

A(E)

activated source

H(Z)
R(Z)

SPECIAL ENVIRONMENT 80960CA-25 -16

3 3 80960CA Mechanical Data

3 3 1 80960CA PGA Pinout

Tables 6 and 7 list the 80960CA pin names with
package location Figure 2 depicts the complete
80960CA PGA pinout as viewed from the top side of

the component (i e

pins facing down) Figure 3

shows the complete 80960CA PGA pinout as
viewed from the pin-side of the package (i e

pins

facing up) See Section 4 0 ELECTRICAL SPECI-
FICATIONS

for specifications and recommended

connections

Table 6 80960CA PGA Pinout

In Signal Order

Address Bus

Data Bus

Bus Control

Processor Control

I O

Signal

A31

S15

D31

BE3

RESET

A16

DREQ3

A30

Q13

D30

BE2

DREQ2

A29

R14

D29

BE1

FAIL

DREQ1

A28

Q14

D28

BE0

DREQ0

A27

S16

D27

STEST

A26

R15

D26

W R

S10

DACK3

A10

A25

S17

D25

ONCE

DACK2

A24

Q15

D24

ADS

DACK1

A23

R16

D23

CLKIN

C13

DACK0

A22

R17

D22

READY

CLKMODE

C14

A21

Q16

D21

BTERM

PLCK1

B14

EOP TC3

A14

A20

P15

D20

PLCK2

B13

EOP TC2

A13

A19

P16

D19

WAIT

S12

EOP TC1

A12

A18

Q17

D18

BLAST

EOP TC0

A11

A17

P17

D17

Location

A16

N16

D16

DT R

S11

Q8 Q9 Q10 Q11

L15 M3 M15 Q7

J15 K3 K15 L3

G15 H3 H15 J3

C11 C12 F15 G3

C7 C8 C9 C10

XINT7

C17

A15

N17

D15

DEN

XINT6

C16

A14

M17

D14

XINT5

B17

A13

L16

D13

LOCK

S14

XINT4

C15

A12

L17

D12

XINT3

B16

A11

K17

D11

XINT2

A17

A10

J17

D10

HOLD

Location

XINT1

A15

H17

HOLDA

R8 R10 R11

N3 N15 Q6 R7

K2 K16 M2 M16

G2 H16 J2 J16

C6 E15 F3 F16

B7 B9 B11 B12

XINT0

B15

G17

BREQ

R13

G16

NMI

D15

F17

D C

S13

E17

DMA

R12

E16

SUP

Q12

CCPLL

B10

D17

No Connect

D16

BOFF

Location

B4 C4 C5 D3

A1 A3 A4 A5 B3

SPECIAL ENVIRONMENT 80960CA-25 -16

Table 7 80960CA PGA Pinout

In Pin Order

Signal

D16

D24

FAIL

D27

ONCE

D31

G15

M15

BTERM

G16

M16

HOLD

DREQ1

G17

M17

A14

ADS

DREQ3

DACK1

D11

D17

DACK2

D10

D18

BE0

A10

DACK3

C10

R10

A11

EOP TC0

C11

H15

N15

R11

A12

EOP TC1

C12

H16

N16

A16

R12

DMA

A13

EOP TC2

C13

CLKIN

H17

N17

A15

R13

BREQ

A14

EOP TC3

C14

CLKMODE

R14

A29

A15

XINT1

C15

XINT4

D12

D19

R15

A26

A16

RESET

C16

XINT6

D20

R16

A23

A17

XINT2

C17

XINT7

D22

R17

A22

J15

P15

A20

BOFF

J16

P16

A19

D25

STEST

J17

A10

P17

A17

D29

READY

D15

NMI

D13

D21

HOLDA

DREQ0

D16

D23

BE3

DREQ2

D17

D26

BE2

K15

Q28

BE1

DACK0

K16

D30

BLAST

K17

A11

DEN

B10

CCPLL

S10

W R

B11

E15

D15

S11

DT R

B12

E16

D14

S12

WAIT

B13

PCLK2

E17

Q10

S13

D C

B14

PCLK1

L15

Q11

S14

LOCK

B15

XINT0

L16

A13

Q12

SUP

S15

A31

B16

XINT3

L17

A12

Q13

A30

S16

A27

B17

XINT5

Q14

A28

S17

A25

F15

Q15

A24

F16

Q16

A21

F17

Q17

A18

SPECIAL ENVIRONMENT 80960CA-25 -16

3 4 Package Thermal Specifications

The 80960CA is specified for operation when T

(case temperature) is within the range of b40 C �

110 C T

may be measured in any environment

to determine whether the 80960CA is within speci-
fied operating range Case temperature should be
measured at the center of the top surface opposite
the pins Refer to Figure 4

(ambient temperature) can be calculated from

(thermal resistance from case to ambient) using

the following equation

P i

Table 8 shows the maximum T

allowable (without

exceeding T

) at various airflows and operating fre-

quencies (f

PCLK

)

Note that T

is greatly improved by attaching fins or

a heatsink to the package P (maximum power con-
sumption) is calculated by using the typical I

tabulated in Section 4 4 DC Specifications and
V

of 5V

271327 � 4

Figure 4 Measuring 80960CA PGA Case Temperature

Table 8 Maximum T

at Various Airflows in C

Airflow-ft min (m sec)

PCLK

200

400

600

800

1000

(MHz)

(0)

(1 01)

(2 03)

(3 04)

(4 06)

(5 07)

with

Heatsink

without

Heatsink

NOTES
0 285

high undirectional heatsink (Al alloy 6061 50 mil fin width 150 mil center-to-center fin spacing)

SPECIAL ENVIRONMENT 80960CA-25 -16

3 5 Stepping Register Information

Upon reset register g0 contains die stepping infor-
mation Figure 5 shows how g0 is configured The
most significant byte contains an ASCII 0 The upper
middle byte contains an ASCII C The lower middle
byte contains an ASCII A The least significant byte
contains the stepping number in ASCII g0 retains
this information until it is overwritten by the user pro-
gram

ASCII

Stepping Number

DECIMAL

Stepping Number

MSB

LSB

Figure 5 Register g0

Table 10 contains a cross reference of the number
in the least significant byte of register g0 to the die
stepping number

Table 10 Die Stepping Cross Reference

g0 Least Significant

Die Stepping

Byte

C-1

C-2 C-3

3 6 Suggested Sources for 80960CA

Accessories

The following is a list of suggested sources for
80960CA accessories This is not an endorsement
of any kind nor is it a warranty of the performance of
any of the listed products and or companies

Sockets

1 3M Textool Test and Interconnection

Products Department
P O Box 2963
Austin TX 78769-2963

2 Augat Inc

Interconnection Products Group
33 Perry Avenue
P O Box 779
Attleboro MA 02703
(508) 699-7646

3 Concept Manufacturing Inc

(Decoupling Sockets)
41484 Christy Street
Fremont CA 94538
(415) 651-3804

Heatsinks Fins

1 Thermalloy Inc

2021 West Valley View Lane
Dallas TX 75234-8993
(214) 243-4321
FAX (214) 241-4656

2 E G

G Division

60 Audubon Road
Wakefield MA 01880
(617) 245-5900

SPECIAL ENVIRONMENT 80960CA-25 -16

4 0 ELECTRICAL SPECIFICATIONS

4 1 Absolute Maximum Ratings

Storage Temperature

65 C to a150 C

Case Temperature Under Bias

40 C to a110 C

Supply Voltage

with Respect to V

0 5V to a6 5V

Voltage on Other Pins

with Respect to V

0 5V to V

0 5V

NOTICE This is a production data sheet The specifi-
cations are subject to change without notice

WARNING Stressing the device beyond the ``Absolute

Maximum Ratings'' may cause permanent damage
These are stress ratings only Operation beyond the
``Operating Conditions'' is not recommended and ex-
tended exposure beyond the ``Operating Conditions''
may affect device reliability

4 2 Operating Conditions

Table 11 Operating Conditons (80960CA-25 -16)

Symbol

Parameter

Min

Max

Units

Notes

Supply Voltage

80960CA-25

4 50

5 50

80960CA-16

4 50

5 50

CLK2x

Input Clock Frequency (2-x Mode)

80960CA-25

MHz

80960CA-16

MHz

CLK1x

Input Clock Frequency (1-x Mode)

80960CA-25

MHz

(Note 1)

80960CA-16

MHz

Case Temperature Under Bias

PGA package

110

80960CA-25 -16

NOTES
1 When in the 1-x input clock mode CLKIN is an input to an internal phase-locked loop and must maintain a minimum
frequency of 8 MHz for proper processor operation However in the 1-x mode CLKIN may still be stopped when the
processor either is in a reset condition or is reset If CLKIN is stopped the specified RESET low time must be provided once
CLKIN restarts and has stabilized
2 Case temperatures are ``instant on''

4 3 Recommended Connections

Power and ground connections must be made to
multiple V

and V

(GND) pins Every 80960CA-

based circuit board should include power (V

) and

ground (V

) planes for power distribution Every

pin must be connected to the power plane and

every V

pin must be connected to the ground

plane Pins identified as ``NC'' must not be connect-
ed in the system

Liberal decoupling capacitance should be placed
near the 80960CA The processor can cause tran-
sient power surges when its numerous output buff-
ers transition particularly when connected to large
capacitive loads

Low inductance capacitors and interconnects are
recommended for best high frequency electrical per-
formance Inductance can be reduced by shortening
the board traces between the processor and decou-
pling capacitors as much as possible Capacitors
specifically designed for PGA packages will offer the
lowest possible inductance

For reliable operation always connect unused in-
puts to an appropriate signal level In particular any
unused interrupt (XINT NMI) or DMA (DREQ) input
should be connected to V

through a pull-up resis-

tor as should BTERM if not used Pull-up resistors
should be in the in the range of 20 KX for each pin
tied high If READY or HOLD are not used the un-
used input should be connected to ground N C
pins must always remain unconnected

Refer to

the

i960

CA Microprocessor User's Manual

(Order

Number 270710) for more information

SPECIAL ENVIRONMENT 80960CA-25 -16

4 4 DC Specifications

Table 12 DC Characteristics

(80960CA-25 -16 under the conditions described in Section 4 2 Operating Conditions )

Symbol

Parameter

Min

Max

Units

Notes

Input Low Voltage for all pins except RESET

0 3

0 8

Input High Voltage for all pins except RESET

2 0

0 3

Output Low Voltage

0 45

5 mA

Output High Voltage

e b

1 mA

2 4

e b

200 mA

0 5

ILR

Input Low Voltage for RESET

0 3

1 5

IHR

Input High Voltage for RESET

3 5

0 3

LI1

Input Leakage Current for each pin

except

BTERM ONCE DREQ3 0 STEST
EOP3 0 TC3 0 NMI XINT7 0 BOFF READY
HOLD CLKMODE

(1)

LI2

Input Leakage Current for
BTERM ONCE DREQ3 0 STEST
EOP3 0 TC3 0 NMI XINT7 0 BOFF

325

0 45V

(2)

LI3

Input Leakage Current for
READY HOLD CLKMODE

500

2 4V

(3 7)

Output Leakage Current

0 45

OUT

Supply Current (80960CA-25)

Max

750

(Note 4)

Typ

600

(Note 5)

Supply Current (80960CA-16)

Max

550

(Note 4)

Typ

400

(Note 5)

ONCE

ONCE-mode Supply Current

100

Input Capacitance for
CLKIN RESET ONCE
READY HOLD DREQ3 0 BOFF
XINT7 0 NMI BTERM CLKMODE

1 MHz

OUT

Output Capacitance of each output pin

1 MHz

(6)

I O

I O Pin Capacitance

1 MHz

NOTES
1 No pullup or pulldown
2 These pins have internal pullup resistors
3 These pins have internal pulldown resistors
4 Measured at worst case frequency V

and temperature with device operating and outputs loaded to the test conditions

described in Section 4 5 1 AC Test Conditions

5 I

Typical is not tested

6 Output Capacitance is the capacitive load of a floating output
7 CLKMODE pin has a pulldown resistor only when ONCE pin is deasserted

SPECIAL ENVIRONMENT 80960CA-25 -16

4 5 AC Specifications

Table 13 80960CA AC Characteristics (25 MHz)

(80960CA-25 only under conditions described in Section 4 2 Operating Conditions and Section 4 5 1
AC Test Conditions

)

Symbol

Parameter

Min

Max

Units

Notes

Input Clock

(1 9)

CLKIN Frequency

MHz

CLKIN Period

In 1-x Mode (f

CLK1x

)

125

(11)

In 2-x Mode (f

CLK2x

)

CLKIN Period Stability

In 1-x Mode (f

CLK1x

)

0 1%

(12)

CLKIN High Time

In 1-x Mode (f

CLK1x

)

62 5

(11)

In 2-x Mode (f

CLK2x

)

CLKIN Low Time

In 1-x Mode (f

CLK1x

)

62 5

(11)

In 2-x Mode (f

CLK2x

)

CLKIN Rise Time

CLKIN Fall Time

Output Clocks

(1 8)

CLKIN to PCLK2 1 Delay

In 1-x Mode (f

CLK1x

)

(3 12)

In 2-x Mode (f

CLK2x

)

(3)

PCLK2 1 Period

In 1-x Mode (f

CLK1x

)

(12)

In 2-x Mode (f

CLK2x

)

(3)

PCLK2 1 High Time

(T 2)

T 2

(12)

PCLK2 1 Low Time

(T 2)

T 2

(12)

PCLK2 1 Rise Time

(3)

PCLK2 1 Fall Time

(3)

Synchronous Outputs

(8)

Output Valid Delay Output Hold

(6 10)

OH1

OV1

A31 2

OH2

OV2

BE3 0

OH3

OV3

ADS

OH4

OV4

W R

OH5

OV5

D C SUP DMA

OH6

OV6

BLAST WAIT

OH7

OV7

DEN

OH8

OV8

HOLDA BREQ

OH9

OV9

LOCK

OH10

OV10

DACK3 0

OH11

OV11

D31 0

OH12

OV12

DT R

T 2

OH13

OV13

FAIL

OH14

OV14

EOP3 0 TC3 0

(6 10)

Output Float for all ouputs

(6)

Synchronous Inputs

(1 9 10)

Input Setup
T

IS1

D31 0

IS2

BOFF

IS3

BTERM READY

IS4

HOLD

Input Hold
T

IH1

D31 0

IH2

BOFF

IH3

BTERM READY

IH4

HOLD

SPECIAL ENVIRONMENT 80960CA-25 -16

Table 13 80960CA AC Characteristics (25 MHz)

(Continued)

(80960CA-25 only under conditions described in Section 4 2 Operating Conditions and Section 4 5 1
AC Test Conditions

)

Symbol

Parameter

Min

Max

Units

Notes

Relative Output Timings

(1 2 3 8)

AVSH1

A31 2 Valid to ADS Rising

AVSH2

BE3 0 W R SUP D C
DMA DACK3 0 Valid to ADS Rising

AVEL1

A31 2 Valid to DEN Falling

AVEL2

BE3 0 W R SUP INST
DMA DACK3 0 Valid to DEN Falling

NLQV

WAIT Falling to Output Data Valid

DVNH

Output Data Valid to WAIT Rising

N T

(4)

NLNH

WAIT Falling to WAIT Rising

N T

(4)

NHQX

Output Data Hold after WAIT Rising

1) T

(5)

EHTV

DT R Hold after DEN High

T 2

(6)

TVEL

DT R Valid to DEN Falling

T 2

Relative Input Timings

(1 2 3)

IS5

RESET Input Setup (2-x Clock Mode)

(13)

IH5

RESET Input Hold (2-x Clock Mode)

(13)

IS6

DREQ3 0 Input Setup

(7)

IH6

DREQ3 0 Input Hold

(7)

IS7

XINT7 0 NMI Input Setup

(15)

IH7

XINT7 0 NMI Input Hold

(15)

IS8

RESET Input Setup (1-x Clock Mode)

(14)

IH8

RESET Input Hold (1-x Clock Mode)

T 4

(14)

NOTES

1 See Section 4 5 2 AC Timing Waveforms for waveforms and definitions
2 See Figure 16 for capacitive derating information for output delays and hold times
3 See Figure 17 for capacitive derating information for rise and fall times
4 Where N is the number of N

RAD

RDD

WAD

or N

WDD

wait states that are programmed in the Bus Controller Region

Table WAIT never goes active when there are no wait states in an access

5 N

Number of wait states inserted with READY

6 Output Data and or DT R may be driven indefinitely following a cycle if there is no subsequent bus activity
7 Since asynchronous inputs are synchronized internally by the 80960CA they have no required setup or hold times to be

recognized and for proper operation However to guarantee recognition of the input at a particular edge of PCLK2 1
the setup times shown must be met Asynchronous inputs must be active for at least two consecutive PCLK2 1 rising
edges to be seen by the processor

8 These specifications are guaranteed by the processor
9 These specifications must be met by the system for proper operation of the processor

10 This timing is dependent upon the loading of PCLK2 1 Use the derating curves of Section 4 5 3 Derating Curves to

adjust the timing for PCLK2 1 loading

11 In the 1-x input clock mode the maximum input clock period is limited to 125 ns while the processor is operating When

the processor is in reset the input clock may stop even in 1-x mode

12 When in the 1-x input clock mode these specifications assume a stable input clock with a period variation of less than

0 1% between adjacent cycles

13 In 2-x clock mode RESET is an asynchronous input which has no required setup and hold time for proper operation

However to guarantee the device exits reset synchronized to a particular clock edge the RESET pin must meet setup
and hold times to the falling edge of the CLKIN (See Figure 21)

14 In 1-x clock mode RESET is an asynchronous input which has no required setup and hold time for proper operation

However to guarantee the device exits reset synchronized to a particular clock edge the RESET pin must meet setup
and hold times to the rising edge of the CLKIN (See Figure 22 )

15 The interrupt pins are synchronized internally by the 80960CA They have no required setup or hold times for proper

operation These pins are sampled by the interrupt controller every other clock and must be active for at least three
consecutive PCLK2 1 rising edges when asserting them asynchronously To guarantee recognition at a particular clock
edge the setup and hold times shown must be met for two consecutive PCLK2 1 rising edges

SPECIAL ENVIRONMENT 80960CA-25 -16

Table 14 80960CA AC Characteristics (16 MHz)

(80960CA-16 only under conditions described in Section 4 2 Operating Conditions and Section 4 5 1
AC Test Conditions

)

Symbol

Parameter

Min

Max

Units

Notes

Input Clock

(1 9)

CLKIN Frequency

MHz

CLKIN Period

In 1-x Mode (f

CLK1x

)

62 5

125

(11)

In 2-x Mode (f

CLK2x

)

31 25

CLKIN Period Stability

In 1-x Mode (f

CLK1x

)

0 1%

(12)

CLKIN High Time

In 1-x Mode (f

CLK1x

)

62 5

(11)

In 2-x Mode (f

CLK2x

)

CLKIN Low Time

In 1-x Mode (f

CLK1x

)

62 5

(11)

In 2-x Mode (f

CLK2x

)

CLKIN Rise Time

CLKIN Fall Time

Output Clocks

(1 8)

CLKIN to PCLK2 1 Delay

In 1-x Mode (f

CLK1x

)

(3 12)

In 2-x Mode (f

CLK2x

)

(3)

PCLK2 1 Period

In 1-x Mode (f

CLK1x

)

(12)

In 2-x Mode (f

CLK2x

)

(3)

PCLK2 1 High Time

(T 2)

T 2

(12)

PCLK2 1 Low Time

(T 2)

T 2

(12)

PCLK2 1 Rise Time

(3)

PCLK2 1 Fall Time

(3)

Synchronous Outputs

(8)

Output Valid Delay Output Hold

(6 10)

OH1

OV1

A31 2

OH2

OV2

BE3 0

OH3

OV3

ADS

OH4

OV4

W R

OH5

OV5

D C SUP DMA

OH6

OV6

BLAST WAIT

OH7

OV7

DEN

OH8

OV8

HOLDA BREQ

OH9

OV9

LOCK

OH10

OV10

DACK3 0

OH11

OV11

D31 0

OH12

OV12

DT R

T 2

OH13

OV13

FAIL

OH14

OV14

EOP3 0 TC3 0

(6 10)

Output Float for All Ouputs

(6)

Synchronous Inputs

(1 9 10)

Input Setup
T

IS1

D31 0

IS2

BOFF

IS3

BTERM READY

IS4

HOLD

Input Hold
T

IH1

D31 0

IH2

BOFF

IH3

BTERM READY

IH4

HOLD

SPECIAL ENVIRONMENT 80960CA-25 -16

Table 14 80960CA AC Characteristics (16 MHz)

(Continued)

(80960CA-16 only under conditions described in Section 4 2 Operating Conditions and Section 4 5 1
AC Test Conditions

)

Symbol

Parameter

Min

Max

Units

Notes

Relative Output Timings

(1 2 3 8)

AVSH1

A31 2 Valid to ADS Rising

AVSH2

BE3 0 W R SUP D C
DMA DACK3 0 Valid to ADS Rising

AVEL1

A31 2 Valid to DEN Falling

AVEL2

BE3 0 W R SUP INST
DMA DACK3 0 Valid to DEN Falling

NLQV

WAIT Falling to Output Data Valid

DVNH

Output Data Valid to WAIT Rising

N T

(4)

NLNH

WAIT Falling to WAIT Rising

N T

(4)

NHQX

Output Data Hold after WAIT Rising

1) T

(5)

EHTV

DT R Hold after DEN High

T 2

(6)

TVEL

DT R Valid to DEN Falling

T 2

Relative Input Timings

(1 2 3)

IS5

RESET Input Setup (2-x Clock Mode)

(13)

IH5

RESET Input Hold (2-x Clock Mode)

(13)

IS6

DREQ3 0 Input Setup

(7)

IH6

DREQ3 0 Input Hold

(7)

IS7

XINT7 0 NMI Input Setup

(15)

IH7

XINT7 0 NMI Input Hold

(15)

IS8

RESET Input Setup (1-x Clock Mode)

(14)

IH8

RESET Input Hold (1-x Clock Mode)

T 4

(14)

NOTES

RAD

RDD

WAD

or N

WDD

wait states that are programmed in the Bus Controller Region

Table WAIT never goes active when there are no wait states in an access

5 N

Number of wait states inserted with READY

8 These specifications are guaranteed by the processor
9 These specifications must be met by the system for proper operation of the processor

10 This timing is dependent upon the loading of PCLK2 1 Use the derating curves of Section 4 5 3 Derating Curves to

adjust the timing for PCLK2 1 loading

11 In the 1-x input clock mode the maximum input clock period is limited to 125 ns while the processor is operating When

the processor is in reset the input clock may stop even in 1-x mode

12 When in the 1-x input clock mode these specifications assume a stable input clock with a period variation of less than

0 1% between adjacent cycles

13 In 2-x clock mode RESET is an asynchronous input which has no required setup and hold time for proper operation

However to guarantee the device exits reset synchronized to a particular clock edge the RESET pin must meet setup
and hold times to the falling edge of the CLKIN (See Figure 21)

14 In 1-x clock mode RESET is an asynchronous input which has no required setup and hold time for proper operation

However to guarantee the device exits reset synchronized to a particular clock edge the RESET pin must meet setup
and hold times to the rising edge of the CLKIN (See Figure 22 )

15 The interrupt pins are synchronized internally by the 80960CA They have no required setup or hold times for proper

SPECIAL ENVIRONMENT 80960CA-25 -16

5 0 RESET BACKOFF AND HOLD

ACKNOWLEDGE

Table 15 lists the condition of each processor output
pin while RESET is asserted (low)

Table 15 Reset Conditions

Pins

State During Reset

(HOLDA Inactive)

A31 2

Floating

D31 0

Floating

BE3 0

Driven high (Inactive)

W R

Driven low (Read)

ADS

Driven high (Inactive)

WAIT

Driven high (Inactive)

BLAST

Driven low (Active)

DT R

Driven low (Receive)

DEN

Driven high (Inactive)

LOCK

Driven high (inactive)

BREQ

Driven low (Inactive)

D C

Floating

DMA

Floating

SUP

Floating

FAIL

Driven low (Active)

DACK3 0

Driven high (Inactive)

EOP3 0 TC3 0

Floating (Set to input mode)

NOTES
1 With regard to bus output pin state only the Hold Ac-

knowledge state takes precedence over the reset state
Although asserting the RESET pin will internally reset
the processor the processor's bus output pins will not
enter the reset state if it has granted Hold Acknowledge
to a previous HOLD request (HOLDA is active) Further-
more the processor will grant new HOLD requests and
enter the Hold Acknowledge state even while in reset

For example if HOLDA is inactive and the processor is
in the reset state then HOLD is asserted the process-
sor's bus pins enter the Hold Acknowledge state and
HOLDA is granted The processor will not be able to
perform memory accesses until the HOLD request is re-
moved even if the RESET pin is brought high This op-
eration is provided to simplify boot-up synchronization
among multiple processors sharing the same bus

Table 16 lists the condition of each processor output
pin while HOLDA is asserted (low)

Table 16 Hold Acknowledge and Backoff

Conditions

Pins

State During HOLDA

A31 2

Floating

D31 0

Floating

BE3 0

Floating

W R

Floating

ADS

Floating

WAIT

Floating

BLAST

Floating

DT R

Floating

DEN

Floating

LOCK

Floating

BREQ

Driven (High or low)

D C

Floating

DMA

Floating

SUP

Floating

FAIL

Driven high (Inactive)

DACK3 0

Driven high (Inactive)

EOP3 0 TC3 0

Driven (If output)

SPECIAL ENVIRONMENT 80960CA-25 -16

271327 � 42

NOTES
1 Case 1 DREQ must deassert before DACK deasserts Applications are Fly-By and some packing and unpacking

modes in which loads are followed by loads or stores are followed by stores

2 Case 2 DREQ must be deasserted by the second clock (rising edge) after DACK is driven high Applications are non

Fly-By transfers and adjacent load-stores or store-loads

3 DACKx is asserted for the duration of a DMA bus request The request may consist of multiple bus accesses (defined

by ADS and BLAST Refer to

i960

CA Microprocessor User's Manual for ``access'' ``request'' definitions

Figure 42 DREQ and DACK Functional Timing

271327 � 43

NOTE
EOP has the same AC Timing Requirements as DREQ to prevent unwanted DMA requests EOP is NOT edge triggered
EOP must be held for a minimum of 2 clock cycles then deasserted within 15 clock cycles

Figure 43 EOP Functional Timing

Электронный компонент: 80960CA-16

Document Outline