Document Outline
- Cover
- Contents
- 1.0 PURPOSE
- 2.0 80960CA OVERVIEW
- 3.0 PACKAGE INFORMATION
- 4.0 ELECTRICAL SPECIFICATIONS
- 5.0 RESET, BACKOFF AND HOLD ACKNOWLEDGE
- 6.0 BUS WAVEFORMS
- 7.0 REVISION HISTORY
- Figures
- Figure 1. 80960CA Block Diagram
- Figure 2. 80960CA PGA Pinout View from Top (Pins Facing Down)
- Figure 3. 80960CA PGA Pinout View from Bottom (Pins Facing Up)
- Figure 4. 80960CA PQFP Pinout (View from Top Side)
- Figure 5. Measuring 80960CA PGA and PQFP Case Temperature
- Figure 6. Register g0
- Figure 7. AC Test Load
- Figure 8. Input and Output Clocks Waveform
- Figure 9. CLKIN Waveform
- Figure 10. Output Delay and Float Waveform
- Figure 11. Input Setup and Hold Waveform
- Figure 12. NMI, XINT7:0 Input Setup and Hold Waveform
- Figure 13. Hold Acknowledge Timings
- Figure 14. Bus Backoff (BOFF) Timings
- Figure 15. Relative Timings Waveforms
- Figure 16. Output Delay or Hold vs. Load Capacitance
- Figure 17. Rise and Fall Time Derating at Highest Operating Temperature and Minimum V CC
- Figure 18. I CC vs. Frequency and Temperature
- Figure 19. Cold Reset Waveform
- Figure 20. Warm Reset Waveform
- Figure 21. Entering the ONCE State
- Figure 22. Clock Synchronization in the 2-x Clock Mode
- Figure 23. Clock Synchronization in the 1-x Clock Mode
- Figure 24. Non-Burst, Non-Pipelined Requests Without Wait States
- Figure 25. Non-Burst, Non-Pipelined Read Request With Wait States
- Figure 26. Non-Burst, Non-Pipelined Write Request With Wait States
- Figure 27. Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus
- Figure 28. Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus
- Figure 29. Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus
- Figure 30. Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus
- Figure 31. Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus
- Figure 32. Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus
- Figure 33. Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus
- Figure 34. Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus
- Figure 35. Burst, Pipelined Read Request Without Wait States, 32-Bit Bus
- Figure 36. Burst, Pipelined Read Request With Wait States, 32-Bit Bus
- Figure 37. Burst, Pipelined Read Request With Wait States, 16-Bit Bus
- Figure 38. Burst, Pipelined Read Request With Wait States, 8-Bit Bus
- Figure 39. Using External READY
- Figure 40. Terminating a Burst with BTERM
- Figure 41. BOFF Functional Timing
- Figure 42. HOLD Functional Timing
- Figure 43. DREQ and DACK Functional Timing
- Figure 44. EOP Functional Timing
- Figure 45. Terminal Count Functional Timing
- Figure 46. FAIL Functional Timing
- Figure 47. A Summary of Aligned and Unaligned Transfers for Little Endian Regions
- Figure 48. A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued)
- Figure 49. Idle Bus Operation
- Tables
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
INTEL CORPORATION, 1993
November 1993
Order Number: 270727-006
80960CA-33, -25, -16
32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
Two Instructions/Clock Sustained Execution
Four 59 Mbytes/s DMA Channels with Data Chaining
Demultiplexed 32-bit Burst Bus with Pipelining
s
32-bit Parallel Architecture
-- Two Instructions/clock Execution
-- Load/Store Architecture
-- Sixteen 32-bit Global Registers
-- Sixteen 32-bit Local Registers
-- Manipulates 64-bit Bit Fields
-- 11 Addressing Modes
-- Full Parallel Fault Model
-- Supervisor Protection Model
s
Fast Procedure Call/Return Model
-- Full Procedure Call in 4 Clocks
s
On-Chip Register Cache
-- Caches Registers on Call/Ret
-- Minimum of 6 Frames Provided
-- Up to 15 Programmable Frames
s
On-Chip Instruction Cache
-- 1 Kbyte Two-Way Set Associative
-- 128-bit Path to Instruction Sequencer
-- Cache-Lock Modes
-- Cache-Off Mode
s
High Bandwidth On-Chip Data RAM
-- 1 Kbyte On-Chip Data RAM
-- Sustains 128 bits per Clock Access
s
Four On-Chip DMA Channels
-- 59 Mbytes/s Fly-by Transfers
-- 32 Mbytes/s Two-Cycle Transfers
-- Data Chaining
-- Data Packing/Unpacking
-- Programmable Priority Method
s
32-Bit Demultiplexed Burst Bus
-- 128-bit Internal Data Paths to and
from Registers
-- Burst Bus for DRAM Interfacing
-- Address Pipelining Option
-- Fully Programmable Wait States
-- Supports 8-, 16- or 32-bit Bus Widths
-- Supports Unaligned Accesses
-- Supervisor Protection Pin
s
Selectable Big or Little Endian Byte
Ordering
s
High-Speed Interrupt Controller
-- Up to 248 External Interrupts
-- 32 Fully Programmable Priorities
-- Multi-mode 8-bit Interrupt Port
-- Four Internal DMA Interrupts
-- Separate, Non-maskable Interrupt Pin
-- Context Switch in 750 ns Typical
ii
CONTENTS
PAGE
1.0 PURPOSE .................................................................................................................................................. 1
2.0 80960CA OVERVIEW................................................................................................................................. 1
2.1 The C-Series Core ..............................................................................................................................2
2.2 Pipelined, Burst Bus ...........................................................................................................................2
2.3 Flexible DMA Controller ......................................................................................................................2
2.4 Priority Interrupt Controller ..................................................................................................................2
2.5 Instruction Set Summary ....................................................................................................................3
3.0 PACKAGE INFORMATION.........................................................................................................................4
3.1 Package Introduction ..........................................................................................................................4
3.2 Pin Descriptions .................................................................................................................................. 4
3.3 80960CA Mechanical Data ............................................................................................................... 11
3.3.1 80960CA PGA Pinout ............................................................................................................ 11
3.3.2 80960CA PQFP Pinout .......................................................................................................... 15
3.4 Package Thermal Specifications ...................................................................................................... 18
3.5 Stepping Register Information .......................................................................................................... 20
3.6 Suggested Sources for 80960CA Accessories.................................................................................. 20
4.0 ELECTRICAL SPECIFICATIONS............................................................................................................. 21
4.1 Absolute Maximum Ratings .............................................................................................................. 21
4.2 Operating Conditions ........................................................................................................................ 21
4.3 Recommended Connections ............................................................................................................ 21
4.4 DC Specifications ............................................................................................................................. 22
4.5 AC Specifications .............................................................................................................................. 23
4.5.1 AC Test Conditions ................................................................................................................ 29
4.5.2 AC Timing Waveforms ........................................................................................................... 29
4.5.3 Derating Curves ..................................................................................................................... 33
5.0 RESET, BACKOFF AND HOLD ACKNOWLEDGE ................................................................................. 35
6.0 BUS WAVEFORMS ................................................................................................................................. 36
7.0 REVISION HISTORY ................................................................................................................................ 64
80960CA-33, -25, -16
32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
iii
CONTENTS
PAGE
LIST OF FIGURES
Figure 1
80960CA Block Diagram .............................................................................................................. 1
Figure 2
80960CA PGA Pinout--View from Top (Pins Facing Down) ...................................................... 13
Figure 3
80960CA PGA Pinout --View from Bottom (Pins Facing Up) .................................................... 14
Figure 4
80960CA PQFP Pinout (View from Top Side) ............................................................................ 17
Figure 5
Measuring 80960CA PGA and PQFP Case Temperature .......................................................... 18
Figure 6
Register g0 ................................................................................................................................. 20
Figure 7
AC Test Load .............................................................................................................................. 29
Figure 8
Input and Output Clocks Waveform ............................................................................................ 29
Figure 9
CLKIN Waveform ........................................................................................................................ 29
Figure 10
Output Delay and Float Waveform ............................................................................................. 30
Figure 11
Input Setup and Hold Waveform ................................................................................................ 30
Figure 12
NMI, XINT7:0 Input Setup and Hold Waveform .......................................................................... 31
Figure 13
Hold Acknowledge Timings ........................................................................................................ 31
Figure 14
Bus Backoff (BOFF) Timings ...................................................................................................... 32
Figure 15
Relative Timings Waveforms ...................................................................................................... 33
Figure 16
Output Delay or Hold vs. Load Capacitance .............................................................................. 33
Figure 17
Rise and Fall Time Derating at Highest Operating Temperature and Minimum V
CC
.................. 34
Figure 18
I
CC
vs. Frequency and Temperature ........................................................................................... 34
Figure 19
Cold Reset Waveform ................................................................................................................ 36
Figure 20
Warm Reset Waveform .............................................................................................................. 37
Figure 21
Entering the ONCE State ........................................................................................................... 38
Figure 22
Clock Synchronization in the 2-x Clock Mode ............................................................................ 39
Figure 23
Clock Synchronization in the 1-x Clock Mode ............................................................................ 39
Figure 24
Non-Burst, Non-Pipelined Requests Without Wait States .......................................................... 40
Figure 25
Non-Burst, Non-Pipelined Read Request With Wait States ....................................................... 41
Figure 26
Non-Burst, Non-Pipelined Write Request With Wait States ....................................................... 42
Figure 27
Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus ........................................ 43
Figure 28
Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus ............................................. 44
Figure 29
Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus ....................................... 45
Figure 30
Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus ............................................. 46
Figure 31
Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus ............................................ 47
Figure 32
Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus ............................................... 48
Figure 33
Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ....................................... 49
Figure 34
Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus ............................................ 50
Figure 35
Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ............................................... 51
Figure 36
Burst, Pipelined Read Request With Wait States, 32-Bit Bus ..................................................... 52
Figure 37
Burst, Pipelined Read Request With Wait States, 16-Bit Bus ..................................................... 53
Figure 38
Burst, Pipelined Read Request With Wait States, 8-Bit Bus ....................................................... 54
iv
CONTENTS
PAGE
LIST OF FIGURES (continued)
Figure 39
Using External READY ............................................................................................................... 55
Figure 40
Terminating a Burst with BTERM ............................................................................................... 56
Figure 41
BOFF Functional Timing ............................................................................................................ 57
Figure 42
HOLD Functional Timing ............................................................................................................ 58
Figure 43
DREQ and DACK Functional Timing .......................................................................................... 59
Figure 44
EOP Functional Timing .............................................................................................................. 59
Figure 45
Terminal Count Functional Timing .............................................................................................. 60
Figure 46
FAIL Functional Timing ............................................................................................................... 60
Figure 47
A Summary of Aligned and Unaligned Transfers for Little Endian Regions ................................ 61
Figure 48
A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued) ............ 62
Figure 49
Idle Bus Operation ...................................................................................................................... 63
LIST OF TABLES
Table 1
80960CA Instruction Set .............................................................................................................. 3
Table 2
Pin Description Nomenclature ...................................................................................................... 4
Table 3
80960CA Pin Description -- External Bus Signals ...................................................................... 5
Table 4
80960CA Pin Description -- Processor Control Signals .............................................................. 8
Table 5
80960CA Pin Description -- DMA and Interrupt Unit Control Signals ....................................... 10
Table 6
80960CA PGA Pinout -- In Signal Order ................................................................................... 11
Table 7
80960CA PGA Pinout -- In Pin Order ........................................................................................ 12
Table 8
80960CA PQFP Pinout -- In Signal Order ................................................................................. 15
Table 9
80960CA PQFP Pinout -- In Pin Order ..................................................................................... 16
Table 10
Maximum T
A
at Various Airflows in
o
C (PGA Package Only) ..................................................... 18
Table 11
80960CA PGA Package Thermal Characteristics ...................................................................... 19
Table 12
80960CA PQFP Package Thermal Characteristics .................................................................... 19
Table 13
Die Stepping Cross Reference ................................................................................................... 20
Table 14
Operating Conditions (80960CA-33, -25, -16) ............................................................................ 21
Table 15
DC Characteristics ..................................................................................................................... 22
Table 16
80960CA AC Characteristics (33 MHz) ...................................................................................... 23
Table 17
80960CA AC Characteristics (25 MHz) ...................................................................................... 25
Table 18
80960CA AC Characteristics (16 MHz) ...................................................................................... 27
Table 19
Reset Conditions ........................................................................................................................ 35
Table 20
Hold Acknowledge and Backoff Conditions ................................................................................ 35
1
80960CA-33, -25, -16
1.0
PURPOSE
This document provides electrical characteristics for
the 33, 25 and 16 MHz versions of the 80960CA. For
a detailed description of any 80960CA functional
topic--other than parametric performance--consult
the 80960CA Product Overview (Order No. 270669)
or the i960
CA Microprocessor User's Manual
(Order No. 270710). To obtain data sheet updates
and errata, please call Intel's FaxBACK
data-on-
demand system (1-800-628-2283 or 916-356-3105).
Other information can be obtained from Intel's tech-
nical BBS (916-356-3600).
2.0
80960CA OVERVIEW
The 80960CA is the second-generation member of
the 80960 family of embedded processors. The
80960CA is object code compatible with the 32-bit
80960 Core Architecture while including Special
Function Register extensions to control on-chip
peripherals and instruction set extensions to shift 64-
bit operands and configure on-chip hardware.
Multiple 128-bit internal buses, on-chip instruction
caching and a sophisticated instruction scheduler
allow the processor to sustain execution of two
instructions every clock and peak at execution of
three instructions per clock.
A 32-bit demultiplexed and pipelined burst bus
provides a 132 Mbyte/s bandwidth to a system's
high-speed external memory sub-system. In
addition, the 80960CA's on-chip caching of instruc-
tions, procedure context and critical program data
substantially decouple system performance from the
wait states associated with accesses to the system's
slower, cost sensitive, main memory subsystem.
The 80960CA bus controller integrates full wait state
and bus width control for highest system perfor-
mance with minimal system design complexity.
Unaligned access and Big Endian byte order support
reduces the cost of porting existing applications to
the 80960CA.
The processor also integrates four complete data-
chaining DMA channels and a high-speed interrupt
controller on-chip. DMA channels perform: single-
cycle or two-cycle transfers, data packing and
unpacking and data chaining. Block transfers--in
addition to source or destination synchronized trans-
fers--are provided.
The interrupt controller provides full programmability
of 248 interrupt sources into 32 priority levels with a
typical interrupt task switch ("latency") time of
750 ns.
Figure 1. 80960CA Block Diagram
Execution
Unit
Programmable
Bus
Controller
Bus Request
Queues
Six-port
Register File
64-Bit
SRC1 Bus
64-Bit
SRC2 Bus
64-Bit
DST Bus
32-Bit
Base Bus
128-Bit
Load Bus
128-Bit
Store Bus
Instruction Prefetch Queue
Instruction Cache
(1 KByte, Two-way
Set Associative)
128-BIT CACHE BUS
Interrupt Controller
Control
Address
Data
Memory-side
Machine Bus
Register-side
Machine Bus
Parallel
Instruction
Scheduler
Memory Region
Configuration
Multiply/Divide
Unit
Four-Channel
DMA Controller
Interrupt
Port
1 KByte
5 to 15 Sets
Register Cache
Data RAM
Address
Generation Unit
F_CX001A
DMA
Port
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