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January 1995

INTEL CORPORATION 1995

Order Number 271328-001

SPECIAL ENVIRONMENT 80960CF-30 -25 -16
32-BIT HIGH-PERFORMANCE SUPERSCALAR

PROCESSOR

Socket and Object Code Compatible with 80960CA

Two Instructions Clock Sustained Execution

Four 59 Mbytes s DMA Channels with Data Chaining

Demultiplexed 32-bit Burst Bus with Pipelining

32-bit Parallel Architecture

Two Instructions clock Execution
Load Store Architecture
Sixteen 32-bit Global Registers
Sixteen 32-bit Local Registers
Manipulate 64-bit Bit Fields
11 Addressing Modes
Full Parallel Fault Model
Supervisor Protection Model

Fast Procedure Call Return Model

Full Procedure Call in 4 clocks

On-Chip Register Cache

Caches Registers on Call Ret
Minimum of 6 Frames provided
Up to 15 Programmable Frames

On-Chip Instruction Cache

4 Kbyte Two-Way Set Associative
128-bit Path to Instruction Sequencer
Cache-Lock Modes
Cache-Off Mode

On-Chip Data Cache

1 Kbyte Direct-Mapped
Write Through
128 bits per Clock Access on
Cache Hit

Product Grades Available

SE3

40 C to

110 C

High Bandwidth On-Chip Data RAM

1 Kbytes On-Chip RAM for Data
Sustain 128 bits per clock access

Four On-Chip DMA Channels

59 Mbytes s Fly-by Transfers
32 Mbytes s Two-Cycle Transfers
Data Chaining
Data Packing Unpacking
Programmable Priority Method

32-Bit Demultiplexed Burst Bus

128-bit Internal Data Paths to

and

from Registers
Burst Bus for DRAM Interfacing
Address Pipelining Option
Fully Programmable Wait States
Supports 8 16 or 32-bit Bus Widths
Supports Unaligned Accesses
Supervisor Protection Pin

Selectable Big or Little Endian Byte
Ordering

High-Speed Interrupt Controller

Up to 248 External Interrupts
32 Fully Programmable Priorities
Multi-mode 8-bit Interrupt Port
Four Internal DMA Interrupts
Separate Non-maskable Interrupt Pin
Context Switch in 750 ns Typical

Special Environment 80960CF-30 -25 -16

32-Bit High Performance Superscalar Processor

CONTENTS

PAGE

1 0 PURPOSE

2 0 i960 CF PROCESSOR

OVERVIEW

2 1 The C-Series Core

2 2 Pipelined Burst Bus

2 3 Flexible DMA Controller

2 4 Priority Interrupt Controller

2 5 Instruction Set Summary

3 0 PACKAGE INFORMATION

3 1 Package Introduction

3 2 Pin Descriptions

3 3 80960CF Pinout

3 4 Mechanical Data

3 5 Package Thermal Specifications

3 6 Stepping Register Information

3 7 Suggested Sources for 80960CF

Accessories

4 0 ELECTRICAL SPECIFICATIONS

4 1 Absolute Maximum Ratings

4 2 Operating Conditions

4 3 Recommended Connections

4 4 DC Specifications

4 5 AC Specifications

5 0 RESET BACKOFF AND HOLD

ACKNOWLEDGE

6 0 BUS WAVEFORMS

CONTENTS

PAGE

FIGURES

Figure 1

80960CF Die Photo

Figure 2

80960CF Block Diagram

Figure 3

Example Pin Description
Entry

Figure 4a

80960CF PGA Pinout (View
from Top Side)

Figure 4b

80960CF PGA Pinout (View
from Bottom Side)

Figure 5

168-Lead Ceramic PGA
Package Dimensions

Figure 6

80960CF PGA Package
Thermal Characteristics

Figure 7

Measuring 80960CF PGA
Case Temperature

Figure 8

Figure 9

AC Test Load

Figure 10a Input and Output Clocks

Waveform

Figure 10b CLKIN Waveform

Figure 11

Output Delay and Float
Waveform

Figure 12a Input Setup and Hold

Waveform

Figure 12b NMI XINT7 0 Input Setup

and Hold Waveform

Figure 13

Hold Acknowledge
Timings

Figure 14

Bus Back-Off (BOFF)
Timings

CONTENTS

PAGE

Figure 15

Relative Timings
Waveforms

Figure 16

Output Delay or Hold vs Load
Capacitance

Figure 17

Rise and Fall Time Derating at
Highest Operating
Temperature and Minimum
V

Figure 18

vs Frequency and

Temperature

Figure 19

Cold Reset Waveform

Figure 20

Warm Reset Waveform

Figure 21

Entering the ONCE State

Figure 22a Clock Synchronization in the

2x Clock Mode

Figure 22b Clock Synchronization in the

1x Clock Mode

Figure 23

Non-Burst Non-Pipelined
Requests without Wait
States

Figure 24

Non-Burst Non-Pipelined
Read Request with Wait
States

Figure 25

Non-Burst Non-Pipelined
Write Request with Wait
States

Figure 26

Burst Non-Pipelined Read
Request without Wait States
32-Bit Bus

Figure 27

Burst Non-Pipelined Read
Request with Wait States
32-Bit Bus

Figure 28

Burst Non-Pipelined Write
Request without Wait States
32-Bit Bus

Figure 29

Burst Non-Pipelined Write
Request with Wait States
32-Bit Bus

Figure 30

Burst Non-Pipelined Read
Request with Wait States
16-Bit Bus

CONTENTS

PAGE

Figure 31

Burst Non-Pipelined Read
Request with Wait States
8-Bit Bus

Figure 32

Non-Burst Pipelined Read
Request without Wait States
32-Bit Bus

Figure 33

Non-Burst Pipelined Read
Request with Wait States
32-Bit Bus

Figure 34

Burst Pipelined Read
Request without Wait States
32-Bit Bus

Figure 35

Burst Pipelined Read
Requests with Wait States
32-Bit Bus

Figure 36

Burst Pipelined Read
Requests with Wait States
16-Bit Bus

Figure 37

Burst Pipelined Read
Requests with Wait States
8-Bit Bus

Figure 38

Using External READY

Figure 39

Terminating a Burst with
BTERM

Figure 40

BOFF Functional Timing

Figure 41

HOLD Functional Timing

Figure 42

DREQ and DACK Functional
Timing

Figure 43

EOP Functional Timing

Figure 44

Terminal Count Functional
Timing

Figure 45

FAIL Functional Timing

Figure 46

A Summary of Aligned and
Unaligned Transfers for Little
Endian Regions

Figure 47

A Summary of Aligned and
Unaligned Transfers for Little
Endian Regions
(Continued)

Figure 48

Idle Bus Operation

SPECIAL ENVIRONMENT 80960CF-30 -25 -16

1 0

PURPOSE

This document previews electrical characterizations
of Intel's i960 CF embedded microprocessor (avail-
able in 33 25 and 16 MHz) For a detailed descrip-
tion of any i960 CF processor functional topic

oth-

er than parametric performance

refer to the latest

i960 CA Microprocessor Reference Manual (Order
No 270710) and the

i960 CF Reference Manual Ad-

dendum

(Order No 272188)

2 0

i960 CF PROCESSOR OVERVIEW

Intel's i960 CF microprocessor is the performance
follow-on product to the i960 CA processor The
i960 CF product is socket- and object code-compati-
ble with the CA this makes CA-to-CF design up-
grades straightforward The i960 CF processor's in-
struction cache is 4 Kbytes (CA device has 1 Kbyte)
CF data cache is 1 Kbyte (CA device has no data
cache) This extra cache on the CF product adds a
significant performance boost over the CA The
80960CF is object code compatible with the 32-bit
80960 Core Architecture while including Special
Function Register extensions to control on-chip pe-
ripherals and instruction set extensions to shift 64-
bit operands and configure on-chip hardware Multi-
ple 128-bit internal busses on-chip instruction cach-
ing and a sophisticated instruction scheduler allow
the processor to sustain execution of two instruc-

tions every clock and peak at execution of three
instructions per clock

A 32-bit demultiplexed and pipelined burst bus pro-
vides a 132 Mbyte s bandwidth to a system's high-
speed external memory sub-system In addition the
80960CF's on-chip caching of instructions proce-
dure context and critical program data substantially
decouples system performance from the wait states
associated with accesses to the system's slower
cost sensitive main memory sub-system

The 80960CF bus controller also integrates full wait
state and bus width control for highest system per-
formance with minimal system design complexity
Unaligned access and Big Endian byte order support
reduces the cost of porting existing applications to
the 80960CF

The processor also integrates four complete data-
chaining DMA channels and a high-speed interrupt
controller on-chip The DMA channels perform sin-
gle-cycle or two-cycle transfers data packing and
unpacking and data chaining Block transfers in ad-
dition to source or destination synchronized trans-
fers are provided

The interrupt controller provides full programmability
of 248 interrupt sources into 32 priority levels with a
typical interrupt task switch (``latency'') time of
750 ns

271328 � 2

Figure 2 80960CF Block Diagram

Электронный компонент: 80960CF-16