Document Outline
- 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor Data Sheet
- Copyright Page
- Contents
- Figures
- Tables
- 1.0 About This Document
- 2.0 Intels 80960Hx Processor
- 3.0 Package Information
- 4.0 Electrical Specifications
- 5.0 Bus Waveforms
- Figure 29. Cold Reset Waveform
- Figure 30. Warm Reset Waveform
- Figure 31. Entering ONCE Mode
- Figure 32. Non-Burst, Non-Pipelined Requests witho...
- Figure 33. Non-Burst, Non-Pipelined Read Request w...
- Figure 34. Non-Burst, Non-Pipelined Write Request ...
- Figure 35. Burst, Non-Pipelined Read Request witho...
- Figure 36. Burst, Non-Pipelined Read Request with ...
- Figure 37. Burst, Non-Pipelined Write Request with...
- Figure 38. Burst, Non-Pipelined Write Request with...
- Figure 39. Burst, Non-Pipelined Read Request with ...
- Figure 40. Burst, Non-Pipelined Read Request with ...
- Figure 41. Non-Burst, Pipelined Read Request witho...
- Figure 42. Non-Burst, Pipelined Read Request with ...
- Figure 43. Burst, Pipelined Read Request without W...
- Figure 44. Burst, Pipelined Read Request with Wait...
- Figure 45. Burst, Pipelined Read Request with Wait...
- Figure 46. Burst, Pipelined Read Request with Wait...
- Figure 47. Using External READY
- Figure 48. Terminating a Burst with BTERM
- Figure 49. BREQ and BSTALL Operation
- Figure 50. BOFF Functional Timing. BOFF occurs dur...
- Figure 51. HOLD Functional Timing
- Figure 52. LOCK Delays HOLDA Timing
- Figure 53. FAIL Functional Timing
- Figure 54. A Summary of Aligned and Unaligned Tran...
- Figure 55. A Summary of Aligned and Unaligned Tran...
- Figure 56. A Summary of Aligned and Unaligned Tran...
- Figure 57. A Summary of Aligned and Unaligned Tran...
- Figure 58. Idle Bus Operation
- Figure 59. Bus States
- 5.1 80960Hx Boundary Scan Chain
- 5.2 Boundary Scan Description Language Example
80960HA/HD/HT 32-Bit High-Performance
Superscalar Processor
Data Sheet
Advance Information
Product Features
s
32-Bit Parallel Architecture
-- Load/Store Architecture
-- Sixteen 32-Bit Global Registers
-- Sixteen 32-Bit Local Registers
-- 1.28 Gbyte Internal Bandwidth
(80 MHz)
-- On-Chip Register Cache
s
Processor Core Clock
-- 80960HA is 1x Bus Clock
-- 80960HD is 2x Bus Clock
-- 80960HT is 3x Bus Clock
s
Binary Compatible with Other 80960
Processors
s
Issue Up To 150 Million Instructions per
Second
s
High-Performance On-Chip Storage
-- 16 Kbyte Four-Way Set-Associative
Instruction Cache
-- 8 Kbyte Four-Way Set-Associative Data
Cache
-- 2 Kbyte General Purpose RAM
-- Separate 128-Bit Internal Paths For
Instructions/Data
s
3.3 V Supply Voltage
-- 5 V Tolerant Inputs
-- TTL Compatible Outputs
s
Guarded Memory Unit
-- Provides Memory Protection
-- User/Supervisor Read/Write/Execute
s
32-Bit Demultiplexed Burst Bus
-- Per-Byte Parity Generation/Checking
-- Address Pipelining Option
-- Fully Programmable Wait State
Generator
-- Supports 8-, 16- or 32-Bit Bus Widths
-- 160 Mbyte/s External Bandwidth
(40 MHz)
s
High-Speed Interrupt Controller
-- Up to 240 External Interrupts
-- 31 Fully Programmable Priorities
-- Separate, Non-maskable Interrupt Pin
s
Dual On-Chip 32-Bit Timers
-- Auto Reload Capability and One-Shot
-- CLKIN Prescaling, 1, 2, 4 or 8
-- JTAG Support - IEEE 1149.1 Compliant
Order Number: 272495-007
July, 1998
Notice: This document contains information on products in the sampling and initial production
phases of development. The specifications are subject to change without notice. Verify with your
local Intel sales office that you have the latest datasheet before finalizing a design.
80960HA/HD/HT
Advance Information
Datasheet
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The
80960HA/HD/HT may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright Intel Corporation, 1998
*Third-party brands and names are the property of their respective owners.
Advance Information
Datasheet
iii
80960HA/HD/HT
Contents
1.0
About This Document
.............................................................................................. 1
2.0
Intel's 80960Hx Processor
...................................................................................... 1
2.1
The i960 Processor Family ................................................................................. 2
2.2
Key 80960Hx Features.......................................................................................... 2
2.2.1
Execution Architecture ............................................................................. 2
2.2.2
Pipelined, Burst Bus ................................................................................. 2
2.2.3
On-Chip Caches and Data RAM .............................................................. 3
2.2.4
Priority Interrupt Controller ....................................................................... 3
2.2.5
Guarded Memory Unit .............................................................................. 3
2.2.6
Dual Programmable Timers ..................................................................... 4
2.2.7
Processor Self Test .................................................................................. 4
2.3
Instruction Set Summary ....................................................................................... 5
3.0
Package Information
................................................................................................. 6
3.1
Pin Descriptions .................................................................................................... 7
3.2
80960Hx Mechanical Data .................................................................................. 12
3.2.1
80960Hx PGA Pinout ............................................................................. 12
3.2.2
80960Hx PQ4 Pinout.............................................................................. 18
3.3
Package Thermal Specifications ......................................................................... 23
3.4
Heat Sink Adhesives ........................................................................................... 26
3.5
PowerQuad4 Plastic Package............................................................................. 26
3.6
Stepping Register Information............................................................................. 26
3.7
Sources for Accessories...................................................................................... 28
4.0
Electrical Specifications
........................................................................................ 29
4.1
Absolute Maximum Ratings................................................................................. 29
4.2
Operating Conditions........................................................................................... 29
4.3
Recommended Connections ............................................................................... 30
4.4
VCC5 Pin Requirements (V
DIFF
) ......................................................................... 30
4.5
VCCPLL Pin Requirements................................................................................. 31
4.6
DC Specifications ................................................................................................ 32
4.7
AC Specifications ................................................................................................ 34
4.7.1
AC Test Conditions ................................................................................ 37
4.8
AC Timing Waveforms ........................................................................................ 38
5.0
Bus Waveforms
......................................................................................................... 46
5.1
80960Hx Boundary Scan Chain .......................................................................... 76
5.2
Boundary Scan Description Language Example................................................. 80
80960HA/HD/HT
iv
Advance Information
Datasheet
Figures
1
80960Hx Block Diagram .......................................................................................1
2
80960Hx 168-Pin PGA Pinout -- View from Top (Pins Facing Down) ...............12
3
80960Hx 168-Pin PGA Pinout -- View from Bottom (Pins Facing Up) ...............13
4
80960Hx 208-Pin PQ4 Pinout .............................................................................18
5
Measuring 80960Hx PGA Case Temperature ....................................................23
6
80960Hx Device Identification Register ..............................................................26
7
VCC5 Current-Limiting Resistor ..........................................................................30
8
AC Test Load ......................................................................................................37
9
CLKIN Waveform ................................................................................................38
10
Output Delay Waveform ......................................................................................38
11
Output Delay Waveform ......................................................................................38
12
Output Float Waveform .......................................................................................39
13
Input Setup and Hold Waveform .........................................................................39
14
NMI, XINT7:0 Input Setup and Hold Waveform ..................................................39
15
Hold Acknowledge Timings .................................................................................40
16
Bus Backoff (BOFF) Timings ..............................................................................40
17
TCK Waveform....................................................................................................41
18
Input Setup and Hold Waveforms for T
BSIS1
and T
BSIH1
....................................41
19
Output Delay and Output Float for T
BSOV1
and T
BSOF1
......................................42
20
Output Delay and Output Float Waveform for T
BSOV2
and T
BSOF2
....................42
21
Input Setup and Hold Waveform for T
BSIS2
and T
BSIH2
......................................42
22
Rise and Fall Time Derating at 85C and Minimum V
CC
....................................43
23
I
CC
Active (Power Supply) vs. Frequency ...........................................................43
24
I
CC
Active (Thermal) vs. Frequency ....................................................................44
25
Output Delay or Hold vs. Load Capacitance .......................................................44
26
Output Delay vs. Temperature ............................................................................45
27
Output Hold Times vs. Temperature ...................................................................45
28
Output Delay vs. V
CC
..........................................................................................45
29
Cold Reset Waveform .........................................................................................46
30
Warm Reset Waveform .......................................................................................47
31
Entering ONCE Mode .........................................................................................48
32
Non-Burst, Non-Pipelined Requests without Wait States ...................................49
33
Non-Burst, Non-Pipelined Read Request with Wait States.................................50
34
Non-Burst, Non-Pipelined Write Request with Wait States .................................51
35
Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus .................52
36
Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus ......................53
37
Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus .................54
38
Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus ......................55
39
Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus ......................56
40
Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus ........................57
41
Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus .................58
42
Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus ......................59
43
Burst, Pipelined Read Request without Wait States, 32-Bit Bus.........................60
44
Burst, Pipelined Read Request with Wait States, 32-Bit Bus..............................61
45
Burst, Pipelined Read Request with Wait States, 8-Bit Bus................................62
46
Burst, Pipelined Read Request with Wait States, 16-Bit Bus..............................63
47
Using External READY........................................................................................64
48
Terminating a Burst with BTERM ........................................................................65
49
BREQ and BSTALL Operation ............................................................................66
Advance Information
Datasheet
v
80960HA/HD/HT
50
BOFF Functional Timing. BOFF occurs during a burst or
non-burst data cycle. .......................................................................................... 67
51
HOLD Functional Timing .................................................................................... 68
52
LOCK Delays HOLDA Timing ............................................................................ 69
53
FAIL Functional Timing....................................................................................... 69
54
A Summary of Aligned and Unaligned Transfers for 32-Bit Regions ................. 70
56
A Summary of Aligned and Unaligned Transfers for 16-Bit Bus ........................ 72
57
A Summary of Aligned and Unaligned Transfers for 8-Bit Bus .......................... 73
58
Idle Bus Operation.............................................................................................. 74
59
Bus States .......................................................................................................... 75
Tables
1
80960Hx Product Description................................................................................ 1
2
Fail Codes For BIST (bit 7 = 1) ............................................................................. 4
3
Remaining Fail Codes (bit 7 = 0)........................................................................... 4
4
80960Hx Instruction Set ........................................................................................ 5
5
80960HA/HD/HT Package Types and Speeds ..................................................... 6
6
Pin Description Nomenclature............................................................................... 7
7
80960Hx Processor Family Pin Descriptions ........................................................ 8
8
80960Hx 168-Pin PGA Pinout -- Signal Name Order ........................................ 14
9
80960Hx 168-Pin PGA Pinout -- Pin Number Order .......................................... 16
10
80960Hx PQ4 Pinout -- Signal Name Order ...................................................... 19
11
80960Hx PQ4 Pinout -- Pin Number Order........................................................ 21
12
Maximum T
A
at Various Airflows in C (PGA Package Only).............................. 24
13
80960Hx 168-Pin PGA Package Thermal Characteristics .................................. 24
14
Maximum T
A
at Various Airflows in C (PQ4 Package Only) .............................. 25
15
80960Hx 208-Pin PQ4 Package Thermal Characteristics .................................. 25
16
Fields of 80960Hx Device ID............................................................................... 27
17
80960Hx Device ID Model Types........................................................................ 27
18
Device ID Version Numbers for Different Steppings ........................................... 27
19
Operating Conditions........................................................................................... 29
20
V
DIFF
Specification for Dual Power Supply Requirements (3.3 V, 5 V)............... 30
21
80960Hx DC Characteristics ............................................................................... 32
22
80960Hx AC Characteristics ............................................................................... 34
23
AC Characteristics Notes .................................................................................... 36
24
80960Hx Boundary Scan Test Signal Timings.................................................... 36
25
80960Hx Boundary Scan Chain .......................................................................... 76
26
Data Sheet Version -006 to -007 Revision History.............................................. 96
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