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November 1992
COPYRIGHT
INTEL CORPORATION 1995
Order Number 270640-004
80C187
80-BIT MATH COPROCESSOR
Y
High Performance 80-Bit Internal
Architecture
Y
Implements ANSI IEEE Standard 754-
1985 for Binary Floating-Point
Arithmetic
Y
Upward Object-Code Compatible from
8087
Y
Fully Compatible with 387DX and 387SX
Math Coprocessors Implements all 387
Architectural Enhancements over 8087
Y
Directly Interfaces with 80C186 CPU
Y
80C186 80C187 Provide a Software
Binary Compatible Upgrade from
80186 82188 8087 Systems
Y
Expands 80C186's Data Types to
Include 32- 64- 80-Bit Floating-Point
32- 64-Bit Integers and 18-Digit BCD
Operands
Y
Directly Extends 80C186's Instruction
Set to Trigonometric Logarithmic
Exponential and Arithmetic
Instructions for All Data Types
Y
Full-Range Transcendental Operations
for SINE COSINE TANGENT
ARCTANGENT and LOGARITHM
Y
Built-In Exception Handling
Y
Eight 80-Bit Numeric Registers Usable
as Individually Addressable General
Registers or as a Register Stack
Y
Available in 40-Pin CERDIP and 44-Pin
PLCC Package
(See Packaging Outlines and Dimensions Order
231369)
The Intel 80C187 is a high-performance math coprocessor that extends the architecture of the 80C186 with
floating-point extended integer and BCD data types A computing system that includes the 80C187 fully
conforms to the IEEE Floating-Point Standard The 80C187 adds over seventy mnemonics to the instruction
set of the 80C186 including support for arithmetic logarithmic exponential and trigonometric mathematical
operations The 80C187 is implemented with 1 5 micron high-speed CHMOS III technology and packaged in
both a 40-pin CERDIP and a 44-pin PLCC package The 80C187 is upward object-code compatible from the
8087 math coprocessor and will execute code written for the 80387DX and 80387SX math coprocessors
80C187
270640
1
Figure 1 80C187 Block Diagram
2
80C187
80C187 Data Registers
79
78
64
63
0
R0
SIGN
EXPONENT
SIGNIFICAND
R1
R2
R3
R4
R5
R6
R7
15
0
15
0
CONTROL REGISTER
INSTRUCTION POINTER
STATUS REGISTER
DATA POINTER
TAG WORD
Figure 2 Register Set
FUNCTIONAL DESCRIPTION
The 80C187 Math Coprocessor provides arithmetic
instructions for a variety of numeric data types It
also executes numerous built-in transcendental
functions (e g tangent sine cosine and log func-
tions) The 80C187 effectively extends the register
and instruction set of the 80C186 CPU for existing
data types and adds several new data types as well
Figure 2 shows the additional registers visible to pro-
grams in a system that includes the 80C187 Essen-
tially the 80C187 can be treated as an additional
resource or an extension to the CPU The 80C186
CPU together with an 80C187 can be used as a sin-
gle unified system
A 80C186 system that includes the 80C187 is com-
pletely upward compatible with software for the
8086 8087
The 80C187 interfaces only with the 80C186 CPU
The interface hardware for the 80C187 is not imple-
mented on the 80C188
PROGRAMMING INTERFACE
The 80C187 adds to the CPU additional data types
registers instructions and interrupts specifically de-
signed to facilitate high-speed numerics processing
All new instructions and data types are directly sup-
ported by the assembler and compilers for high-level
languages
The 80C187 also supports the full
80387DX instruction set
All communication between the CPU and the
80C187 is transparent to applications software The
CPU automatically controls the 80C187 whenever a
numerics instruction is executed All physical memo-
ry and virtual memory of the CPU are available for
storage of the instructions and operands of pro-
grams that use the 80C187 All memory addressing
modes are available for addressing numerics oper-
ands
The end of this data sheet lists by class the instruc-
tions that the 80C187 adds to the instruction set
NOTE
The 80C187 Math Coprocessor is also referred to
as a Numeric Processor Extension (NPX) in this
document
Data Types
Table 1 lists the seven data types that the 80C187
supports and presents the format for each type Op-
erands are stored in memory with the least signifi-
cant digit at the lowest memory address Programs
retrieve these values by generating the lowest ad-
dress For maximum system performance all oper-
ands should start at even physical-memory address-
es operands may begin at odd addresses but will
require extra memory cycles to access the entire op-
erand
Internally the 80C187 holds all numbers in the ex-
tended-precision real format Instructions that load
operands from memory automatically convert oper-
ands represented in memory as 16- 32- or 64-bit
integers 32- or 64-bit floating-point numbers or 18-
digit packed BCD numbers into extended-precision
real format Instructions that store operands in mem-
ory perform the inverse type conversion
3
80C187
Numeric Operands
A typical NPX instruction accepts one or two oper-
ands and produces one (or sometimes two) results
In two-operand instructions one operand is the con-
tents of an NPX register while the other may be a
memory location The operands of some instructions
are predefined for example FSQRT always takes
the square root of the number in the top stack ele-
ment (refer to the section on Data Registers)
Register Set
Figure 2 shows the 80C187 register set When an
80C187 is present in a system programmers may
use these registers in addition to the registers nor-
mally available on the CPU
DATA REGISTERS
80C187 computations use the extended-precision
real data type
Table 1 Data Type Representation in Memory
270640 2
NOTES
1 S
e
Sign bit (0
e
Positive 1
e
Negative)
2 d
n
e
Decimal digit (two per byte)
3 X
e
Bits have no significance 80C187 ignores when loading zeros when storing
4
U
e
Position of implicit binary point
5 I
e
Integer bit of significand stored in temporary real implicit in single and double precision
6 Exponent Bias (normalized values)
Single 127 (7FH)
Double 1023 (3FFH)
Extended Real 16383 (3FFFH)
7 Packed BCD (
b
1)
S
(D
17
D
0
)
8 Real (
b
1)
S
(2
E-BIAS
) (F
0
F
1
)
4
80C187
The 80C187 register set can be accessed either as
a stack with instructions operating on the top one or
two stack elements or as individually addressable
registers The TOP field in the status word identifies
the current top-of-stack register A ``push'' operation
decrements TOP by one and loads a value into the
new top register A ``pop'' operation stores the value
from the current top register and then increments
TOP by one The 80C187 register stack grows
``down'' toward lower-addressed registers
Instructions may address the data registers either
implicitly or explicitly Many instructions operate on
the register at the TOP of the stack These instruc-
tions implicitly address the register at which TOP
points Other instructions allow the programmer to
explicitly specify which register to use This explicit
addressing is also relative to TOP
TAG WORD
The tag word marks the content of each numeric
data register as Figure 3 shows Each two-bit tag
represents one of the eight data registers The prin-
cipal function of the tag word is to optimize the
NPX's performance and stack handling by making it
possible to distinguish between empty and nonemp-
ty register locations It also enables exception han-
dlers to identify special values (e g NaNs or denor-
mals) in the contents of a stack location without the
need to perform complex decoding of the actual
data
STATUS WORD
The 16-bit status word (in the status register) shown
in Figure 4 reflects the overall state of the 80C187 It
may be read and inspected by programs
Bit 15 the B-bit (busy bit) is included for 8087 com-
patibility only It always has the same value as the
ES bit (bit 7 of the status word) it does not indicate
the status of the BUSY output of 80C187
Bits 13 11 (TOP) point to the 80C187 register that
is the current top-of-stack
The four numeric condition code bits (C
3
C
0
) are
similar to the flags in a CPU instructions that per-
form arithmetic operations update these bits to re-
flect the outcome The effects of these instructions
on the condition code are summarized in Tables 2
through 5
Bit 7 is the error summary (ES) status bit This bit is
set if any unmasked exception bit is set it is clear
otherwise If this bit is set the ERROR signal is as-
serted
Bit 6 is the stack flag (SF) This bit is used to distin-
guish invalid operations due to stack overflow or un-
derflow from other kinds of invalid operations When
SF is set bit 9 (C
1
) distinguishes between stack
overflow (C
1
e
1) and underflow (C
1
e
0)
Figure 4 shows the six exception flags in bits 5 0 of
the status word Bits 5 0 are set to indicate that the
80C187 has detected an exception while executing
an instruction A later section entitled ``Exception
Handling'' explains how they are set and used
Note that when a new value is loaded into the status
word by the FLDENV or FRSTOR instruction the
value of ES (bit 7) and its reflection in the B-bit (bit
15) are not derived from the values loaded from
memory but rather are dependent upon the values of
the exception flags (bits 5 0) in the status word and
their corresponding masks in the control word If ES
is set in such a case the ERROR output of the
80C187 is activated immediately
15
0
TAG (7)
TAG (6)
TAG (5)
TAG (4)
TAG (3)
TAG (2)
TAG (1)
TAG (0)
NOTE
The index i of tag(i) is not top-relative A program typically uses the ``top'' field of Status Word to determine
which tag(i) field refers to logical top of stack
TAG VALUES
00
e
Valid
01
e
Zero
10
e
QNaN SNaN Infinity Denormal and Unsupported Formats
11
e
Empty
Figure 3 Tag Word
5
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