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Электронный компонент: 80C51GB-1

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Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
November 1994
COPYRIGHT
INTEL CORPORATION 1995
Order Number 272337-002
8XC51GB
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Commercial Express
87C51GB
8 Kbytes OTP 8 Kbytes Internal Program Memory
83C51GB
8 Kbytes Factory Programmable ROM
80C51GB
CPU with RAM and I O
8XC51GB
3 5 MHz to 12 MHz
g
20% V
CC
8XC51GB-1
3 5 MHz to 16 MHz
g
20% V
CC
Y
8 Kbytes On-Chip ROM OTP ROM
Y
256 Bytes of On-Chip Data RAM
Y
Two Programmable Counter Arrays
with
2 x 5 High Speed Input Output
Channels Compare Capture
Pulse Width Modulators
Watchdog Timer Capabilities
Y
Three 16-Bit Timer Counters with
Four Programmable Modes
Capture Baud Rate Generation
(Timer 2)
Y
Dedicated Watchdog Timer
Y
8-Bit 8-Channel A D with
Eight 8-Bit Result Registers
Four Programmable Modes
Y
Programmable Serial Channel with
Framing Error Detection
Automatic Address Recognition
Y
Serial Expansion Port
Y
Programmable Clock Out
Y
Extended Temperature Range
(
b
40 C to
a
85 C)
Y
48 Programmable I O Lines with
40 Schmitt Trigger Inputs
Y
15 Interrupt Sources with
7 External 8 Internal Sources
4 Programmable Priority Levels
Y
Pre-Determined Port States on Reset
Y
High Performance CHMOS Process
Y
TTL and CHMOS Compatible Logic
Levels
Y
Power Saving Modes
Y
64K External Data Memory Space
Y
64K External Program Memory Space
Y
Three Level Program Lock System
Y
ONCE (ON-Circuit Emulation) Mode
Y
Quick Pulse Programming Algorithm
Y
MCS
51 Microcontroller Fully
Compatible Instruction Set
Y
Boolean Processor
Y
Oscillator Fail Detect
Y
Available in 68-Pin PLCC
MEMORY ORGANIZATION
PROGRAM MEMORY Up to 8 Kbytes of the program memory can reside in the on-chip ROM Also the device
can address up to 64K of program memory external to the chip
DATA MEMORY This microcontroller has a 256 x 8 on-chip RAM In addition it can address up to 64 Kbytes of
external data memory
The Intel 8XC51GB is a single-chip control oriented microcontroller which is fabricated on Intel's CHMOS III-E
technology The 8XC51GB is an enhanced version of the 8XC51FA and uses the same powerful instruction
set and architecture as existing MCS 51 microcontroller products Added features make it an even more
powerful microcontroller for applications that require On-Chip A D Pulse Width Modulation High Speed I O
up down counting capabilities and memory protection features It also has a more versatile serial channel that
facilitates multi-processor communications
8XC51GB
272337 1
Figure 1 8XC51GB Block Diagram
PROCESS INFORMATION
This device is manufactured on P629 0 a CHMOS
III-E process Additional process and reliability infor-
mation is available in Intel's Components Quality
and Reliability Handbook Order No 210997
PACKAGES
Part
Prefix
Package Type
8XC51GB
N
68-Pin PLCC
2
8XC51GB
PARALLEL I O PORTS
The 8XC51GB contains six 8-bit parallel I O ports
All six ports are bidirectional and consist of a latch
an output driver and an input buffer Many of the
port pins have multiplexed I O and control functions
Port Pins as Outputs
Port 0 has open drain outputs when it is not serving
as the external data bus The internal pullup is active
only when the pin is outputting a logic 1 during exter-
nal memory access An external pullup resistor is
required on Port 0 when it is serving as an output
port
Ports 1 2 3 4 and 5 have quasi-bidirectional out-
puts A strong pullup provides a fast rise time when
the pin is set to a logic 1 This pullup turns on for two
oscillator periods to drive the pin high and then turns
off The pin is held high by a weak pullup
Writing the P0 P1 P2 P3 P4 or P5 Special Function
Register sets the corresponding port pins All six
port registers are bit addressable
Port Pins as Inputs
The pins of all six ports are configured as inputs by
writing a logic 1 to them Since Port 0 is an open
drain port it provides a very high input impedance
Since pins of Port 1 2 3 4 and 5 have weak pullups
(which are always on) they source a small current
when driven low externally All ports except Port 0
have Schmitt trigger inputs
Port States During Reset
Ports 0 and 3 reset asynchronously to a one and
Ports 1 2 4 and 5 reset to a zero asynchronously
PIN DESCRIPTIONS
The 8XC51GB will be packaged in the 68-lead PLCC
package Its pin assignment is shown in Figure 2
V
CC
Supply Voltage
V
SS
Circuit Ground
Diagram is for Pin Reference Only Package Size is Not to Scale
272337 2
OTP only
Figure 2 Pin Connections
3
8XC51GB
ALTERNATE PORT FUNCTIONS
Ports 0 1 2 3 4 and 5 have alternate functions as well as their I O function as described below
Port Pin
Alternate Function
P0 0 ADO P0 7 AD7
Multiplexed Address Data for External Memory
P1 0 T2
Timer 2 External Clock Input Clock-Out
P1 1 T2EX
Timer 2 Reload Capture Direction Control
P1 2 ECI
PCA External Clock Input
P1 3 CEXO P1 7 CEX4
PCA Capture Input Compare PWM Output
P2 0 A8 P2 7 A15
High Byte of Address for External Memory
P3 0 RXD
Serial Port Input
P3 1 TXD
Serial Port Output
P3 2 INT0
External Interrupt 0
P3 3 INT1
External Interrupt 1
P3 4 T0
Timer 0 External Clock Input
P3 5 T1
Timer 1 External Clock Input
P3 6 WR
Write Strobe for External Memory
P3 7 RD
Read Strobe for External Memory
P4 0 SEPCLK
Clock Source for Serial Expansion Port
P4 1 SEPDAT
Data I O for the Serial Expansion Port
P4 2 ECI1
PCA1 External Clock Input
P4 3 C1EX0 P4 7 C1EX4
PCA1 Capture Input Compare PWM Output
P5 2 INT2 P5 6 INT6
External Interrupt INT2 INT6
RST
Reset input A low on this pin for two machine
cycles while the oscillator is running resets the de-
vice The port pins will be driven to their reset condi-
tion when a voltage below V
IL
max voltage is ap-
plied whether the oscillator is running or not An
internal pullup resistor permits a power-on reset with
only a capacitor connected to V
SS
ALE PROG
Address Latch Enable output pulse for
latching the low byte of the address during accesses
to external memory This pin (ALE PROG) is also
the program pulse input during programming of the
87C51GB
In normal operation ALE is emitted at a constant
rate of
the oscillator frequency and may be used
for external timing or clocking purposes Note how-
ever that one ALE pulse is skipped during each ac-
cess to external Data Memory
If desired ALE operation can be disabled by setting
bit 0 of SFR location 8EH With this bit set the pin is
weakly pulled high However the ALE disable fea-
ture will be suspended during a MOVX or MOVC in-
struction idle mode power down mode and ICE
mode The ALE disable feature will be terminated by
reset When the ALE disable feature is suspended or
terminated the ALE pin will no longer be pulled up
weakly Setting the ALE-disable bit has no affect if
the microcontroller is in external execution mode
Throughout the remainder of this data sheet ALE
will refer to the signal coming out of the ALE PROG
pin and the pin will be referred to as the ALE PROG
pin
PSEN
Program Store Enable is the read strobe to
external Program Memory
When the 8XC51GB is executing code from external
Program Memory PSEN is activated twice each ma-
chine cycle except that two PSEN activations are
skipped during each access to external Data Memo-
ry
EA V
PP
External Access enable
EA must be
strapped to V
SS
in order to enable the device to
fetch code from external Program Memory locations
0000H to 1FFFH Note however that if either of the
Program Lock bits are programmed EA will be inter-
nally latched on reset
EA should be strapped to V
CC
for internal program
executions
4
8XC51GB
This pin also receives the 12 75V programming sup-
ply voltage (V
PP
) during programming (OTP only)
XTAL1
Input to the inverting oscillator amplifier
XTAL2
Output from the inverting oscillator amplifi-
er
A D CONVERTER
The 8XC51GB A D converter has a resolution of 8
bits and an accuracy of
g
1 LSB (
g
2 LSB for chan-
nels 0 and 1) The conversion time for a single chan-
nel is 20 ms at a clock frequency of 16 MHz with the
sample and hold function included Independent
supply voltages are provided for the A D Also the
A D operates both in Normal Mode or in Idle Mode
The A D has 8 analog input pins ACH0 (A D CHan-
nel 0)
ACH7 1 reference input pin COMPREF
(COMParison REFerence) 1 control input pin TRI-
GIN (TRIGger IN) and 2 power pins AVREF (Volt-
age
REFerence)
and
analog
ground
(ANalog
GrouND) In addition the A D has 8 conversion re-
sult registers ADRES0 (A D result for channel 0)
ADRES7 1 comparison result register ACMP (Ana-
log Comparison) and 1 control register ACON (A D
Control)
The control bit ACE (A D Conversion Enable) in
ACON controls whether the A D is in operation or
not ACE e 0 idles the A D ACE e 1 enables A D
conversion The control bit AIM (A D Input mode) in
ACON controls the mode of channel selection AIM
e
0 is the Scan Mode and AIM e 1 is the Select
Mode The result registers ADRES4
ADRES7 al-
ways contain the result of a conversion from the cor-
responding channels ACH4
CH7 However the
result registers ADRES0
ADRES3 depend on the
mode selected In the scan mode ADRES0
AD-
RES3 contain the values from ACH0
ACH3 In
the Select Mode one of the four channels ACH0
ACH3 is converted four times and the four values
are stored sequentially in locations ADRES0
AD-
RES3 Its channel is selected by bits ACS1 and
ACS0 (A D Channel Select 1 and 0) in ACON
PROGRAMMABLE COUNTER ARRAYS
The Programmable Counter Arrays (PCA PCA1) are
each made up of a Counter Module and five Regis-
ter Comparator Modules as shown below
The
16-bit output of the counter module is available to all
five Register Comparator Modules providing one
common timing reference Each Register Compara-
tor Module is associated with a pin of Port 1 or Port 4
and is capable of performing input capture output
compare and pulse width modulation functions The
PCAs are exactly the same in function except for the
addition of clock input sources on PCA1
The PCA Counter and five Register Comparator
Modules each have a status bit in the CCON
C1CON Special Function Registers
These six
status bits are set according to the selected modes
of operation described below The CCON C1CON
Register provides a convenient means to determine
which of the six PCA PCA1 interrupts has occurred
The EC Bit in the IE (Interrupt Enable) Special Func-
tion Register is a global interrupt enable for the PCA
272337 3
Figure 3 Programmable Counter Arrays
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output respec-
tively of an inverting amplifier which can be config-
ured for use as an on-chip oscillator as shown in
Figure 4 Either a quartz crystal or ceramic resonator
may be used More detailed information concerning
the use of the on-chip oscillator is available in Appli-
cation Note AP-155 ``Oscillators for Microcontrol-
lers '' Order No 230659
To drive the device from an external clock source
XTAL should be driven while XTAL2 floats as
shown in Figure 5 There are no requirements on the
duty cycle of the external clock signal since the in-
put to the internal clocking circuitry is through a di-
vide-by-two flip-flop but minimum and maximum
high and low times specified on the data sheet must
be observed
5
8XC51GB
272337 4
C1 C2
e
30 pF
g
10 pF for Crystals
For Ceramic Resonators contact resonator
manufacturer
Figure 4 Oscillator Connections
272337 5
Figure 5 External Clock Drive Configuration
IDLE MODE
The user's software can invoke the Idle Mode When
the microcontroller is in this mode power consump-
tion is reduced The Special Function Registers and
the onboard RAM retain their values during idle pe-
ripherals continue to operate but the processor
stops executing instructions Idle Mode will be exited
if the chip is reset or if an enabled interrupt occurs
The PCA timer counter can optionally be left run-
ning or paused during Idle Mode The Watchdog
Timer continues to count in Idle Mode and must be
serviced to prevent a device RESET while in Idle
POWER DOWN MODE
To save even more power a Power Down mode can
be invoked by software In this mode the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed The on-chip
RAM and Special Function Registers retain their val-
ues until the Power Down mode is terminated
On the 8XC51GB either a hardware reset or an ex-
ternal interrupt can cause an exit from Power Down
Reset redefines all the SFRs but does not change
the on-chip RAM An external interrupt does not re-
define the SFR's or change the on-chip RAM An
external interrupt will modify the interrupt associated
SFR's in the same way an interrupt will in all other
modes The interrupt must be enabled and config-
ured as level sensitive To properly terminate Power
Down the reset or external interrupt should not be
executed before V
CC
is restored to its normal oper-
ating level The reset or external interrupt must be
held active long enough for the oscillator to restart
and stabilize The Oscillator Fail Detect must be dis-
abled prior to entering Power Down
DESIGN CONSIDERATIONS
When the idle mode is terminated by a hardware
reset the device normally resumes program exe-
cution from where it left off up to two machine
cycles before the internal reset algorithm takes
control On-chip hardware inhibits access to inter-
nal RAM in this event but access to the port pins
is not inhibited To eliminate the possibility of an
unexpected write when Idle is terminated by re-
set the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory
As RESET rises the 8XC51GB will remain in re-
set for up to 5 machine cycles (60 oscillator peri-
ods) after RESET reaches V
IH1
Table 1 Status of the External Pins during Idle and Power Down
Mode
Program
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Memory
Idle
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power Down
Internal
0
0
Data
Data
Data
Data
Power Down
External
0
0
Float
Data
Data
Data
NOTE
For more detailed information on the reduced power modes refer to current Embedded Microcontrollers
and Processors Handbook Volume I (Order No 270645) and Application Note AP-252 (Embedded
Applications Handbook Order No 270648) ``Designing with the 80C51BH ''
6
8XC51GB
ONCE MODE
The ONCE (``On-Circuit Emulation'') Mode facilitates
testing
and
debugging
of
systems
using
the
8XC51GB without removing it from the circuit The
ONCE Mode is invoked by
1) Pulling ALE low while the device is in reset and
PSEN is high
2) Holding ALE low as RESET is deactivated
While the device is in ONCE Mode the Port 0 pins
float and the other port pins and ALE and PSEN are
weakly pulled high The oscillator circuit remains ac-
tive While the 8XC51GB is in this mode an emula-
tor or test CPU can be used to drive the circuit Nor-
mal operation is restored when a normal reset is ap-
plied
Watchdog Timer (WDT)
The 8XC51GB contains a dedicated Watchdog Tim-
er (WDT) to allow recovery from a software or hard-
ware upset The WDT consists of a 14-bit counter
which is cleared on Reset and subsequently incre-
mented every machine cycle While the oscillator is
running the WDT will be incrementing and cannot
be disabled The counter may be reset by writing
1EH and E1H in sequence to the WDTRST Special
Function Register If the counter is not reset before
it reaches 3FFFH (16383D) the chip will be forced
into a reset sequence by the WDT This works out to
12 28 ms
16 MHz WDTRST is a write only regis-
ter The WDT does not force the external reset pin
low
While in Idle mode the WDT continues to count If
the user does not wish to exit Idle with a reset then
the processor must be periodically ``woken up'' to
service the WDT In Power Down mode the WDT
stops counting and holds its current value
Serial Expansion Port (SEP)
The Serial Expansion Port is a half-duplex synchro-
nous serial interface with the following features
Four Clock Frequencies
XTAL 12 24 48 96
Four Interface Modes
High Low Falling Rising
Edges
Interrupt Driven
Oscillator Fail Detect (OFD)
The Oscillator Fail Detect circuitry triggers a reset if
the oscillator frequency is lower than the OFD trig-
ger frequency It can be disabled by software by writ-
ing E1H followed by 1EH to the OFDCON register
Before going into Power Down Mode the OFD must
be disabled or it will force the GB out of Power
Down The OFD has the following features
OFD Trigger Frequency Below 20 KHz the
8XC51GB will be held in reset Above 400 KHz
the 8XC51GB will not be held is reset
Functions in Normal and Idle Modes
Reactivated by Reset (or External Interrupt Ze-
ro One Pins) after Software Disable
8XC51GB EXPRESS
The Intel EXPRESS products are designed to meet
the needs of those applications whose operating re-
quirements exceed commercial standards
With the commercial standard temperature range
operational characteristics are guaranteed over the
temperature range of 0 C to a70 C With the ex-
tended temperature range option operational char-
acteristics are guaranteed over the range of b40 C
to a85 C The 87C51GB EXPRESS is packaged in
the 68-lead PLCC package In order to designate a
part as an EXPRESS part a ``T'' is added as a prefix
to the part number TN87C51GB denotes an EX-
PRESS part in a PLCC package
All AC and DC parameters in this data sheet apply to
the EXPRESS devices
7
8XC51GB
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature under Bias
0 C to a70 C
Storage Temperature
b
65 C to a150 C
Voltage on EA V
PP
Pin to V
SS
0V to a13 0V
I
OL
per I O Pin
15 mA
Voltage on Any Other
Pin to V
SS
b
0 5V to a6 5V
Power Dissipation
1 5W
(Based on Package heat transfer limitations not de-
vice power consumption)
OTP only
NOTICE This data sheet contains preliminary infor-
mation on new products in production The specifica-
tions are subject to change without notice Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design
WARNING Stressing the device beyond the ``Absolute
Maximum Ratings'' may cause permanent damage
These are stress ratings only Operation beyond the
``Operating Conditions'' is not recommended and ex-
tended exposure beyond the ``Operating Conditions''
may affect device reliability
OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
T
A
Ambient Temperature Under Bias
Commercial
0
a
70
C
Express
b
40
a
85
C
V
CC
Supply Voltage
4 0
6 0
V
f
OSC
Oscillator Frequency
8XC51GB
3 5
12
MHz
8XC51GB-1
3 5
16
MHz
DC CHARACTERISTICS
(Over Operating Conditions)
Symbol
Parameter
Min
Typ
(1)
Max
Unit
Test Conditions
V
IL
Input Low Voltage
b
0 5
0 2 V
CC
b
0 1
V
(except Port 2 and EA)
V
IL1
Input Low Voltage
b
0 5
0 2 V
CC
b
0 3
V
(Port 2)
V
IL2
Input Low Voltage
0
0 2 V
CC
b
0 3
V
(EA)
V
IH
Input High Voltage
0 2 V
CC
a
0 9
V
CC
a
0 5
V
(except XTAL1 and RST)
V
IH1
Input High Voltage
0 7 V
CC
V
CC
a
0 5
V
(XTAL1 RST)
V
OL
Output Low Voltage
0 3
V
I
OL
e
100 mA
(2 3)
(Ports 1 2 3 4 and 5)
0 45
V
I
OL
e
1 6 mA
(2 3)
1 0
V
I
OL
e
3 5 mA
(2 3)
V
OL1
Output Low Voltage
0 3
V
I
OL
e
200 mA
(2 3)
(Port 0 PSEN ALE)
0 45
V
I
OL
e
3 2 mA
(2 3)
1 0
V
I
OL
e
7 0 mA
(2 3)
8
8XC51GB
DC CHARACTERISTICS
(Over Operating Conditions) (Continued)
Symbol
Parameter
Min
Typ
(1)
Max
Unit
Test Conditions
V
OH
Output High Voltage
V
CC
b
0 3
V
I
OH
e b
10 mA
(4)
(Ports 1 2 3 4 and 5
V
CC
b
0 7
V
I
OH
e b
30 mA
(4)
ALE PSEN)
V
CC
b
1 5
V
I
OH
e b
60 mA
(4)
V
OH1
Output High Voltage
V
CC
b
0 3
V
I
OH
e b
200 mA
(Port 0 in External
V
CC
b
0 7
V
I
OH
e b
3 2 mA
Bus Mode)
V
CC
b
1 5
V
I
OH
e b
7 0 mA
I
IL
Logical 0 Input Current
b
50
m
A
V
IN
e
0 45V
(Ports 1 2 3 4 5)
I
TL
Logical 1-to-0 Transition
b
650
m
A
V
IN
e
2 0V
Current (Ports 1 2 3 4 5)
I
LI
Input Leakage Current
g
10
m
A
0 45
k
V
IN
k
V
CC
(Port 0)
RRST
RST Pullup Resistor
50
300
kX
C
IO
Pin Capacitance
10
pF
Freq e 1 MHz
T
A
e
25 C
I
PD
Power Down Current
50
m
A
(5)
I
DL
Idle Mode Current
18
mA
(5)
I
CC
Operating Current
16 MHz
50
mA
(5)
I
REF
A D Converter Reference
5
mA
Current
NOTES
1 Typical values are obtained using V
CC
e
5 0V T
A
e
25 C and are not guaranteed
2 Under steady state (non-transient) conditions I
OL
must be externally limited as follows
Maximum I
OL
per Port Pin
10 mA
Maximum I
OL
per 8-Bit Port
Port 0
26 mA
Ports 1 5
15 mA
Maximum Total I
OL
for All Outputs Pins 101 mA
If I
OL
exceeds the test conditions V
OL
may exceed the related specification Pins are not guaranteed to sink current
greater than the listed test conditions
3 Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0 4V on the low level outputs of ALE and
Ports 1 2 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to 0 In applications where capacitive loading exceeds 100 pF the noise pulses on these signals may exceed
0 8V It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic
4 Capacitive loading on Ports 0 and 2 cause the V
OH
on ALE and PSEN to drop below the 0 9 V
CC
specification when the
address lines are stabilizing
5 See Figures 6 10 for test conditions Minimum V
CC
for Power Down is 2V
9
8XC51GB
272337 6
I
CC
Max at other frequencies is given by
Active Mode
I
CC
Max
e
(Osc Freq
c
3)
a
4
Idle Mode
I
CC
Max
e
(Osc Freq
c
0 5)
a
4
Where Osc Freq is in MHz I
CC
is in mA T
CLCH
e
T
CHCL
e
5 ns
Figure 6 I
CC
vs Frequency
272337 7
All other pins disconnected
TCLCH
e
TCHCL
e
5 ns
Figure 7 I
CC
Test Condition
Active Mode
272337 8
All other pins disconnected
TCLCH
e
TCHCL
e
5 ns
Figure 8 I
CC
Test Condition Idle Mode
272337 9
All other pins disconnected
Figure 9 I
CC
Test Condition Power Down Mode
V
CC
e
2 0V to 5 5V
272337 10
Figure 10 Clock Signal Waveform for I
CC
Tests in Active and Idle Modes TCLCH e TCHCL e 5 ns
10
8XC51GB
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters The first char-
acter is always a ``T'' (stands for time) The other
characters depending on their positions stand for
the name of a signal or the logical status of that
signal The following is a list of all the characters and
what they stand for
A Address
C Clock
D Input Data
H Logic Level HIGH
I Instruction (Program Memory Contents)
L Logic Level LOW or ALE
P PSEN
Q Output Data
R RD Signal
T Time
V Valid
W WR Signal
X No Longer a Valid Logic Level
Z Float
For Example
TAVLL e Time from Address Valid to ALE Low
TLLPL e Time from ALE Low to PSEN Low
AC SPECIFICATIONS
Over Operating Conditions Load Capacitance on Port 0 ALE and PSEN e 100 pF Load Capacitance on all
other outputs e 80 pF
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
Symbol
Parameter
12 MHz Osc
Variable Osc
Units
Min
Max
Min
Max
1 TCLCL
Osc Freq
3 5
16
MHz
TLHLL
ALE Pulse Width
127
2TCLCL b 40
ns
TAVLL
ADDR Valid to ALE Low
43
TCLCL b 40
ns
TLLAX
ADDR Hold after ALE Low
53
TCLCL b 30
ns
TLLIV
ALE Low to Valid Inst IN
234
4TCLCL b 100
ns
TLLPL
ALE LOW to PSEN LOW
53
TCLCL b 30
ns
TPLPH
PSEN Pulse Width
205
3TCLCL b 45
ns
TPLIV
PSEN Low to Valid Instr In
145
3TCLCL b 105
ns
TPXIX
Input Instr Hold after PSEN
0
0
ns
TPXIZ
Input Instr Float after PSEN
59
TCLCL b 25
ns
TAVIV
ADDR to Valid Instr In
312
5TCLCL b 105
ns
TPLAZ
PSEN Low to ADDR Float
10
10
ns
TRLRH
RD Pulse Width
400
6TCLCL b 100
ns
TWLWH
WR Pulse Width
400
6TCLCL b 100
ns
TRLDV
RD Low to Valid Data In
252
5TCLCL b 165
ns
TRHDX
Data Hold after RD
0
0
ns
TRHDZ
Data Float after RD
107
2TCLCL b 60
ns
TLLDV
ALE Low to Valid Data In
517
8TCLCL b 150
ns
TAVDV
ADDR to Valid Data In
585
9TCLCL b 165
ns
TLLWL
ALE Low to RD or WR Low
200
300
3TCLCL b 50
3TCLCL a 50
ns
TAVWL
ADDR Valid to RD or WR Low
203
4TCLCL b 130
ns
TQVWX
Data Valid to WR Transition
33
TCLCL b 50
ns
TWHQX
Data Hold after WR
33
TCLCL b 50
ns
TQVWH
Data Valid to WR High
433
7 TCLCL b 150
ns
TRLAZ
RD Low to Addr Float
0
0
ns
TWHLH
RD or WR High to ALE High
43
123
TCLCL b 40
TCLCL a 40
ns
11
8XC51GB
EXTERNAL PROGRAM MEMORY READ CYCLE
272337 11
EXTERNAL DATA MEMORY READ CYCLE
272337 12
EXTERNAL DATA MEMORY WRITE CYCLE
272337 13
12
8XC51GB
SERIAL PORT TIMING
SHIFT REGISTER MODE
Test Conditions Over Operating Conditions Load Capacitance e 80 pF
Symbol
Parameter
12 MHz
Variable
Units
Oscillator
Oscillator
Min
Max
Min
Max
TXLXL
Serial Port Clock
1
12TCLCL
m
s
Cycle Time
TQVXH
Output Data Setup to
700
10TCLCL b 133
ns
Clock Rising Edge
TXHQX
Output Data Hold after
50
2TCLCL b 117
ns
Clock Rising Edge
TXHDX
Input Data Hold after
0
0
ns
Clock Rising Edge
TXHDV
Clock Rising Edge to
700
10TCLCL b 133
ns
Input Data Valid
SHIFT REGISTER MODE TIMING WAVEFORMS
272337 14
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
1 TCLCL
Oscillator Frequency
3 5
16
MHz
TCHCX
High Time
20
ns
TCLCX
Low Time
20
ns
TCLCH
Rise Time
20
ns
TCHCL
Fall Time
20
ns
EXTERNAL CLOCK DRIVE WAVEFORM
272337 15
13
8XC51GB
SEP AC TIMING SPECIFICATIONS
Test Conditions Over Operating Conditions Load Capacitance e 80 pF
Symbol
Parameter
12 MHz
Variable
Units
Oscillator
Oscillator
Min
Max
Min
Max
TXSXL
SEPCLK Cycle Time
1
12 TCLCL
m
s
TXSST
Output Data Setup to SEPCLK
435
6 TCLCL b 65
ns
TXSOH
Output Data Hold after SEPCLK
445
6 TCLCL b 55
ns
TXSIH
Input Data Hold after SEPCLK
210
2 TCLCL a 43
ns
Sampling Edge
TXSDV
Input Data Valid to SEPCLK
947
12 TCLCL b 53
ns
Sampling Edge
SEP Waveform
(SEPS1 e 0 SEPS0 e 0 CLKPOL e 0 CLKPH e 0)
272337 16
272337 17
14
8XC51GB
AC TESTING INPUT OUTPUT WAVEFORMS
272337 18
AC inputs during testing are driven at V
CC
b
0 5V for a Logic
``1'' and 0 5V for a Logic ``0'' Timing measurements are
made at V
IH
for a Logic ``1'' and V
OL
max for a Logic ``0''
FLOAT WAVEFORMS
272337 19
For timing purposes a port pin is no longer floating
when a 100 mV change from load voltage occurs
and begins to float when a 100 mV change from
the loaded V
OH
V
OL
level occurs I
OL
I
OH
t g
20
mA
A TO D CHARACTERISTICS
The absolute conversion accuracy is dependent on
the accuracy of AV
REF
The specifications given be-
low assume adherence to the Operating Conditions
section of this data sheet
Testing is done at
AV
REF
e
5 12V and V
CC
e
5 0V
OPERATING CONDITIONS
V
CC
4 0V to 6 0V
AV
REF
4 5V to 5 5V
V
SS
AV
SS
0V
ACH0 7
AV
SS
to V
REF
T
A
0 C to a70 C Ambient
FOSC (STD Version)
3 5 MHz to 12 MHz
FOSC (-1 Version)
3 5 MHz to 16 MHz
A D CONVERTER SPECIFICATIONS
T
A
e
0 C to a70 C
Parameter
Min
Typ
Max
Units
Notes
Resolution
256
256
Levels
8
8
Bits
Absolute Error (Ch 2 7)
0
g
1
LSB
Absolute Error (Ch 0 and 1)
0
g
2
LSB
Full Scale Error
g
1
LSB
Zero Offset Error
g
1
LSB
Non-Linearity
0
g
1
LSB
Differential Non-Linearity
0
g
1
LSB
Channel-to-Channel Matching
0
g
1
LSB
Repeatability
g
0 25
LSB
15
8XC51GB
A D CONVERTER SPECIFICATIONS
T
A
e
0 C to a70 C (Continued)
Parameter
Min
Typ
Max
Units
Notes
Temperature Coefficients
Offset
0 003
LSB C
Full Scale
0 003
LSB C
Differential Non-Linearity
0 003
LSB C
Input Capacitance
3
pF
Off Isolation
b
60
dB
(8 9)
Feedthrough
b
60
dB
(8)
V
CC
Power Supply Rejection
b
60
dB
(8)
Input Resistance to
750
1 2K
X
Sample-and-Hold Capacitor
DC Input Leakage
0
3 0
m
A
NOTES
These values are expected for most parts at 25 C
AN ``LSB'' as used here has a value of approximately 20 mV
8 DC to 100 KHz
9 Multiplexer Break-Before-Make Guaranteed
10 There is no indication when a single A D conversion is complete Please refer to the 8XC51GB Hardware Description on
how to read a single A D conversion
11 T
CY
e
12 TCLCL
A D Conversion Time
Notes
Per Channel
26 T
CY
(10 11)
8 Conversions
208 T
CY
(11)
16
8XC51GB
PROGRAMMING THE OTP
The part must be running with a 4 MHz to 6 MHz
oscillator The address of a location to be pro-
grammed is applied to address lines while the code
byte to be programmed in that location is applied to
data lines Control and program signals must be held
at the levels indicated in Table 2 Normally EA V
PP
is held at logic high until just before ALE PROG is to
be pulsed The EA V
PP
is raised to V
PP
ALE PROG
is pulsed low and then EA V
PP
is returned to a high
(also refer to timing diagrams)
NOTE
Exceeding the V
PP
maximum for any amount of
time could damage the device permanently The
V
PP
source must be well regulated and free of
glitches
DEFINITION OF TERMS
ADDRESS LINES
P1 0 P1 7 P2 0 P2 4 respec-
tively for A0 A12
DATA LINES
P0 0 P0 7 for D0 D7
CONTROL SIGNALS
RST PSEN P2 6 P2 7 P3 3
P3 6 P3 7
PROGRAM SIGNALS
ALE PROG EA V
PP
272337 20
See Table 2 for proper input on these pins
Figure 11 Programming the OTP
Table 2 OTP Programming Modes
Mode
RST
PSEN
ALE
EA
P2 6
P2 7
P3 3
P3 6
P3 7
PROG
V
PP
Program Code Data
L
L
12 75V
L
H
H
H
H
Verify Code Data
L
L
H
H
L
L
L
H
H
Program Encryption
L
L
12 75V
L
H
H
L
H
Array Address 0 3FH
Program Lock
Bit 1
L
L
12 75V
H
H
H
H
H
Bits
Bit 2
L
L
12 75V
H
H
H
L
L
Bit 3
L
L
12 75V
H
L
H
H
L
Read Signature Byte
L
H
H
H
L
L
L
L
L
17
8XC51GB
PROGRAMMING ALGORITHM
Refer to Table 2 and Figures 11 and 12 for address
data and control signals set up To program the
87C51GB the following sequence must be exer-
cised
1 Input the valid address on the address lines
2 Input the appropriate data byte on the data lines
3 Activate the correct combination of control sig-
nals
4 Raise EA V
PP
from V
CC
to 12 75V
g
0 25V
5 Pulse ALE PROG 5 times for the OTP array and
25 times for the encryption table and the lock
bits
Repeat 1 through 5 changing the address and data
for the entire array or until the end of the object file is
reached
PROGRAM VERIFY
Program verify may be done after each byte that is
programmed or after a block of bytes that is pro-
grammed In either case a complete verify of the
array will ensure that it has been programmed cor-
rectly
The lock bits cannot be directly verified Verification
of the lock bits is done by observing that their fea-
tures are enabled Refer to the Program Lock sec-
tion in this data sheet
272337 21
Figure 12 Programming Signal's Waveforms
18
8XC51GB
ROM and EPROM Lock System
The 87C51GB and the 83C51GB program lock sys-
tems when programmed protect the on-board pro-
gram against software piracy
The 83C51GB has a one-level program lock system
and a 64-byte encryption table See line 2 of Table
3 If program protection is desired the user submits
the encryption table with their code and both the
lock bit and encryption array are programmed by the
factory The encryption array is not available without
the lock bit For the lock bit to be programmed the
user must submit an encryption table
The 87C51GB has a 3-level program lock system
and a 64-byte encryption array Since this is an
EPROM device all locations are user programma-
ble See Table 3
Encryption Array
Within the programmable array are 64 bytes of En-
cryption Array that are initially unprogrammed (all
1's) Every time that a byte is addressed during a
verify 5 address lines are used to select a byte of
the Encryption Array This byte is then exclusive-
NOR'ed (XNOR) with the code byte creating an En-
cryption Verify byte The algorithm with the array in
the unprogrammed state (all 1's) will return the
code in its original unmodified form For program-
ming the Encryption Array refer to Table 2
When using the encryption array feature one impor-
tant factor needs to be considered If a code byte
has the value 0FFH verification of the byte will pro-
duce the encryption byte value If a large block (
l
64
bytes) of code is left unprogrammed a verification
routine will display the contents of the encryption
array For this reason it is strongly recommended
that all unused code bytes be programmed with
some value other than 0FFH and not all of them the
same value This practice will ensure the maximum
possible program protection
Program Lock Bits
The 87C51GB has 3 programmable lock bits that
when programmed according to Table 3 will provide
different levels of protection for the on-chip code
and data
The 83C51GB has 1 program lock bit
See line 2 of Table 3
Reading the Signature Bytes
The 8XC51GB has 3 signature bytes in locations
30H 31H and 60H To read these bytes follow the
procedure for verify but activate the control lines
provided in Table 2 for Read Signature Byte
Location
Contents
87C51GB
83C51GB
30H
89H
89H
31H
58H
58H
60H
EBH
EBH 6BH
Table 3 Program Lock Bits and the Features
Program Lock Bits
Protection Type
LB1
LB2
LB3
1
U
U
U
No Program Lock features enabled (Code verify will
still be encrypted by the Encryption Array if
programmed)
2
P
U
U
MOVC instructions executed from external program
memory are disabled from fetching code bytes from
internal memory EA is sampled and latched on
Reset and further programming of the EPROM is
disabled
3
P
P
U
Same as 2 also verify is disabled
4
P
P
P
Same as 3 also external execution is disabled
Any other combination of lock bits is not defined
19
8XC51GB
OTP PROGRAMMING AND VERIFICATION CHARACTERISTICS
(T
A
e
21 C to 27 C V
CC
e
5V
g
20% V
SS
e
0V)
Symbol
Parameter
Min
Max
Units
V
PP
Programming Supply Voltage
12 5
13 0
V
I
PP
Programming Supply Current
75
mA
1 TCLCL
Oscillator Frequency
4
6
MHz
TAVGL
Address Setup to PROG Low
48TCLCL
TGHAX
Address Hold after PROG
48TCLCL
TDVGL
Data Setup to PROG Low
48TCLCL
TGHDX
Data Hold after PROG
48TCLCL
TEHSH
(Enable) High to V
PP
48TCLCL
TSHGL
V
PP
Setup to PROG Low
10
m
s
TGHSL
V
PP
Hold after PROG
10
m
s
TGLGH
PROG Width
90
110
m
s
TAVQV
Address to Data Valid
48TCLCL
TELQV
ENABLE Low to Data Valid
48TCLCL
TEHQZ
Data Float after ENABLE
0
48TCLCL
TGHGL
PROG High to PROG Low
10
m
s
PROGRAMMING AND VERIFICATION WAVEFORMS
272337 22
25 Pulses for Encryption Table and Lock Bits
20
8XC51GB
A D Glossary of Terms
Absolute Error
The maximum difference between
corresponding actual and ideal code transitions Ab-
solute Error accounts for all deviations of an actual
converter from an ideal converter
Actual Characteristic
The characteristic of an ac-
tual converter The characteristic of a given convert-
er may vary over temperature supply voltage and
frequency conditions An actual characteristic rarely
has ideal first and last transition locations or ideal
code widths It may even vary over multiple conver-
sions under the same conditions
Break-Before-Make
The property of a multiplexer
which guarantees that a previously selected channel
will be deselected before a new channel is selected
(e g the converter will not short inputs together)
Channel-to-Channel Matching
The difference be-
tween corresponding code transitions of actual char-
acteristics taken from different channels under the
same temperature voltage and frequency condi-
tions
Characteristic
A graph of input voltage versus the
resultant output code for an A D converter It de-
scribes the transfer function of the A D converter
Code
The digital value output by the converter
Code Center
The voltage corresponding to the
midpoint between two adjacent code transitions
Code Transition
The point at which the converter
changes from an output code of Q to a code of Q a
1 The input voltage corresponding to a code tran-
sition is defined to be that voltage which is equally
likely to produce either of two adjacent codes
Code Width
The voltage corresponding to the dif-
ference between two adjacent code transitions
Crosstalk
See ``Off-Isolation''
DC Input Leakage
Leakage current to ground
from an analog input pin
Differential
Non-Linearity
The difference be-
tween the ideal and actual code widths of the termi-
nal based characteristic
Feedthrough
Attenuation of a voltage applied on
the selected channel of the A D Converter after the
sample window closes
Full Scale Error
The difference between the ex-
pected and actual input voltage corresponding to
the full scale code transition
Ideal Characteristic
A characteristic with its first
code transition at V
IN
e
0 5 LSB its last code tran-
sition at V
IN
e
(V
REF
b
1 5 LSB) and all code
widths equal to one LSB
Input Resistance
The effective series resistance
from the analog input pin to the sample capacitor
LSB
Least Significant Bit
The voltage corre-
sponding to the full scale voltage divided by 2
n
where n is the number of bits of resolution of the
converter For an 8-bit converter with a reference
voltage of 5 12V one LSB is 20 mV Note that this is
different than digital LSBs since an uncertainty of
two LSBs when referring to an A D converter
equals 40 mV (This has been confused with an un-
certainty of two digital bits which would mean four
counts or 80 mV)
Monotonic
The property of successive approxi-
mation converters which guarantees that increasing
input voltages produce adjacent codes of increasing
value and that decreasing input voltages produce
adjacent codes of decreasing value
No Missed Codes
For each and every output
code there exists a unique input voltage range
which produces that code only
Non-Linearity
The maximum deviation of code
transitions of the terminal based characteristic from
the corresponding code transitions of the ideal char-
acteristic
Off-Isolation
Attenuation of a voltage applied on a
deselected channel of the A D converter (Also re-
ferred to as Crosstalk )
Repeatability
The
difference
between
corre-
sponding code transitions from different actual char-
acteristics taken from the same converter on the
same channel at the same temperature voltage and
frequency conditions
Resolution
The number of input voltage levels
that the converter can unambiguously distinguish
between Also defines the number of useful bits of
information which the converter can return
Sample Delay
The delay from receiving the start
conversion signal to when the sample window
opens
Sample Delay Uncertainty
The variation in the
sample delay
Sample Time
The time that the sample window is
open
Sample Time Uncertainty
The variation in the
sample time
21
8XC51GB
Sample Window
Begins when the sample capaci-
tor is attached to a selected channel and ends when
the sample capacitor is disconnected from the se-
lected channel
Successive Approximation
An A D conversion
method which uses a binary search to arrive at the
best digital representation of an analog input
Temperature Coefficients
Change in the stated
variable
per
degree
centrigrade
temperature
change Temperature coefficients are added to the
typical values of a specification to see the effect of
temperature drift
Terminal Based Characteristic
An actual charac-
teristic which has been rotated and translated to re-
move zero offset and full scale error
V
CC
Rejection
Attenuation of noise on the V
CC
line to the A D converter
Zero Offset
The difference between the expected
and actual input voltage corresponding to the first
code transition
DATA SHEET REVISION SUMMARY
The following differences exist between this data-
sheet and the previous version (270869-003)
1 Merged 87C51GB Express (270889-001)
2 New order number 272337-001
The following differences exist between the 270869-
003 data sheet and the previous version (270869-
002)
1 Changed data sheet status from ``Advance Infor-
mation'' to ``Preliminary'' and updated associated
notices
2 Added 83C51GB throughout
3 Added Package and Process Information
4 Clarified
g
2 LSB accuracy for channels 0 and 1
in A D Converter Section
5 Added ``ROM and EPROM Lock System'' section
and added 83C51GB to ``Program Lock Bits''
section
6 Modified Signature Bytes Table
The
following
differences
exist
between
the
270869-002 data sheet and the previous version
(270869-001)
1 Changed data sheet status from ``Product Pre-
view'' to ``Advance Information'' and updated as-
sociated notices
2 Asynchronous port reset was added to RESET
pin description
3 ALE disable paragraph was added to ALE pin de-
scription
4 C
1
C
2
guidelines clarified in Figure 4
5 Operating Conditions heading was added
6 Maximum I
OL
per I O pin was added to Absolute
Maximum Ratings
7 VT
a
VT
b
V
HYS
V
OL2
and V
TL
removed
8 V
OL
value for ALE included with V
OL1
9 V
IL1
and V
IL2
added
10 RRST minimum changed from 40K to 50K
RRST maximum changed from 225K to 300K
11 I
PD
maximum changed from 200 mA to 50 mA
12 I
DL
maximum changed from 15 mA to 18 mA
13 Typical values for I
PD
I
DL
I
CC
and I
REF
re-
moved
14 Note 3 (page 9) was reworded
15 SEP AC Timings added
16 A D Absolute Error for Channels 0 and 1
changed to
g
2 LSB
17 T
CY
clarified
18 Encryption array paragraph was added
19 Corrected pin numbers on Figure 11 to reflect
PLCC package
22