Intel
815EM Chipset: 82815EM
Graphics and Memory Controller
Hub (GMCH2-M)
Datasheet
April 2003
Document Reference Number:
290689-002
R
Intel
82815EM GMCH
R
2
Datasheet
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended
for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future
definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
815EM chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I
2
C is a 2-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed by Intel.
Implementations of the I
2
C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
Corporation.
Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
www.intel.com
or call 1-800-548-4725
*Third-party brands and names are the property of their respective owners.
Copyright Intel Corporation 2000
Intel
82815EM GMCH
R
Datasheet
3
Contents
1.
Overview.....................................................................................................................................13
1.1.
Component Identification via Programming Interface ...................................................13
1.2.
Component Marking Information ...................................................................................13
1.3.
The Intel
815EM Chipset System ................................................................................14
1.4.
Intel
815EM Chipset GMCH2-M Overview ..................................................................15
1.5.
Host Interface.................................................................................................................16
1.6.
System Memory Interface..............................................................................................17
1.7.
Multiplexed AGP and Display Cache Interface..............................................................17
1.8.
AGP Interface ................................................................................................................17
1.8.1.
Display Cache Interface...............................................................................18
1.9.
Hub Interface .................................................................................................................18
1.10.
GMCH2-M Integrated Graphics (GFX) Support ............................................................18
1.10.1.
Intel
Dynamic Video Memory Technology (D.V.M.T.) ...............................19
1.10.2.
Display 19
1.10.3.
Digital Video Out Port (DVO).......................................................................19
1.11.
System Clocking ............................................................................................................19
1.12.
GMCH2-M Power Delivery ............................................................................................19
1.13.
References.....................................................................................................................19
2.
Signal Description.......................................................................................................................20
2.1.
Host Interface Signals....................................................................................................21
2.2.
System Memory Interface Signals .................................................................................23
2.3.
AGP Interface Signals ...................................................................................................23
2.3.1.
AGP Addressing Signals .............................................................................23
2.3.2.
AGP Flow Control Signals ...........................................................................25
2.3.3.
AGP Status Signals .....................................................................................25
2.3.4.
AGP Clocking Signals - Strobes..................................................................26
2.3.5.
AGP FRAME# Signals.................................................................................27
2.3.6.
AGP C3 support Signals..............................................................................29
2.4.
Display Cache Interface Signals....................................................................................30
2.5.
Hub Interface Signals ....................................................................................................31
2.6.
Display Interface Signals ...............................................................................................31
2.7.
Digital Video Output Signals/TV-Out Pins .....................................................................32
2.8.
Power Signals ................................................................................................................33
2.9.
Clock Signals .................................................................................................................33
2.10.
Miscellaneous Interface Signals ....................................................................................34
2.11.
GMCH2-M Power-Up/Reset Strap Options ...................................................................34
2.12.
Multiplexed Display Cache and AGP Signal Mapping...................................................35
3.
PCI Configuration Registers.......................................................................................................36
3.1.
Register Nomenclature and Access Attributes..............................................................36
3.2.
GMCH2-M Register Introduction ...................................................................................37
3.3.
I/O Mapped Registers....................................................................................................37
3.3.1.
CONFIG_ADDRESS
Configuration Address Register .............................38
Intel
82815EM GMCH
R
4
Datasheet
3.3.2.
CONFIG_DATA
Configuration Data Register .......................................... 39
3.4.
PCI Bus Configuration Mechanism ............................................................................... 40
3.5.
PCI Configuration Space Access .................................................................................. 40
3.5.1.
Logical PCI Bus #0 Configuration Mechanism............................................ 41
3.5.2.
Primary PCI (PCI0) and Downstream Configuration Mechanism............... 41
3.5.3.
Internal Graphics Device (GFX) Configuration Mechanism........................ 41
3.6.
Host-Hub Interface Bridge/DRAM Controller Device Registers (Device #0) ................ 41
3.6.1.
VID--Vendor Identification Register (Device 0).......................................... 44
3.6.2.
DID--Device Identification Register (Device 0) .......................................... 44
3.6.3.
PCICMD--PCI Command Register (Device 0)........................................... 45
3.6.4.
PCISTS--PCI Status Register (Device 0) .................................................. 46
3.6.5.
RID--Revision Identification Register (Device 0) ....................................... 46
3.6.6.
SUBC--Sub-Class Code Register (Device 0) ............................................ 47
3.6.7.
BCC--Base Class Code Register (Device 0) ............................................. 47
3.6.8.
MLT--Master Latency Timer Register (Device 0) ...................................... 48
3.6.9.
HDR--Header Type Register (Device 0) .................................................... 48
3.6.10.
APBASE--Aperture Base Configuration Register (Device 0 - AGP MODE
ONLY) 49
3.6.11.
SVID--Subsystem Vendor Identification Register (Device 0) .................... 50
3.6.12.
SID--Subsystem Identification Register (Device 0) ................................... 50
3.6.13.
CAPPTR--Capabilities Pointer (Device 0) ................................................. 51
3.6.14.
GMCHCFG--GMCH2-M Configuration Register (Device 0) ...................... 51
3.6.15.
APCONT--Aperture Control (Device 0)...................................................... 53
3.6.16.
DRP--DRAM Row Population Register (Device 0) .................................... 54
3.6.17.
DRAMT--DRAM Timing Register (Device 0) ............................................. 55
3.6.18.
DRP2--DRAM Row Population Register 2 (Device 0) ............................... 56
3.6.19.
FDHC
Fixed DRAM Hole Control Register (Device 0) ........................... 57
3.6.20.
PAM
Programmable Attributes Map Registers (Device 0) ....................... 57
3.6.21.
C3STATUS --C3 Control and Status Register (Device #0) ....................... 60
3.6.22.
SMRAM - System Management RAM Control Register (Device 0)............ 61
3.6.23.
MISCC--Miscellaneous Control Register (Device 0) ................................. 63
3.6.24.
CAPID--Capability Identification (Device 0 - AGP MODE ONLY) ............. 64
3.6.25.
BUFF_SC--System Memory Buffer Strength Control Register (Device 0) 66
3.6.26.
BUFF_SC2-System Memory Buffer Strength Control Register 2 (Device 0)69
3.6.27.
ACAPID--AGP Capability Identifier Register (Device 0)............................ 70
3.6.28.
AGPSTAT--AGP Status Register (Device 0) ............................................. 71
3.6.29.
AGPCMD--AGP Command Register (Device 0)........................................ 72
3.6.30.
AGPCTRL--AGP Control Register (Device 0) ........................................... 73
3.6.31.
APSIZE--Aperture Size (Device 0)............................................................. 74
3.6.32.
ATTBASE-Aperture Translation Table Base Register (Device 0) .............. 75
3.6.33.
AMTT--AGP Multi-Transaction Timer (Device 0)....................................... 76
3.6.34.
LPTT--AGP Low Priority Transaction Timer Register (Device 0) .............. 77
3.6.35.
GMCHCFG--GMCH2-M Configuration Register (Device 0) ...................... 78
3.6.36.
ERRCMD--Error Command Register (Device 0) ....................................... 79
3.7.
AGP/PCI Bridge Registers (Device #1 - Visible in AGP Mode Only)......................... 80
3.7.1.
VID1--Vendor Identification Register (Device 1)........................................ 81
3.7.2.
DID1--Device Identification Register (Device 1) ........................................ 81
3.7.3.
PCICMD1--PCI-PCI Command Register (Device 1) ................................. 82
3.7.4.
PCISTS1--PCI-PCI Status Register (Device 1) ......................................... 83
3.7.5.
RID1--Revision Identification Register (Device 1) ..................................... 84
3.7.6.
SUBC1--Sub-Class Code Register (Device 1) .......................................... 84
3.7.7.
BCC1--Base Class Code Register (Device 1) ........................................... 85
3.7.8.
MLT1--Master Latency Timer Register (Device 1) .................................... 85
Intel
82815EM GMCH
R
Datasheet
5
3.7.9.
HDR1--Header Type Register (Device 1) ..................................................85
3.7.10.
PBUSN--Primary Bus Number Register (Device 1) ...................................86
3.7.11.
SBUSN--Secondary Bus Number Register (Device 1) ..............................86
3.7.12.
SUBUSN--Subordinate Bus Number Register (Device 1) .........................86
3.7.13.
SMLT--Secondary Master Latency Timer Register (Device 1) ..................87
3.7.14.
IOBASE--I/O Base Address Register (Device 1) .......................................88
3.7.15.
IOLIMIT--I/O Limit Address Register (Device 1) ........................................89
3.7.16.
SSTS--Secondary PCI-PCI Status Register (Device 1) ............................90
3.7.17.
MBASE--Memory Base Address Register (Device 1) ................................91
3.7.18.
MLIMIT--Memory Limit Address Register (Device 1) .................................92
3.7.19.
PMBASE--Prefetchable Memory Base Address Register (Device 1) ........93
3.7.20.
PMLIMIT--Prefetchable Memory Limit Address Register (Device 1) .........94
3.7.21.
BCTRL--PCI-PCI Bridge Control Register (Device 1)................................95
3.7.22.
ERRCMD1--Error Command Register (Device 1)......................................97
3.8.
Graphics Device Registers (Device 2 - VISIBLE IN GFX MODE ONLY)......................97
3.8.1.
VID2--Vendor Identification Register (Device 2) ........................................98
3.8.2.
DID2--Device Identification Register (Device 2).........................................99
3.8.3.
PCICMD2--PCI Command Register (Device 2) .........................................99
3.8.4.
PCISTS2--PCI Status Register (Device 2)...............................................101
3.8.5.
RID2--Revision Identification Register (Device 2)....................................102
3.8.6.
PI--Programming Interface Register (Device 2) .......................................102
3.8.7.
SUBC2--Sub-Class Code Register (Device 2).........................................102
3.8.8.
BCC2--Base Class Code Register (Device 2)..........................................103
3.8.9.
CLS--Cache Line Size Register (Device 2)..............................................103
3.8.10.
MLT2--Master Latency Timer Register (Device 2) ...................................103
3.8.11.
HDR2--Header Type Register (Device 2) ................................................104
3.8.12.
BIST--BIST Register (Device 2) ...............................................................104
3.8.13.
GMADR-Graphics Memory Range Address Register (Device 2) ............105
3.8.14.
MMADR--Memory Mapped Range Address Register (Device 2) ............106
3.8.15.
SVID--Subsystem Vendor Identification Register (Device 2)..................106
3.8.16.
SID--Subsystem Identification Register (Device 2) ..................................107
3.8.17.
ROMADR - Video BIOS ROM Base Address Registers (Device 2)..........107
3.8.18.
CAPPOINT--Capabilities Pointer Register (Device 2)..............................107
3.8.19.
INTRLINE--Interrupt Line Register (Device 2) .........................................108
3.8.20.
INTRPIN--Interrupt Pin Register (Device 2) .............................................108
3.8.21.
MINGNT--Minimum Grant Register (Device 2) ........................................108
3.8.22.
MAXLAT--Maximum Latency Register (Device 2) ...................................108
3.8.23.
PM_CAPID--Power Management Capabilities ID Register (Device 2)....109
3.8.24.
PM_CAP--Power Management Capabilities Register (Device 2) ............109
3.8.25.
PM_CS - Power Management Control/Status Register (Device 2)...........110
4.
Functional Description ..............................................................................................................112
4.1.
System Memory and I/O Address Map........................................................................112
4.1.1.
Memory Address Space ............................................................................112
4.2.
DOS Compatibility Memory Space ..............................................................................115
4.2.1.1.
DOS Area (00000h-9FFFh) ..........................................................116
4.2.1.2.
Video Buffer Area (A0000h-BFFFFh) ...........................................116
4.2.1.3.
Monochrome Adapter (MDA) Range (B0000h - B7FFFh) ............116
4.2.1.4.
Expansion Area (C0000h-DFFFFh)..............................................117
4.2.1.5.
Extended System BIOS Area (E0000h-EFFFFh) .........................117
4.2.1.6.
System BIOS Area (F0000h-FFFFFh)..........................................117
4.3.
Extended Memory Area ...............................................................................................117
4.3.1.
Main DRAM Address Range (0010_0000h to TOM).................................117
4.3.1.1.
15MB-16MB Hole Area .................................................................117
PDF 
ZIP