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March 1996
COPYRIGHT
INTEL CORPORATION 1996
Order Number 290477-004
82375EB 82375SB PCI-EISA BRIDGE (PCEB)
Y
Provides the Bridge Between the PCI
Local Bus and EISA Bus
Y
100% PCI and EISA Compatible
PCI and EISA Master Slave Interface
Directly Drives 10 PCI Loads and 8
EISA Slots
Supports PCI from 25 to 33 MHz
Y
Data Buffers Improve Performance
Four 32-bit PCI-to-EISA Posted Write
Buffers
Four 16-byte EISA-to-PCI Read Write
Line Buffers
EISA-to-PCI Read Prefetch
EISA-to-PCI and PCI-to-EISA Write
Posting
Y
Data Buffer Management Ensures Data
Coherency
Flush Posted Write Buffers
Flush or Invalidate Line Buffers
System-Wide Data Buffer Coherency
Control
Y
Burst Transfers on both the PCI and
EISA Buses
Y
32-Bit Data Paths
Y
Integrated EISA Data Swap Buffers
Y
Arbitration for PCI Devices
Supports Six PCI Masters
Fixed Rotating or a Combination of
the Two
Supports External PCI Arbiter and
Arbiter Cascading
Y
PCI and EISA Address Decoding and
Mapping
Positive Decode of Main Memory
Areas (MEMCS
Generation)
Four Programmable PCI Memory
Space Regions
Four Programmable PCI I O Space
Regions
Y
Programmable Main Memory Address
Decoding
Main Memory Sizes up to
512 MBytes
Access Attributes for 15 Memory
Segments in First 1 MByte of Main
Memory
Programmable Main Memory Hole
Y
Integrated 16-bit BIOS Timer
Y
Only Available as Part of a Supported
Kit
The 82375EB SB PCI-EISA Bridge (PCEB) provides the master slave functions on both the PCI Local Bus
and the EISA Bus Functioning as a bridge between the PCI and EISA buses the PCEB provides the address
and data paths bus controls and bus protocol translation for PCI-to-EISA and EISA-to-PCI transfers Exten-
sive data buffering in both directions increases system performance by maximizing PCI and EISA Bus efficien-
cy and allowing concurrency on the two buses The PCEB's buffer management mechanism ensures data
coherency The PCEB integrates central bus control functions including a programmable bus arbiter for the
PCI Bus and EISA data swap buffers for the EISA Bus Integrated system functions include PCI parity genera-
tion system error reporting and programmable PCI and EISA memory and I O address space mapping and
decoding The PCEB also contains a BIOS Timer that can be used to implement timing loops The PCEB is
intended to be used with the EISA System Component (ESC) to provide an EISA I O subsystem interface
This document describes both the 82375EB and 82375SB components Unshaded areas describe the
82375EB Shaded areas like this one describe the 82375SB operations that differ from the 82375EB
82375EB SB
290477 1
PCEB Simplified Block Diagram
2
82375EB 82375SB PCI-EISA BRIDGE (PCEB)
CONTENTS
PAGE
1 0 ARCHITECTURAL OVERVIEW
8
1 1 PCEB Overview
10
1 2 ESC Overview
12
2 0 SIGNAL DESCRIPTION
14
2 1 PCI Bus Interface Signals
15
2 2 PCI Arbiter Signals
18
2 3 Address Decoder Signals
19
2 4 EISA Interface Signals
20
2 5 ISA Interface Signals
23
2 6 PCEB ESC Interface Signals
24
2 7 Test Signal
26
3 0 REGISTER DESCRIPTION
27
3 1 Configuration Registers
27
3 1 1 VID
VENDOR IDENTIFICATION REGISTER
29
3 1 2 DID
DEVICE IDENTIFICATION REGISTER
29
3 1 3 PCICMD
PCI COMMAND REGISTER
30
3 1 4 PCISTS
PCI STATUS REGISTER
31
3 1 5 RID
REVISION IDENTIFICATION REGISTER
31
3 1 6 MLT
MASTER LATENCY TIMER REGISTER
32
3 1 7 PCICON
PCI CONTROL REGISTER
32
3 1 8 ARBCON
PCI ARBITER CONTROL REGISTER
33
3 1 9 ARBPRI
PCI ARBITER PRIORITY CONTROL REGISTER
34
3 1 10 ARBPRIX
PCI ARBITER PRIORITY CONTROL EXTENSION REGISTER
35
3 1 11 MCSCON
MEMCS
CONTROL REGISTER
35
3 1 12 MCSBOH
MEMCS
BOTTOM OF HOLE REGISTER
36
3 1 13 MCSTOH
MEMCS
TOP OF HOLE REGISTER
37
3 1 14 MCSTOM
MEMCS
TOP OF MEMORY REGISTER
37
3 1 15 EADC1
EISA ADDRESS DECODE CONTROL 1 REGISTER
38
3 1 16 IORT
ISA I O RECOVERY TIMER REGISTER
39
3 1 17 MAR1
MEMCS
ATTRIBUTE REGISTER
1
40
3 1 18 MAR2
MEMCS
ATTRIBUTE REGISTER
2
40
3 1 19 MAR3
MEMCS
ATTRIBUTE REGISTER
3
41
3 1 20 PDCON
PCI DECODE CONTROL REGISTER
42
3 1 21 EADC2
EISA ADDRESS DECODE CONTROL EXTENSION REGISTER
43
3
CONTENTS
PAGE
3 1 22 EPMRA
EISA-TO-PCI MEMORY REGION ATTRIBUTES REGISTER
44
3 1 23 MEMREGN 4 1
EISA-TO-PCI MEMORY REGION ADDRESS REGISTERS
45
3 1 24 IOREGN 4 1
EISA-TO-PCI I O REGION ADDRESS REGISTERS
46
3 1 25 BTMR
BIOS TIMER BASE ADDRESS REGISTER
46
3 1 26 ELTCR
EISA LATENCY TIMER CONTROL REGISTER
47
3 2 I O Registers
47
3 2 1 BIOSTM
BIOS TIMER REGISTER
47
4 0 ADDRESS DECODING
48
4 1 PCI Cycle Address Decoding
50
4 1 1 MEMORY SPACE ADDRESS DECODING
51
4 1 1 1 Main Memory Decoding (MEMCS )
51
4 1 1 2 BIOS Memory Space
54
4 1 1 3 Subtractively And Negatively Decoded Cycles To EISA
54
4 1 2 PCEB CONFIGURATION REGISTERS
56
4 1 3 PCEB I O REGISTERS
56
4 1 4 POSITIVELY DECODED COMPATIBILITY I O REGISTERS
56
4 1 4 1 ESC Resident PIC Registers
57
4 1 4 2 EISA Resident IDE Registers
57
4 2 EISA Cycle Address Decoding
58
4 2 1 POSITIVELY DECODED MEMORY CYCLES TO MAIN MEMORY
58
4 2 2 PROGRAMMABLE EISA-TO-PCI MEMORY ADDRESS REGIONS
61
4 2 3 PROGRAMMABLE EISA-TO-PCI I O ADDRESS REGIONS
61
4 2 4 EXTERNAL EISA-TO-PCI I O ADDRESS DECODER
62
4 3 Palette DAC Snoop Mechanism
62
5 0 PCI INTERFACE
62
5 1 PCI Bus Transactions
63
5 1 1 PCI COMMAND SET
63
5 1 2 PCI CYCLE DESCRIPTIONS
64
5 1 2 1 Interrupt Acknowledge
64
5 1 2 2 Special Cycle
65
5 1 2 3 I O Read
65
5 1 2 4 I O Write
65
5 1 2 5 Memory Read
66
5 1 2 6 Memory Write
67
5 1 2 7 Configuration Read Configuration Write
67
5 1 2 8 Memory Read Multiple
68
4
CONTENTS
PAGE
5 1 2 9 Memory Read Line
68
5 1 2 10 Memory Write And Invalidate
68
5 1 3 PCI TRANSFER BASICS
68
5 1 3 1 Turn-Around-Cycle Definition
69
5 1 3 2 Idle Cycle Definition
69
5 1 4 BASIC READ
71
5 1 5 BASIC WRITE
72
5 1 6 CONFIGURATION CYCLES
73
5 1 7 INTERRUPT ACKNOWLEDGE CYCLE
74
5 1 8 EXCLUSIVE ACCESS
75
5 1 9 DEVICE SELECTION
77
5 1 10 TRANSACTION TERMINATION
78
5 1 10 1 Master Initiated Termination
78
5 1 10 2 Target Initiated Termination
79
5 1 10 3 PCEB Target Termination Conditions
81
5 1 10 4 PCEB Master Termination Conditions
81
5 1 10 5 PCEB Responses Results Of Termination
81
5 1 11 PCI DATA TRANSFERS WITH SPECIFIC BYTE ENABLE COMBINATIONS
82
5 2 PCI Bus Latency
82
5 2 1 MASTER LATENCY TIMER (MLT)
82
5 2 2 INCREMENTAL LATENCY MECHANISM
83
5 3 PCI Bus Parity Support And Error Reporting
83
5 3 1 PARITY GENERATION AND CHECKING
83
5 3 1 1 Address Phase
84
5 3 1 2 Data Phase
84
5 3 2 PARITY ERROR
PERR
SIGNAL
84
5 3 3 SYSTEM ERRORS
84
5 4 PCI Bus Arbitration
85
5 4 1 PCI ARBITER CONFIGURATION
85
5 4 1 1 Fixed Priority Mode
87
5 4 1 2 Rotating Priority Mode
89
5 4 1 3 Mixed Priority Mode
89
5 4 1 4 Locking Masters
89
5 4 2 ARBITRATION SIGNALING PROTOCOL
89
5 4 2 1 REQ
and GNT
Rules
90
5 4 2 2 Back-to-Back Transactions
90
5
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