GD82559ER Fast Ethernet**
PCI Controller
Networking Silicon
Datasheet
Product Features
s
Optimum Integration for Lowest Cost
Solution
-- Integrated IEEE 802.3 10BASE-T and
100BASE-TX compatible PHY
-- Glueless 32-bit PCI master interface
-- 128 Kbyte Flash interface
-- Thin BGA 15mm
2
package
-- ACPI and PCI Power Management
-- Power management event on
"interesting" packets and link status
change support
-- Test Access Port
s
High Performance Networking Functions
-- Chained memory structure similar to the
82559,82558, 82557, and 82596
-- Improved dynamic transmit chaining
with multiple priorities transmit queues
-- Full Duplex support at both 10 and 100
Mbps
-- IEEE 802.3u Auto-Negotiation support
-- 3 Kbyte transmit and 3 Kbyte receive
FIFOs
-- Fast back-to-back transmission support
with minimum interframe spacing
-- IEEE 802.3x 100BASE-TX Flow
Control support
-- Low Power Features
-- Low power 3.3 V device
-- Efficient dynamic standby mode
-- Deep power down support
-- Clockrun protocol support
Document Number: 714682-001
Revision 1.0
March 1999
GD82559ER - Networking Silicon
ii
Datasheet
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 82559 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copyright Intel Corporation, 1999
* Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.
** Third-party brands and names are the property of their respective owners.
Revision History
Revision
Date
Revision
Description
Mar. 1999
1.0
First release.
Datasheet
iii
Networking Silicon -- GD82559ER
Contents
1.
INTRODUCTION ............................................................................................................................. 1
1.1
GD82559ER Overview ....................................................................................................... 1
1.2
Suggested Reading ............................................................................................................ 1
2.
GD82559ER ARCHITECTURAL OVERVIEW ................................................................................ 3
2.1
Parallel Subsystem Overview ............................................................................................. 3
2.2
FIFO Subsystem Overview................................................................................................. 4
2.3
10/100 Mbps Serial CSMA/CD Unit Overview.................................................................... 5
2.4
10/100 Mbps Physical Layer Unit ....................................................................................... 5
3.
SIGNAL DESCRIPTIONS ............................................................................................................... 7
3.1
Signal Type Definitions ....................................................................................................... 7
3.2
PCI Bus Interface Signals................................................................................................... 7
3.2.1
Address and Data Signals .................................................................................. 7
3.2.2
Interface Control Signals .................................................................................... 8
3.2.3
System and Power Management Signals........................................................... 9
3.3
Local Memory Interface Signals ......................................................................................... 9
3.4
Testability Port Signals ..................................................................................................... 10
3.5
PHY Signals ..................................................................................................................... 11
4.
GD82559ER MEDIA ACCESS CONTROL FUNCTIONAL DESCRIPTION ................................. 13
4.1
82559ER Initialization ....................................................................................................... 13
4.1.1
Initialization Effects on 82559ER Units ............................................................ 13
4.2
PCI Interface..................................................................................................................... 14
4.2.1
82559ER Bus Operations................................................................................. 14
4.2.2
Clockrun Signal ................................................................................................ 22
4.2.3
Power Management Event Signal .................................................................... 22
4.2.4
Power States .................................................................................................... 23
4.2.5
Wake-up Events ...............................................................................................27
4.3
Parallel Flash Interface ..................................................................................................... 28
4.4
Serial EEPROM Interface ................................................................................................. 28
4.5
10/100 Mbps CSMA/CD Unit ............................................................................................ 30
4.5.1
Full Duplex ....................................................................................................... 31
4.5.2
Flow Control ..................................................................................................... 31
4.5.3
Address Filtering Modifications......................................................................... 31
4.5.4
Long Frame Reception ..................................................................................... 31
4.6
Media Independent Interface (MII) Management Interface............................................... 32
5.
GD82559ER TEST PORT FUNCTIONALITY ............................................................................... 33
5.1
Introduction ....................................................................................................................... 33
5.2
Asynchronous Test Mode ................................................................................................. 33
5.3
Test Function Description ................................................................................................. 33
5.4
85/85................................................................................................................................. 33
5.5
TriState ............................................................................................................................. 34
5.6
Nand - Tree ...................................................................................................................... 34
6.
GD82559ER PHYSICAL LAYER FUNCTIONAL DESCRIPTION ................................................ 37
6.1
100BASE-TX PHY Unit .................................................................................................... 37
6.1.1
100BASE-TX Transmit Clock Generation ........................................................ 37
GD82559ER -- Networking Silicon
iv
Datasheet
6.1.2
100BASE-TX Transmit Blocks ......................................................................... 37
6.1.3
100BASE-TX Receive Blocks .......................................................................... 40
6.1.4
100BASE-TX Collision Detection ..................................................................... 41
6.1.5
100BASE-TX Link Integrity and Auto-Negotiation Solution.............................. 41
6.1.6
Auto 10/100 Mbps Speed Selection ................................................................. 41
6.2
10BASE-T Functionality ................................................................................................... 41
6.2.1
10BASE-T Transmit Clock Generation............................................................. 41
6.2.2
10BASE-T Transmit Blocks.............................................................................. 42
6.2.3
10BASE-T Receive Blocks............................................................................... 42
6.2.4
10BASE-T Collision Detection.......................................................................... 43
6.2.5
10BASE-T Link Integrity ................................................................................... 43
6.2.6
10BASE-T Jabber Control Function ................................................................. 43
6.2.7
10BASE-T Full Duplex ..................................................................................... 43
6.3
Auto-Negotiation Functionality.......................................................................................... 43
6.3.1
Description ....................................................................................................... 44
6.3.2
Parallel Detect and Auto-Negotiation ............................................................... 44
6.4
LED Description................................................................................................................ 45
7.
PCI CONFIGURATION REGISTERS ........................................................................................... 47
7.1
LAN (Ethernet) PCI Configuration Space ......................................................................... 47
7.1.1
PCI Vendor ID and Device ID Registers .......................................................... 47
7.1.2
PCI Command Register ................................................................................... 48
7.1.3
PCI Status Register.......................................................................................... 49
7.1.4
PCI Revision ID Register.................................................................................. 50
7.1.5
PCI Class Code Register ................................................................................. 50
7.1.6
PCI Cache Line Size Register.......................................................................... 50
7.1.7
PCI Latency Timer............................................................................................ 51
7.1.8
PCI Header Type.............................................................................................. 51
7.1.9
PCI Base Address Registers............................................................................ 51
7.1.10 PCI Subsystem Vendor ID and Subsystem ID Registers ................................. 53
7.1.11 Capability Pointer ............................................................................................. 53
7.1.12 Interrupt Line Register...................................................................................... 53
7.1.13 Interrupt Pin Register ....................................................................................... 54
7.1.14 Minimum Grant Register .................................................................................. 54
7.1.15 Maximum Latency Register.............................................................................. 54
7.1.16 Capability ID Register....................................................................................... 54
7.1.17 Next Item Pointer.............................................................................................. 54
7.1.18 Power Management Capabilities Register ....................................................... 54
7.1.19 Power Management Control/Status Register (PMCSR)................................... 55
7.1.20 Data Register ................................................................................................... 56
8.
CONTROL/STATUS REGISTERS................................................................................................ 57
8.1
LAN (Ethernet) Control/Status Registers.......................................................................... 57
8.1.1
System Control Block Status Word .................................................................. 58
8.1.2
System Control Block Command Word ............................................................ 59
8.1.3
System Control Block General Pointer............................................................. 59
8.1.4
PORT ............................................................................................................... 59
8.1.5
Flash Control Register...................................................................................... 59
8.1.6
EEPROM Control Register............................................................................... 59
8.1.7
Management Data Interface Control Register.................................................. 59
8.1.8
Receive Direct Memory Access Byte Count..................................................... 60
8.1.9
Early Receive Interrupt..................................................................................... 60
Datasheet
v
Networking Silicon -- GD82559ER
8.1.10 Flow Control Register ....................................................................................... 60
8.1.11 Power Management Driver Register ................................................................ 60
8.1.12 General Control Register..................................................................................61
8.1.13 General Status Register ................................................................................... 61
8.2
Statistical Counters........................................................................................................... 62
9.
PHY UNIT REGISTERS ................................................................................................................ 65
9.1
MDI Registers 0 - 7........................................................................................................... 65
9.1.1
Register 0: Control Register Bit Definitions ..................................................... 65
9.1.2
Register 1: Status Register Bit Definitions ....................................................... 66
9.1.3
Register 2: PHY Identifier Register Bit Definitions ........................................... 67
9.1.4
Register 3: PHY Identifier Register Bit Definitions ........................................... 67
9.1.5
Register 4: Auto-Negotiation Advertisement Register Bit Definitions .............. 67
9.1.6
Register 5: Auto-Negotiation Link Partner Ability Register Bit Definitions ....... 67
9.1.7
Register 6: Auto-Negotiation Expansion Register Bit Definitions .................... 68
9.2
MDI Registers 8 - 15......................................................................................................... 68
9.3
MDI Register 16 - 31 ........................................................................................................ 68
9.3.1
Register 16: PHY Unit Status and Control Register Bit Definitions ................. 68
9.3.2
Register 17: PHY Unit Special Control Bit Definitions .....................................69
9.3.3
Register 18: PHY Address Register ................................................................. 70
9.3.4
Register 19: 100BASE-TX Receive False Carrier Counter Bit Definitions ...... 70
9.3.5
Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions ......... 70
9.3.6
Register 21: 100BASE-TX Receive Error Frame Counter Bit Definitions ........ 70
9.3.7
Register 22: Receive Symbol Error Counter Bit Definitions ............................ 70
9.3.8
Register 23: 100BASE-TX Receive Premature End of Frame Error Counter
Bit Definitions .................................................................................................. 71
9.3.9
Register 24: 10BASE-T Receive End of Frame Error Counter Bit Definitions . 71
9.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions ........ 71
9.3.11 Register 26: Equalizer Control and Status Bit Definitions ................................ 71
9.3.12 Register 27: PHY Unit Special Control Bit Definitions .....................................71
10.
ELECTRICAL AND TIMING SPECIFICATIONS .......................................................................... 73
10.1 Absolute Maximum Ratings .............................................................................................. 73
10.2 DC Specifications ............................................................................................................73
10.3 AC Specifications ............................................................................................................. 76
10.4 Timing Specifications........................................................................................................ 77
10.4.1 Clocks Specifications ....................................................................................... 77
10.4.2 Timing Parameters ........................................................................................... 78
12.
PACKAGE AND PINOUT INFORMATION ................................................................................... 85
12.1 Package Information......................................................................................................... 85
12.2 Pinout Information ............................................................................................................86
12.2.1 GD82559ER Pin Assignments ........................................................................ 86
12.2.2 GD82559ER Ball Grid Array Diagram ............................................................. 88
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