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Электронный компонент: 82562EZ

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82562EZ 10/100 Mbps Platform LAN
Connect (PLC)
Networking Silicon
Datasheet
Product Features
IEEE 802.3 10BASE-T/100BASE-TX
compliant physical layer interface
IEEE 802.3u Auto-Negotiation support
Digital Adaptive Equalization control
Link status interrupt capability
XOR tree mode support
3-port LED support (speed, link and
activity)
10BASE-T auto-polarity correction
LAN Connect interface
82540EM layout compatible
Diagnostic loopback mode
1:1 transmit transformer ratio support
Low power (less than 300 mW in active
transmit mode)
Reduced power in "unplugged mode" (less
than 50 mW)
Automatic detection of "unplugged mode"
3.3 V device
Thin BGA 15mm
2
package
82562EX with Alert on LAN support
available
Lead-free
a
196-pin Ball Grid Array (BGA).
(Devices that are lead-free are marked with
a circled "e1" and have the product code:
LUxxxxxx.)
a.This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity
at <1000 ppm.
The Material Declaration Data Sheet, which includes lead impurity levels and the concentration
of other Restriction on Hazardous Substances (RoHS)-banned materials, is available at:
ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmark
In addition, this device has been tested and conforms to the same parametric specifications as previous versions
of the device.
For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales repre-
sentative.
Revision 1.5
January 2005
ii
Datasheet
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating
to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 82562EZ may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright 2004, Intel Corporation
* Other product and corporate names may be trademarks of other companies and are used only for explanation and to the owners' benefit, without
intent to infringe.
Datasheet
iii
Networking Silicon -- 82562EZ
Revision History
Revision
Revision Date
Description
0.5
Sep 2001
Initial release (Intel Secret)
0.6
Oct 2001
Update to Table 10 - Pin Assignments (Intel Secret)
1.0
Apr 2002
Added part number (Intel Confidential)
1.1
Jul 2002
Table 15- Pin assignments revised from Rev. 1.3 to Rev 2.0
1.2
Nov 2003
Removed confidential status
1.3
Nov 2004
Updated signal names to match design guides and reference schematics.
1.4
Nov 2004
Added lead-free information.
Added Test Port Functionality section.
Added information about migrating from a 2-layer 0.36 mm wide-trace sub-
strate to a 2-layer 0.32 mm wide-trace substrate. Refer to the section on
Package and Pinout Information.
Added statement that no changes to existing soldering processes are
needed for the 2-layer 0.32 mm wide-trace substrate change in the section
describing "Package Information".
1.5
January 2005
Added a note for PHY signals RBIAS100 and RBIAS10 to Section 3.3.
82562EZ -- Networking Silicon
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Datasheet
Note:
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Datasheet
v
Networking Silicon -- 82562EZ
Contents
1.0
Introduction.........................................................................................................................1
1.1
Overview ...............................................................................................................1
1.2
Scope ....................................................................................................................1
1.3
Features ................................................................................................................1
1.4
Reference Documents...........................................................................................2
2.0
82562EZ Architectural Overview........................................................................................3
3.0
82562EZ Signal Descriptions .............................................................................................5
3.1
Signal Type Definitions .........................................................................................5
3.2
Twisted Pair Ethernet (TPE) Pins .........................................................................5
3.3
External Bias Pins ................................................................................................5
3.4
Clock Pins ............................................................................................................6
3.5
Platform LAN Connect Interface Pins....................................................................6
3.6
LED Pins ..............................................................................................................7
3.7
Miscellaneous Control Pins ..................................................................................7
3.8
Power and Ground Connections ..........................................................................8
4.0
Physical Layer Interface Functionality................................................................................9
4.1
100BASE-TX Mode ...............................................................................................9
4.1.1
100BASE-TX Transmit Blocks .................................................................9
4.1.2
100BASE-TX Receive Blocks ................................................................11
4.2
10BASE-T Mode .................................................................................................12
4.2.1
10BASE-T Transmit Blocks....................................................................12
4.2.2
10BASE-T Receive Blocks.....................................................................12
4.3
Analog References..............................................................................................13
4.4
Dynamic Reduced Power & Auto Plugging Detection.........................................14
4.4.1
Auto Plugging Detection.........................................................................14
4.4.2
Dynamic Reduced Power.......................................................................14
4.4.3
Configuration ..........................................................................................14
4.5
Reset ...................................................................................................................15
4.6
LAN Connect Interface ........................................................................................15
4.6.1
LAN Connect Clock ................................................................................15
4.6.2
LAN Connect Reset................................................................................15
4.7
LED Functionality ...............................................................................................15
5.0
Platform LAN Connect Registers .....................................................................................17
5.1
Medium Dependent Interface Registers 0 through 7...........................................17
5.1.1
Register 0: Control Register Bit Definitions ...........................................17
5.1.2
Register 1: Status Register Bit Definitions ............................................18
5.1.3
Register 2: PHY Identifier Register Bit Definitions ................................19
5.1.4
Register 3: PHY Identifier Register Bit Definitions ................................19
5.1.5
Register 4: Auto-Negotiation Advertisement Register Bit Definitions ....19
5.1.6
Register 5: Auto-Negotiation
Link Partner Ability Register Bit Definitions ...........................................20
5.1.7
Register 6: Auto-Negotiation Expansion Register Bit Definitions ..........20
5.2
Medium Dependent Interface Registers 8 through 15.........................................20