82803AA MRH-R
R
Datasheet
2
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The Intel
82803AA Memory Repeater Hub for RDRAM (MRH-R) may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I
2
C is a 2-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed by Intel. Implementations
of the I
2
C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation.
Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM
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Copyright Intel Corporation 2000
82803AA
MRH-R
R
Datasheet
3
Contents
1. Overview.......................................................................................................................................9
1.1. System
Architecture .........................................................................................................9
1.2.
`Expansion' Channel Interface .......................................................................................10
1.3.
MRH-R Direct RDRAM `Stick' Channel Interface...........................................................10
1.4. Register
Interface...........................................................................................................11
1.5. Terminology ...................................................................................................................11
2. Signal
Description.......................................................................................................................13
2.1.
`Expansion' Channel Interface .......................................................................................13
2.2.
`Stick' Channel A Interface.............................................................................................14
2.3.
`Stick' Channel B Interface.............................................................................................15
2.4.
Miscellaneous Signals Interface.....................................................................................15
2.4.1.
MRH_SIO and SMBus Signal Interface .......................................................15
2.4.2.
Clocks, Reset, and Miscellaneous ...............................................................16
2.4.3.
Voltage/Ground References .......................................................................16
3. Register
Description ...................................................................................................................17
3.1.
MDID--MRH-R Device ID Register ...............................................................................17
3.2.
EXCC--Expansion Bus Current Control Register .........................................................18
3.3.
CACC--Channel A Current Control Register.................................................................18
3.4.
CBCC--Channel B Current Control Register.................................................................19
3.5.
SPDRDR--SPD Read Data and Status Register ..........................................................19
3.6.
CCR--Clock Control Register........................................................................................20
3.7.
LMTR--Levelization Mode And Timing Register ...........................................................20
3.7.1.
RIR--RAC Initialization Register..................................................................22
3.8.
RACAL--Stick Channel A RAC Configuration Low WORD Register ............................23
3.9.
RACAH--Stick Channel A RAC Configuration High WORD Register...........................23
3.10. RACBL--Stick Channel B RAC Configuration Low Word Register ...............................23
3.11. RACBH--Stick Channel B RAC Configuration High Word Register..............................24
3.12. RACXL--Expansion Channel RAC Configuration Low Word Register .........................24
3.13. RACXH--Expansion Channel RAC Configuration High Word Register ........................25
3.14. INIT--MRH-R Initialization Register...............................................................................25
3.15. CNFGA--MRH-R Configuration Register ......................................................................26
3.16. ST--Stepping
Register ..................................................................................................26
4. Functional
Description ................................................................................................................27
4.1.
MRH-R and the Direct RDRAM Channel .......................................................................27
4.1.1. Operation
Overview .....................................................................................27
4.1.2.
Signal and Protocol Overview......................................................................27
4.1.2.1.
Refresh and Post-Refresh Precharge.............................................28
4.1.2.2.
Power Mode Control........................................................................28
4.1.2.3. Current
Calibration ..........................................................................28
4.1.2.4.
Thermal Sensor Read .....................................................................29
4.1.2.5. Temperature
Calibration .................................................................29
4.1.3. CMOS
Protocol ............................................................................................29
82803AA MRH-R
R
Datasheet
4
4.1.3.1. Overview......................................................................................... 29
4.1.3.2. Packet
Formats .............................................................................. 30
4.1.3.3. Transactions ................................................................................... 33
4.1.3.4. Levelization ..................................................................................... 34
4.1.3.5. Initialization ..................................................................................... 34
4.1.3.6.
MRH-R Register Operations........................................................... 34
4.1.3.7.
RDRAM Register Operations.......................................................... 35
4.1.4. SMBUS
Operation ....................................................................................... 35
4.1.4.1.
SIO Request Packet for SPD Random Read ................................. 36
4.1.4.2.
SIO Request Packet for SPD Write Command .............................. 37
4.1.4.3.
Command Protocol and Bus Timing............................................... 38
4.2. Reset ............................................................................................................................. 39
4.3. Power
Management ...................................................................................................... 39
4.4. STR
Support.................................................................................................................. 39
5.
Ballout and Package Information ............................................................................................... 41
5.1. MRH-R
Ballout............................................................................................................... 41
5.2. Package
Specifications ................................................................................................. 46
5.3.
MRH-R RSL Normalized Trace Length Data................................................................. 48
6. Testability ................................................................................................................................... 51
6.1. Tri-state
Mode ............................................................................................................... 51
6.2.
XOR Chain Mode .......................................................................................................... 51