ChipFind - документация

Электронный компонент: 82803AA

Скачать:  PDF   ZIP

Document Outline

Intel
82803AA Memory Repeater
Hub for RDRAM (MRH-R)

Datasheet
August 2000


R
Order Number:
298022 - 002
82803AA MRH-R
R
Datasheet
2
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness
for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in
medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future
definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
82803AA Memory Repeater Hub for RDRAM (MRH-R) may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I
2
C is a 2-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed by Intel. Implementations
of the I
2
C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation.
Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
www.intel.com
or call 1-800-548-4725
*Third-party brands and names are the property of their respective owners.
Copyright Intel Corporation 2000
82803AA
MRH-R
R
Datasheet
3
Contents
1. Overview.......................................................................................................................................9
1.1. System
Architecture .........................................................................................................9
1.2.
`Expansion' Channel Interface .......................................................................................10
1.3.
MRH-R Direct RDRAM `Stick' Channel Interface...........................................................10
1.4. Register
Interface...........................................................................................................11
1.5. Terminology ...................................................................................................................11
2. Signal
Description.......................................................................................................................13
2.1.
`Expansion' Channel Interface .......................................................................................13
2.2.
`Stick' Channel A Interface.............................................................................................14
2.3.
`Stick' Channel B Interface.............................................................................................15
2.4.
Miscellaneous Signals Interface.....................................................................................15
2.4.1.
MRH_SIO and SMBus Signal Interface .......................................................15
2.4.2.
Clocks, Reset, and Miscellaneous ...............................................................16
2.4.3.
Voltage/Ground References .......................................................................16
3. Register
Description ...................................................................................................................17
3.1.
MDID--MRH-R Device ID Register ...............................................................................17
3.2.
EXCC--Expansion Bus Current Control Register .........................................................18
3.3.
CACC--Channel A Current Control Register.................................................................18
3.4.
CBCC--Channel B Current Control Register.................................................................19
3.5.
SPDRDR--SPD Read Data and Status Register ..........................................................19
3.6.
CCR--Clock Control Register........................................................................................20
3.7.
LMTR--Levelization Mode And Timing Register ...........................................................20
3.7.1.
RIR--RAC Initialization Register..................................................................22
3.8.
RACAL--Stick Channel A RAC Configuration Low WORD Register ............................23
3.9.
RACAH--Stick Channel A RAC Configuration High WORD Register...........................23
3.10. RACBL--Stick Channel B RAC Configuration Low Word Register ...............................23
3.11. RACBH--Stick Channel B RAC Configuration High Word Register..............................24
3.12. RACXL--Expansion Channel RAC Configuration Low Word Register .........................24
3.13. RACXH--Expansion Channel RAC Configuration High Word Register ........................25
3.14. INIT--MRH-R Initialization Register...............................................................................25
3.15. CNFGA--MRH-R Configuration Register ......................................................................26
3.16. ST--Stepping
Register ..................................................................................................26
4. Functional
Description ................................................................................................................27
4.1.
MRH-R and the Direct RDRAM Channel .......................................................................27
4.1.1. Operation
Overview .....................................................................................27
4.1.2.
Signal and Protocol Overview......................................................................27
4.1.2.1.
Refresh and Post-Refresh Precharge.............................................28
4.1.2.2.
Power Mode Control........................................................................28
4.1.2.3. Current
Calibration ..........................................................................28
4.1.2.4.
Thermal Sensor Read .....................................................................29
4.1.2.5. Temperature
Calibration .................................................................29
4.1.3. CMOS
Protocol ............................................................................................29
82803AA MRH-R
R
Datasheet
4
4.1.3.1. Overview......................................................................................... 29
4.1.3.2. Packet
Formats .............................................................................. 30
4.1.3.3. Transactions ................................................................................... 33
4.1.3.4. Levelization ..................................................................................... 34
4.1.3.5. Initialization ..................................................................................... 34
4.1.3.6.
MRH-R Register Operations........................................................... 34
4.1.3.7.
RDRAM Register Operations.......................................................... 35
4.1.4. SMBUS
Operation ....................................................................................... 35
4.1.4.1.
SIO Request Packet for SPD Random Read ................................. 36
4.1.4.2.
SIO Request Packet for SPD Write Command .............................. 37
4.1.4.3.
Command Protocol and Bus Timing............................................... 38
4.2. Reset ............................................................................................................................. 39
4.3. Power
Management ...................................................................................................... 39
4.4. STR
Support.................................................................................................................. 39
5.
Ballout and Package Information ............................................................................................... 41
5.1. MRH-R
Ballout............................................................................................................... 41
5.2. Package
Specifications ................................................................................................. 46
5.3.
MRH-R RSL Normalized Trace Length Data................................................................. 48
6. Testability ................................................................................................................................... 51
6.1. Tri-state
Mode ............................................................................................................... 51
6.2.
XOR Chain Mode .......................................................................................................... 51
82803AA
MRH-R
R
Datasheet
5
Figures
Figure 1. Intel
840 Chipset Memory Subsystem with MRH-Rs.................................................9
Figure 2. 82840 MCH to 82803AA MRH-R Interconnect Diagram ...........................................10
Figure 3. Connection of CMOS Signals....................................................................................30
Figure 4. Expansion Bus Register Read Packet Format ..........................................................31
Figure 5. Expansion Bus Register Write Packet Format ..........................................................31
Figure 6. Expansion Bus Non-Register Operation Packet Format...........................................31
Figure 7. ExSIO Reset Sequence.............................................................................................33
Figure 8. RDRAM SIO Reset Sequence...................................................................................33
Figure 9. MRH-R Register Read...............................................................................................34
Figure 10. MRH-R Register Write.............................................................................................34
Figure 11. RDRAM Register Read from the Expansion Serial Bus..........................................35
Figure 12. RDRAM Register Write from the Expansion Serial Bus..........................................35
Figure 13. SMBUS SIO Random Read Request Packet Format .............................................36
Figure 14. SPDR Command sequence ....................................................................................36
Figure 15. SMBUS Transactions to Read EEPROM................................................................36
Figure 16. SMBUS SIO Random Write Request Packet Format .............................................37
Figure 17. SPDW Command sequence ...................................................................................37
Figure 18. SMBUS Transactions to Write to EEPROM............................................................37
Figure 19. SMBUS Start and Stop Conditions..........................................................................38
Figure 20. MRH-R Ballout (Top View, Left Side) ......................................................................42
Figure 21. MRH-R Ballout (Top View, Right Side)....................................................................43
Figure 22. Package Dimensions (324 BGA) Top and Side Views.........................................46
Figure 23. Package Dimensions (324 BGA) Bottom View ....................................................47
Tables
Table 1. Maximum Memory Support ..........................................................................................9
Table 2. Expansion Bus Serial Packet Field Definitions ...........................................................32
Table 3. Read Byte Protocol.....................................................................................................38
Table 4. MRH-R Alphabetical Ball Assignment ........................................................................44
Table 5. BGA Package Dimensions (324 BGA) .......................................................................47
Table 6. MRH-S RSL Normalized Trace Length Data..............................................................49
Table 7. MRH-R Test Modes....................................................................................................51
Table 8. MRH-R XOR Chains...................................................................................................52