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Intel
810 Chipset:
Intel
82810/82810-DC100 Graphics
and Memory Controller Hub (GMCH)
Datasheet
June 1999
Order Number: 290656-002
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Intel
82810/82810-DC100 (GMCH)
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2
Datasheet
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness
for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in
medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future
definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
810 and Intel
810-DC100 may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I
2
C is a 2-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed by Intel. Implementations
of the I
2
C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation.
Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
or call 1-800-548-4725
*Third-party brands and names are the property of their respective owners.
Copyright Intel Corporation 1998, 1999
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Intel
82810/82810-DC100 (GMCH)
Datasheet
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Contents
1.
Overview..................................................................................................................................... 11
1.1.
The Intel
810 Chipset System ..................................................................................... 11
1.2.
GMCH Overview ............................................................................................................ 14
1.3.
Host Interface ................................................................................................................ 15
1.4.
System Memory Interface.............................................................................................. 15
1.5.
Display Cache Interface (82810-DC100 Only)............................................................... 15
1.6.
Hub Interface ................................................................................................................. 15
1.7.
GMCH Graphics Support............................................................................................... 16
1.7.1.
Display, Digital Video Out, and LCD/Flat Panel ................................................ 16
1.8.
System Clocking ............................................................................................................ 17
1.9.
References .................................................................................................................... 17
2.
Signal Description....................................................................................................................... 19
2.1.
Host Interface Signals.................................................................................................... 20
2.2.
System Memory Interface Signals ................................................................................. 21
2.3.
Display Cache Interface Signals (82810-DC100 only)................................................... 22
2.4.
Hub Interface Signals .................................................................................................... 22
2.5.
Display Interface Signals ............................................................................................... 23
2.6.
Digital Video Output Signals/TV-Out Pins ..................................................................... 24
2.7.
Power Signals ................................................................................................................ 25
2.8.
Clock Signals ................................................................................................................. 25
2.9.
Miscellaneous Interface Signals .................................................................................... 26
2.10.
Power-Up/Reset Strap Options (82810) ........................................................................ 26
2.11.
Power-Up/Reset Strap Options (82810-DC100)............................................................ 26
3.
Configuration Registers .............................................................................................................. 27
3.1.
Register Nomenclature and Access Attributes .............................................................. 27
3.2.
PCI Configuration Space Access................................................................................... 28
3.2.1.
PCI Bus Configuration Mechanism ................................................................... 28
3.2.2.
Logical PCI Bus #0 Configuration Mechanism.................................................. 29
3.2.3.
Primary PCI (PCI0) and Downstream Configuration Mechanism ..................... 29
3.2.4.
Internal Graphics Device Configuration Mechanism ......................................... 29
3.2.5.
GMCH Register Introduction ............................................................................. 29
3.3.
I/O Mapped Registers.................................................................................................... 30
3.3.1.
CONFIG_ADDRESS
Configuration Address Register ................................... 30
3.3.2.
CONFIG_DATA
Configuration Data Register ................................................ 31
3.4.
Host-Hub Interface Bridge/DRAM Controller Device Registers (Device 0) ................... 31
3.4.1.
VID
Vendor Identification Register (Device 0) ................................................ 33
3.4.2.
DID
Device Identification Register (Device 0) ................................................ 33
3.4.3.
PCICMD
PCI Command Register (Device 0)................................................. 33
3.4.4.
PCISTS
PCI Status Register (Device 0) ........................................................ 35
3.4.5.
RID
Revision Identification Register (Device 0).............................................. 36
3.4.6.
SUBC
Sub-Class Code Register (Device 0) .................................................. 36
3.4.7.
BCC
Base Class Code Register (Device 0) ................................................... 36
3.4.8.
MLT
Master Latency Timer Register (Device 0)............................................. 37
3.4.9.
HDR
Header Type Register (Device 0) .......................................................... 37
Intel
82810/82810-DC100 (GMCH)
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4
Datasheet
3.4.10. SVID
Subsystem Vendor Identification Register (Device 0) .......................... 37
3.4.11. SID
Subsystem Identification Register (Device 0) ......................................... 38
3.4.12. CAPPTR
Capabilities Pointer (Device 0) ....................................................... 38
3.4.13. GMCHCFG
GMCH Configuration Register (Device 0) .................................. 39
3.4.14. PAMR--Programmable Attributes Register (Device 0) .................................... 40
3.4.15. DRP
DRAM Row Population Register (Device 0) .......................................... 41
3.4.16. DRAMT
DRAM Timing Register (Device 0) ................................................... 43
3.4.17. FCHC
Fixed DRAM Hole Control Register (Device 0)................................... 44
3.4.18. SMRAM
System Management RAM Control Register (Device 0) ................ 45
3.4.19. MISCC
Miscellaneous Control Register (Device 0) ....................................... 47
3.4.20. MISCC2
Miscellaneous Control 2 Register (Device 0) .................................. 48
3.4.21. BUFF_SC--System Memory Buffer Strength Control Register (Device 0) ...... 49
3.5.
Graphics Device Registers (Device 1) ....................................................................... 51
3.5.1.
VID
Vendor Identification Register (Device 1) ............................................... 52
3.5.2.
DID
Device Identification Register (Device 1)................................................ 52
3.5.3.
PCICMD
PCI Command Register (Device 1) ................................................ 53
3.5.4.
PCISTS
PCI Status Register (Device 1) ........................................................ 54
3.5.5.
RID
Revision Identification Register (Device 1) ............................................. 55
3.5.6.
PI-Programming Interface Register (Device 1) ................................................ 55
3.5.7.
SUBC1--Sub-Class Code Register (Device 1) ................................................ 55
3.5.8.
BCC1--Base Class Code Register (Device 1)................................................. 56
3.5.9.
CLS
Cache Line Size Register (Device 1) ..................................................... 56
3.5.10. MLT
Master Latency Timer Register (Device 1) ............................................ 56
3.5.11. HDR
Header Type Register (Device 1).......................................................... 57
3.5.12. BIST
Built In Self Test (BIST) Register (Device 1) ........................................ 57
3.5.13. GMADR
Graphics Memory Range Address Register (Device 1) .................. 58
3.5.14. MMADR
Memory Mapped Range Address Register (Device 1).................... 59
3.5.15. SVID
Subsystem Vendor Identification Register (Device 1) .......................... 59
3.5.16. SID
Subsystem Identification Register (Device 1) ......................................... 60
3.5.17. ROMADR
Video BIOS ROM Base Address Registers (Device 1)................ 60
3.5.18. CAPPOINT
Capabilities Pointer Register (Device 1)..................................... 60
3.5.19. INTRLINE
Interrupt Line Register (Device 1)................................................. 61
3.5.20. INTRPIN
Interrupt Pin Register (Device 1) .................................................... 61
3.5.21. MINGNT
Minimum Grant Register (Device 1) ............................................... 61
3.5.22. MAXLAT
Maximum Latency Register (Device 1) .......................................... 61
3.5.23. PM_CAPID
Power Management Capabilities ID Register (Device 1) ........... 62
3.5.24. PM_CAP
Power Management Capabilities Register (Device 1).................... 62
3.5.25. PM_CS--Power Management Control/Status Register (Device 1)................. 63
3.6.
Display Cache Interface (82810-DC100 Only) .............................................................. 64
3.6.1.
DRT--DRAM Row Type ................................................................................... 64
3.6.2.
DRAMCL--DRAM Control Low ........................................................................ 65
3.6.3.
DRAMCH--DRAM Control High....................................................................... 66
3.7.
Display Cache Detect and Diagnostic Registers (82810-DC100 Only)........................ 67
3.7.1.
GRX
GRX Graphics Controller Index Register .............................................. 67
3.7.2.
MSR
Miscellaneous Output ........................................................................... 68
3.7.3.
GR06
Miscellaneous Register ....................................................................... 69
3.7.4.
GR10
Address Mapping................................................................................. 70
3.7.5.
GR11
Page Selector ...................................................................................... 70
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Intel
82810/82810-DC100 (GMCH)
Datasheet
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4.
Functional Description ................................................................................................................ 71
4.1.
System Address Map..................................................................................................... 71
4.1.1.
Memory Address Ranges.................................................................................. 71
4.1.1.1. Compatibility Area ................................................................................ 72
4.1.1.2. Extended Memory Area........................................................................ 74
4.1.1.3. System Management Mode (SMM) Memory Range ............................ 76
4.1.2.
Memory Shadowing .......................................................................................... 76
4.1.3.
I/O Address Space ............................................................................................ 77
4.1.4.
GMCH Decode Rules and Cross-Bridge Address Mapping ............................. 77
4.2.
Host Interface ................................................................................................................ 78
4.2.1.
Host Bus Device Support .................................................................................. 78
4.2.2.
Special Cycles................................................................................................... 81
4.3.
System Memory DRAM Interface .................................................................................. 82
4.3.1.
DRAM Organization and Configuration............................................................. 82
4.3.1.1. Configuration Mechanism For DIMMs.................................................. 83
4.3.1.2. DRAM Register Programming.............................................................. 84
4.3.2.
DRAM Address Translation and Decoding ....................................................... 84
4.3.3.
DRAM Array Connectivity.................................................................................. 86
4.3.4.
SDRAMT Register Programming...................................................................... 86
4.3.5.
SDRAM Paging Policy....................................................................................... 87
4.4.
Intel
Dynamic Video Memory Technology (D.V.M.T.) .................................................. 87
4.5.
Display Cache Interface (82810-DC100 Only)............................................................... 87
4.5.1.
Supported DRAM Types ................................................................................... 88
4.5.2.
Memory Configurations ..................................................................................... 88
4.5.3.
Address Translation .......................................................................................... 89
4.5.4.
Display Cache Interface Timing ........................................................................ 89
4.6.
Internal Graphics Device ............................................................................................... 90
4.6.1.
3D/2D Instruction Processing ........................................................................... 90
4.6.2.
3D Engine ......................................................................................................... 91
4.6.3.
Buffers............................................................................................................... 91
4.6.4.
Setup................................................................................................................. 93
4.6.5.
Texturing ........................................................................................................... 93
4.6.6.
2D Operation..................................................................................................... 95
4.6.7.
Fixed Blitter (BLT) and Stretch Blitter (STRBLT) Engines ................................ 95
4.6.7.1. Fixed BLT Engine ................................................................................. 96
4.6.7.2. Arithmetic Stretch BLT Engine ............................................................. 96
4.6.8.
Hardware Motion Compensation....................................................................... 96
4.6.9.
Hardware Cursor............................................................................................... 97
4.6.10. Overlay Engine.................................................................................................. 97
4.6.11. Display............................................................................................................... 97
4.6.12. Flat Panel Interface / 1.8V TV-Out Interface..................................................... 99
4.6.13. DDC (Display Data Channel) .......................................................................... 100
4.7.
System Reset for the GMCH ....................................................................................... 101
4.8.
System Clock Description............................................................................................ 101
4.9.
Power Management..................................................................................................... 101
4.9.1.
Specifications Supported ................................................................................ 101
5.
Pinout and Package Information .............................................................................................. 103
5.1.
82810 and 82810-DC100 GMCH Pinout ..................................................................... 103
5.2.
Package Dimensions ................................................................................................... 109