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Электронный компонент: 82815EG

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AC'AC'




Intel
815 Chipset Family:
82815G/82815EG Graphics and
Memory Controller Hub (GMCH)
For Use with Universal Socket 370

Datasheet



September 6 2001










Document Number:
290714-001
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82815G GMCH Datasheet
Information in this document is provided in connection with Intel
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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
815 chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I
2
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed by Intel.
Implementations of the I
2
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Corporation.
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*Other names and brands may be claimed as the property of others.
Copyright
2001, Intel Corporation
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82815G GMCH Datasheet
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Contents
1
Introduction ........................................................................................................................13
1.1
Related Documents ..............................................................................................14
1.2
The Intel
815G Chipset .......................................................................................14
1.3
Intel
82815G GMCH Overview............................................................................16
1.4
Host Interface........................................................................................................17
1.5
System Memory Interface .....................................................................................17
1.6
Display Cache Interface........................................................................................17
1.7
Hub Interface ........................................................................................................18
1.8
Intel
82815G GMCH Integrated Graphics Support .............................................18
1.8.1
Display, Digital Video Out, and LCD/Flat Panel/Digital CRT .................18
1.9
System Clocking ...................................................................................................19
1.10
GMCH Power Delivery..........................................................................................19
2
Signal Description..............................................................................................................21
2.1
Host Interface Signals...........................................................................................22
2.2
System Memory Interface Signals ........................................................................24
2.3
Display Cache Interface Signals ...........................................................................25
2.4
Hub Interface Signals............................................................................................26
2.5
Display Interface Signals.......................................................................................26
2.6
Digital Video Output Signals/TV-Out Pins.............................................................27
2.7
Power Signals .......................................................................................................28
2.8
Clock Signals ........................................................................................................28
2.9
GMCH Power-Up/Reset Strap Options.................................................................29
2.10
Intel
815G Display Cache and Intel
815 AGP Signal Mapping..........................30
2.11
Display Cache Mapping at the AGP Connector ....................................................31
2.12
Intel
815 to Intel
815G Signal Name Changes ..................................................33
3
Configuration Registers .....................................................................................................35
3.1
Register Nomenclature and Access Attributes .....................................................35
3.2
PCI Configuration Space Access..........................................................................36
3.2.1
PCI Bus Configuration Mechanism .......................................................36
3.2.2
Logical PCI Bus #0 Configuration Mechanism ......................................37
3.2.3
Primary PCI (PCI0) and Downstream Configuration Mechanism .........37
3.2.4
Internal Graphics Device Configuration Mechanism .............................37
3.2.5
GMCH Register Introduction .................................................................38
3.3
I/O Mapped Registers ...........................................................................................38
3.3.1
CONF_ADDR
Configuration Address Register ..................................38
3.3.2
CONF_DATA
Configuration Data Register.........................................40
3.4
Host-Hub Interface Bridge/DRAM Controller Device Registers (Device 0) ..........41
3.4.1
VID--Vendor Identification Register (Device 0) ....................................43
3.4.2
DID--Device Identification Register (Device 0).....................................43
3.4.3
PCICMD--PCI Command Register (Device 0) .....................................44
3.4.4
PCISTS--PCI Status Register (Device 0).............................................45
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82815G GMCH Datasheet
3.4.5
RID--Revision Identification Register (Device 0)..................................46
3.4.6
SUBC--Sub-Class Code Register (Device 0).......................................46
3.4.7
BCC--Base Class Code Register (Device 0)........................................47
3.4.8
MLT--Master Latency Timer Register (Device 0).................................47
3.4.9
HDR--Header Type Register (Device 0) ..............................................47
3.4.10
APBASE--Aperture Base Configuration Register
(Device 0: AGP Mode Only) ..................................................................48
3.4.11
SVID--Subsystem Vendor Identification Register (Device 0) ...............50
3.4.12
SID--Subsystem Identification Register (Device 0) ..............................50
3.4.13
CAPPTR--Capabilities Pointer (Device 0)............................................50
3.4.14
GMCHCFG--GMCH Configuration Register (Device 0).......................51
3.4.15
APCONT--Aperture Control (Device 0) ................................................53
3.4.16
DRP--DRAM Row Population Register (Device 0)...............................54
3.4.17
DRAMT--DRAM Timing Register (Device 0)........................................55
3.4.18
DRP2--DRAM Row Population Register 2 (Device 0)..........................56
3.4.19
FDHC--Fixed DRAM Hole Control Register (Device 0)........................57
3.4.20
PAM--Programmable Attributes Map Registers (Device 0) .................57
3.4.21
SMRAM--System Management RAM Control Register (Device 0) .....62
3.4.22
MISCC--Miscellaneous Control Register (Device 0) ............................64
3.4.23
CAPID--Capability Identification (Device 0: AGP Mode Only).............66
3.4.24
BUFF_SC--System Memory Buffer Strength Control Register
(Device 0) ..............................................................................................67
3.4.25
BUFF_SC2--System Memory Buffer Strength Control Register 2
(Device 0) ..............................................................................................70
3.4.26
SM_RCOMP--System Memory R Compensation Control Register
(Device 0) ..............................................................................................71
3.4.27
SM--System Memory Control Register ................................................72
3.4.28
ACAPID--AGP Capability Identifier Register
(Device 0: AGP Mode Only) ..................................................................73
3.4.29
AGPSTAT--AGP Status Register (Device 0: AGP Mode Only) ..........74
3.4.30
AGPCMD--AGP Command Register (Device 0: AGP Mode Only) .....75
3.4.31
AGPCTRL--AGP Control Register (Device 0: AGP Mode Only).........76
3.4.32
APSIZE--Aperture Size (Device 0: AGP Mode Only) ...........................77
3.4.33
ATTBASE--Aperture Translation Table Base Register
(Device 0: AGP Mode Only) ..................................................................78
3.4.34
AMTT--AGP Multi-Transaction Timer (Device 0: AGP Mode Only) ....79
3.4.35
LPTT--AGP Low Priority Transaction Timer Register
(Device 0: AGP Mode Only) ..................................................................80
3.4.36
GMCHCFG--GMCH Configuration Register
(Device 0: AGP Mode Only) ..................................................................81
3.4.37
ERRCMD--Error Command Register (Device 0: AGP Mode Only) ....82
3.5
AGP/PCI Bridge Registers (Device 1: Visible in AGP Mode Only) ......................84
3.5.1
VID1--Vendor Identification Register (Device 1) ..................................85
3.5.2
DID1--Device Identification Register (Device 1)...................................85
3.5.3
PCICMD1--PCI-PCI Command Register (Device 1)............................85
3.5.4
PCISTS1--PCI-PCI Status Register (Device 1)....................................87
3.5.5
RID1--Revision Identification Register (Device 1)................................88
3.5.6
SUBC1--Sub-Class Code Register (Device 1).....................................88
3.5.7
BCC1--Base Class Code Register (Device 1)......................................88
3.5.8
MLT1--Master Latency Timer Register (Device 1)...............................89
3.5.9
HDR1--Header Type Register (Device 1) ............................................89
3.5.10
PBUSN--Primary Bus Number Register (Device 1) .............................89
3.5.11
SBUSN--Secondary Bus Number Register (Device 1) ........................90
3.5.12
SUBUSN--Subordinate Bus Number Register (Device 1)....................90
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82815G GMCH Datasheet
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3.5.13
SMLT--Secondary Master Latency Timer Register ( Device 1) ...........91
3.5.14
IOBASE--I/O Base Address Register (Device 1) .................................92
3.5.15
IOLIMIT--I/O Limit Address Register (Device 1) ..................................93
3.5.16
SSTS--Secondary PCI-PCI Status Register (Device 1) .......................94
3.5.17
MBASE--Memory Base Address Register (Device 1) ..........................95
3.5.18
MLIMIT--Memory Limit Address Register (Device 1)...........................96
3.5.19
PMBASE--Prefetchable Memory Base Address Register (Device 1) ..97
3.5.20
PMLIMIT--Prefetchable Memory Limit Address Register (Device 1) ...98
3.5.21
BCTRL--PCI-PCI Bridge Control Register (Device 1) ..........................99
3.5.22
ERRCMD1--Error Command Register (Device 1) .............................101
3.6
Graphics Device Registers (Device 2: Visible In GFX Mode Only)....................102
3.6.1
VID2--Vendor Identification Register (Device 2) ................................103
3.6.2
DID2--Device Identification Register (Device 2).................................103
3.6.3
PCICMD2--PCI Command Register (Device 2) .................................104
3.6.4
PCISTS2--PCI Status Register (Device 2).........................................105
3.6.5
RID2--Revision Identification Register (Device 2)..............................106
3.6.6
PI--Programming Interface Register (Device 2).................................106
3.6.7
SUBC2--Sub-Class Code Register (Device 2)...................................106
3.6.8
BCC2--Base Class Code Register (Device 2)....................................107
3.6.9
CLS--Cache Line Size Register (Device 2) ........................................107
3.6.10
MLT2--Master Latency Timer Register (Device 2).............................107
3.6.11
HDR2--Header Type Register (Device 2) ..........................................108
3.6.12
BIST--BIST Register (Device 2) .........................................................108
3.6.13
GMADR--Graphics Memory Range Address Register (Device 2) ....109
3.6.14
MMADR--Memory Mapped Range Address Register (Device 2).......110
3.6.15
SVID--Subsystem Vendor Identification Register (Device 2) .............110
3.6.16
SID--Subsystem Identification Register (Device 2) ............................111
3.6.17
ROMADR--Video BIOS ROM Base Address Register (Device 2) .....111
3.6.18
CAPPOINT--Capabilities Pointer Register (Device 2)........................112
3.6.19
INTRLINE--Interrupt Line Register (Device 2) ...................................112
3.6.20
INTRPIN--Interrupt Pin Register (Device 2) .......................................112
3.6.21
MINGNT--Minimum Grant Register (Device 2) ..................................112
3.6.22
MAXLAT--Maximum Latency Register (Device 2) .............................113
3.6.23
PM_CAPID--Power Management Capabilities ID Register
(Device 2) ............................................................................................113
3.6.24
PM_CAP--Power Management Capabilities Register (Device 2) ......114
3.6.25
PM_CS--Power Management Control/Status Register (Device 2)....115
3.7
Display Cache Interface......................................................................................116
3.7.1
DRT--DRAM Row Type......................................................................116
3.7.2
DRAMCL--DRAM Control Low...........................................................117
3.7.3
DRAMCH--DRAM Control High .........................................................118
3.8
Display Cache Detect and Diagnostic Registers ................................................119
3.8.1
GRX--GRX Graphics Controller Index Register.................................119
3.8.2
MSR
Miscellaneous Output ..............................................................120
3.8.3
GR06
Miscellaneous Register ..........................................................120
3.8.4
GR10
Address Mapping ...................................................................121
3.8.5
GR11
Page Selector.........................................................................121
4
Functional Description .....................................................................................................123
4.1
System Address Map..........................................................................................123
4.1.1
Memory Address Ranges....................................................................124
4.1.2
Compatibility Area ...............................................................................125
4.1.3
Extended Memory Area.......................................................................127