ADVANCE INFORMATION
COPYRIGHT INTEL CORPORATION, 1997
May 1997
Order Number: 272928-003
8
x
930H
x
UNIVERSAL SERIAL BUS HUB
PERIPHERAL CONTROLLER
s
USB Hub with One Upstream, One
Internal Downstream, and Three
External Downstream Ports on HD/HE
Parts or Four on HF/HG Parts
-- Complete Universal Serial Bus Speci-
fication 1.0 Compatibility
-- Serves as both USB Hub and USB
Embedded Function (Internal Port)
s
USB Hub
-- Connectivity Management
-- Downstream Device
Connect/Disconnect Detection
-- Power Management, Including
Suspend and Resume
-- Bus Fault Detection and Recovery
-- Full and Low Speed Downstream
Device Support
s
Output Pin for Port Power Switching
s
Input Pin for Overcurrent Detection
s
USB Embedded Function
-- Supports Isochronous and
Non-isochronous Data
s
On-chip USB Transceivers
s
Serial Bus Interface Engine (SIE)
-- Packet Decoding/Generation
-- CRC Generation and Checking
-- NRZI Encoding/Decoding and
Bit-stuffing
s
Hub FIFO Data Buffers
-- One Pair of 16-byte Transmit and
Receive FIFOs
-- One 1-byte Transmit Register
s
Embedded Function FIFO Data Buffers
-- Three Pairs of 16-byte Transmit and
Receive FIFOs
-- One Pair of Configurable Transmit
and Receive FIFOs (1 Kbyte total)
s
Automatic Transmit/Receive FIFO
Management
s
Three USB Interrupt Vectors
-- Endpoint Transmit/Receive Done
-- Start of Frame/Hub Endpoint Done
-- Global Suspend/Resume
s
Low Clock Mode
s
User-selectable Configurations
-- External Wait State
-- External Address Range
-- Page Mode
s
Real-time Wait Function
s
256-Kbyte External Code/Data Memory
Space
s
On-chip ROM Options
-- 0, 8, or 16 Kbytes
s
1024 bytes On-chip Data RAM
s
Four Input/Output Ports
s
Standard MCS
51 UART
s
Power-saving Idle and Powerdown
Modes
s
Register-based MCS
251 Architecture
s
Code-compatible with MCS 51 and
MCS 251 Microcontrollers
s
12-MHz Crystal Operation
The 8
x
930H
x
USB hub peripheral controller is based on the MCS
251 microcontroller. It consists of standard
8XC251Sx peripherals plus a USB module. The USB module provides both USB hub
and USB embedded
function capabilities. The 8
x
930H
x
supports USB hub functionality, embedded function, suspend/resume
modes, isochronous/non-isochronous transfers, and it is fully USB rev 1.0 specification compliant. The USB
module contains one internal and three (or four) external downstream ports and integrates the USB trans-
ceivers, serial bus interface engine (SIE), hub interface unit (HIU), function interface unit (FIU), and
transmit/receive FIFOs. The 8
x
930H
x
uses the standard instruction set of the MCS 251 architecture, which is
binary code compatible with the MCS
51 architecture.
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or oth-
erwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-548-4725
COPYRIGHT INTEL CORPORATION, 1997
iii
CONTENTS
1.0
About This Document.......................................................................................................... 1
1.1
Additional Information Sources ...................................................................................... 1
1.2
Electronic Information..................................................................................................... 1
1.3
Product Summary........................................................................................................... 2
2.0
Nomenclature Overview ...................................................................................................... 4
3.0
Pinout .................................................................................................................................. 6
4.0
Signals .............................................................................................................................. 12
5.0
Address Map ..................................................................................................................... 16
6.0
Electrical Characteristics ................................................................................................... 17
6.1
Operating Frequencies ................................................................................................. 17
6.2
DC Characteristics........................................................................................................ 18
6.3
Explanation of Timing Symbols .................................................................................... 20
6.4
System Bus AC Characteristics.................................................................................... 21
6.4.1
System Bus Timing Diagrams ...............................................................................23
6.4.2
Real-time Wait State Function AC Characteristics ................................................27
6.4.3
Real-time Wait State Function Timing Diagrams ..................................................28
6.5
AC Characteristics -- Synchronous Mode 0 ................................................................ 30
6.6
External Clock Drive ..................................................................................................... 30
6.7
Testing Waveforms ...................................................................................................... 31
7.0
Thermal Characteristics .................................................................................................... 32
8.0
Design Considerations ...................................................................................................... 32
8.1
External Bus Timing and Peripheral Timing Affected by PLLSEL2:0 Selection ........... 32
8.2
Low Clock Mode Frequency ......................................................................................... 32
8.3
Setting RXFFRC Bit Clears Only the Oldest Packet in the FIFO ................................. 32
8.4
Series Resistor Requirement for Impedance Matching ................................................ 32
8.5
Pullup Resistor Requirement for 8x930Hx Hub devices............................................... 32
8.6
Powerdown Mode Cannot Be Invoked Before USB Suspend ...................................... 32
8.7
Unused Downstream Ports........................................................................................... 33
9.0
8x930Hx Errata ................................................................................................................. 33
10.0 Datasheet Revision History ............................................................................................... 33
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
iv
Figures
1.
8x930Hx Block Diagram.......................................................................................................2
2.
8x930Hx USB Module Block Diagram..................................................................................3
3.
Product Nomenclature .........................................................................................................4
4.
8x930HD/HE and 8x930HF/HG 68-pin PLCC Package.......................................................6
5.
8x930HD/HE and 8x930HF/HG 64-pin SDIP Package ........................................................7
6.
8x930Hx Code Fetch, Nonpage Mode ...............................................................................23
7.
8x930Hx Data Read, Nonpage Mode ................................................................................24
8.
8x930Hx Data Write, Nonpage Mode.................................................................................24
9.
8x930Hx Code Fetch, Page Mode .....................................................................................25
10.
8x930Hx Data Read, Page Mode ......................................................................................26
11.
8x930Hx Data Write, Page Mode.......................................................................................26
12.
External Code Fetch/Data Read (Nonpage Mode, Real-time Wait State) .........................28
13.
External Data Write (Nonpage Mode, Real-time Wait State) .............................................28
14.
External Data Read (Page Mode, Real-time Wait State) ...................................................29
15.
External Data Write (Page Mode, Real-time Wait State) ...................................................29
16.
Serial Port Waveform -- Synchronous Mode 0..................................................................30
17.
External Clock Drive Waveforms........................................................................................30
18.
AC Testing Input, Output Waveforms.................................................................................31
19.
Float Waveforms ................................................................................................................31
Tables
1.
Related Documentation........................................................................................................1
2.
Electronic Information ..........................................................................................................1
3.
Description of Product Nomenclature...................................................................................4
5.
Downstream Port Allocation .................................................................................................5
4.
Proliferation Options.............................................................................................................5
6.
68-pin PLCC Pin Assignment...............................................................................................8
7.
64-pin SDIP Pin Assignment ................................................................................................9
8.
68-pin PLCC Signal Assignments Arranged by Functional Category ................................10
9.
64-pin SDIP Signal Assignments Arranged by Functional Category..................................11
10.
Signal Description ..............................................................................................................12
11.
Memory Signal Selections (RD1:0) ...................................................................................15
12.
8x930Hx Address Map .......................................................................................................16
13.
8x930Hx Operating Frequency ..........................................................................................17
14.
DC Characteristics at Operating Conditions.......................................................................18
15.
AC Timing Symbol Definitions............................................................................................20
16.
AC Characteristics at Operating Conditions.......................................................................21
17.
Real-time Wait State AC Timing Specifications .................................................................27
18.
Serial Port Timing -- Synchronous Mode 0 .......................................................................30
19.
External Clock Drive...........................................................................................................31
20.
Thermal Characteristics ..................................................................................................... 32
ADVANCE INFORMATION
1
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
1.0
ABOUT THIS DOCUMENT
This data sheet contains advance information about
Intel's 8
x
930H
x
Universal Serial Bus hub peripheral
controller, based on the MCS 251 peripheral
controller, which includes a functional overview,
mechanical data, targeted electrical specifications
(simulated), and bus functional waveforms. A
detailed functional description, other than
parametric performance, is published in the
8x930Ax, 8x930Hx Universal Serial Bus Micorcon-
troller User's Manual
(272949).
1.1
Additional Information Sources
Intel documentation is available from your local Intel
Sales Representative or Intel Literature Sales.
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
1-800-879-4683
1.2
Electronic Information
We offer a variety of technical and product infor-
mation through the World Wide Web (see Table 2
for URL) and through FaxBack service which is an
on-demand publishing system that sends
documents to your fax machine. You can get
product announcements, change notifications,
product literature, device characteristics, design
recommendations, and quality and reliability infor-
mation 24 hours a day, 7 days a week. Just dial the
telephone number and respond to the system
prompts.
Table 1. Related Documentation
Table 2. Electronic Information
Document Title
Order/Contact
8x930Ax, 8x930Hx Universal Serial Bus Micorcontroller
User's Manual
Intel Order # 272949
Universal Serial Bus Specification
Intel Order # 272962
Document Title
Order/Contact
Intel's World-Wide Web (WWW) Location:
http://www.intel.com/design/usb/
Customer Support (US and Canada):
800-628-8686
FaxBack Service:
US and Canada
800-628-2283
Europe
+44(0)793-496646
worldwide
916-356-3105
Application Bulletin Board Service:
up to 14.4-Kbaud line, worldwide
916-356-3600
dedicated 2400-baud line, worldwide
916-356-7209
Europe
+44(0)793-496340
2
ADVANCE INFORMATION
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
1.3
Product Summary
Figure 1. 8
x
930H
x
Block Diagram
A4340-01
SRC2 (8)
Code Address (24)
Code Bus (16)
RAM
ROM
Watchdog
Timer
Timer/
Counters
PCA
Serial I/O
Port 2
Drivers
P2.7:0
Port 0
Drivers
P0.7:0
Port 3
Drivers
P3.7:0
Port 1
Drivers
P1.7:0
Data Address (24)
Data Bus (8)
Memory Address (16)
System Bus and I/O Ports
I/O Ports and
Peripheral Signals
SRC1 (8)
IB Bus (8)
Peripheral
Interface
Interrupt
Handler
Clock
&
Reset
Bus Interface
Instruction Sequencer
DST (16)
ALU
Data
Memory
Interface
Memory Data (16)
Register
File
USB
USB Ports
Microcontroller Core
For details, see the USB module block diagram.
ADVANCE INFORMATION
3
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Figure 2. 8
x
930H
x
USB Module Block Diagram
D
P3
D
M3
Transceiver
A5102-02
D
P5
D
M5
D
P2
D
M2
D
P1
D
M0
D
P0
D
M1
Repeater
USB Upstream Port
USB
Downstream
Ports
Serial Bus Interface Engine
(SIE)
Transceiver
Transceiver
Transceiver
Hub
Interface
Unit
(HIU)
Function
Interface
Unit
(FIU)
Control
Control
FIFOs
Data Bus
To
CPU
Transmit/Receive Bus
Transceiver
HF/HG only
4
ADVANCE INFORMATION
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
2.0
NOMENCLATURE OVERVIEW
Figure 3. Product Nomenclature
Table 3. Description of Product Nomenclature
Parameter
Options
Description
Temperature and Burn-in
no mark
Commercial operating temperature range (0
o
C to 70
o
C) with
Intel standard burn-in
Packaging Options
N
Plastic Leaded Chip Carrier (PLCC)
U
Shrink Dual In-Line Package (SDIP)
Program Memory Options
0
Without ROM
3
With ROM
Process and Voltage Information
no mark
CHMOS
Product Family
930Hx
Advanced 8-bit microcontroller architecture with on-chip
Universal Serial Bus Hub and Function capability. Indicates
ROM size, RAM size, and quantity of external downstream
ports (see Table 4).
Device Speed
no mark
12 MHz crystal
Program Memory Options
XXXXX
XX
X
X
8
XX
X
Packaging Options
Temperature and Burn-in Options
A2815-01
Process Information
Product Family Device Speed
ADVANCE INFORMATION
5
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Table 5. Downstream Port Allocation
Table 4. Proliferation Options
4 External
Downstream Ports
(HF/HG)
3 External
Downstream Ports
(HD/HE)
ROM Size
RAM Size
Package
N80930HF
N80930HD
0
1024 bytes
68-pin PLCC
N83930HF
N83930HD
8 Kbytes
1024 bytes
68-pin PLCC
N83930HG
N83930HE
16 Kbytes
1024 bytes
68-pin PLCC
U80930HF
U80930HD
0
1024 bytes
64-pin SDIP
U83930HF
U83930HD
8 Kbytes
1024 bytes
64-pin SDIP
U83930HG
U83930HE
16 Kbytes
1024 bytes
64-pin SDIP
Downstream Port
Number
8
x
930HD/HE
8
x
930HF/HG
1
External
External
2
External
External
3
External
External
4
Internal (Embedded Function)
Internal (Embedded Function)
5
--
External
6
ADVANCE INFORMATION
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
3.0
PINOUT
Figure 4 illustrates a diagram of the 8
x
930HD/HE PLCC package. Table 6 and Table 8 contain indexes of the
pin arrangement. Table 10 contains the signal descriptions for all pins.
.
Figure 4. 8
x
930HD/HE and 8
x
930HF/HG 68-pin PLCC Package
UPWEN#
/D
P5
OVRI#
/D
M5
D
P1
D
M1
Reserved
D
P0
D
M0
ECAP
V
SSP
V
CCP
SOF#
D
P3
D
M3
Reserved
D
P2
D
M2
PLLSEL0
A8 / P2.0
A9 / P2.1
A10 / P2.2
A11 / P2.3
A12 / P2.4
A13 / P2.5
A14 / P2.6
A15 / P2.7
V
SS
V
CC
EA#
ALE
PSEN#
Reserved
Reserved
Reserved
/UPWEN#
Reserved
/OVRI#
A4421-01
AD7 / P0.7
AD6 / P0.6
AD5 / P0.5
AD4 / P0.4
AD3 / P0.3
AD2 / P0.2
AD1 / P0.1
AD0 / P0.0
V
SSP
V
CCP
P3.0 / RXD
P3.1 / TXD
P3.2 / INT0#
P3.3 / INT1#
P3.4 / T0
P3.5 / T1
P3.6 / WR#
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
View of component as
mounted on PC board
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
P3.7 / RD# / A16
P1.0 / T2
P1.1 / T2EX
P1.2 / ECI
P1.3 / CEX0
P1.4 / CEX1
P1.5 / CEX2
P1.6 / CEX3 / WAIT#
P1.7 / CEX4 / A17 / WCLK
V
CC
V
SS
XTAL1
XTAL2
AV
CC
RST
PLLSEL1
PLLSEL2
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
NOTE:
Reserved pins must be left unconnected.
Specific to the 8x930HD/HE
Specific to the 8x930HF/HG
ADVANCE INFORMATION
7
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Figure 5. 8
x
930HD/HE and 8
x
930HF/HG 64-pin SDIP Package
RESERVED
/D
M5
AV
CC
AD2 / P0.2
P3.3 / INT1#
P3.2 / INT0#
AD3 / P0.3
AD1 / P0.1
P3.1 / TXD
AD0 / P0.0
P3.0 / RXD
ECAP
V
SSP
SOF#
V
CCP
DM0
PLLSEL0
DP0
PLLSEL2
DMI
PLLSEL1
DP1
RST
RESERVED
/D
P5
XTAL2
OVRI#
XTAL1
UPWEN#
V
SS
PSEN#
V
CC
ALE
P1.7 / CEX4 / A17 / WCLK
EA#
P1.6 / CEX3 / WAIT#
V
CC
P1.5 / CEX2
V
SS
P1.4 / CEX1
A15 / P2.7
P1.3 / CEX0
A14 / P2.6
P1.2 / ECI
A13 / P2.5
P1.1 / T2EX
A12 / P2.4
P1.0 / T2
A11 / P2.3
P3.7 / A16 / RD#
A10 / P2.2
P3.6 / WR#
A9 / P2.1
P3.5 / T1
A8 / P2.0
P3.4 / T0
AD7 / P0.7
V
CCP
AD6 / P0.6
DP3
AD5 / P0.5
V
SSP
AD4 / P0.4
DM3
DP2
DM2
59
60
58
57
63
64
62
61
51
52
50
49
55
56
54
53
43
44
42
41
47
48
46
45
35
36
34
33
39
40
38
37
6
5
7
8
2
1
8X930HX
A4422-01
3
4
14
15
16
10
9
11
12
22
21
23
24
18
17
19
20
30
29
31
32
26
25
27
28
NOTE:
Reserved pins must be left unconnected.
56
View of
component
as mounted
on PC board
13
Specific to the 8x930HD/HE
Specific to the 8x930HF/HG
8
ADVANCE INFORMATION
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Table 6. 68-pin PLCC Pin Assignment
Pin
Name
Pin
Name
Pin
Name
1
V
SS
24
P3.4/T0
47
Reserved
2
A15/P2.7
25
P3.5/T1
48
D
M
3
3
A14/P2.6
26
P3.6/WR#
49
D
P
3
4
A13/P2.5
27
P3.7/RD#/A16
50
SOF#
5
A12/P2.4
28
P1.0/T2
51
V
CCP
6
A11/P2.3
29
P1.1/T2EX
52
V
SSP
7
A10/P2.2
30
P1.2/ECI
53
ECAP
8
A9/P2.1
31
P1.3/CEX0
54
D
M
0
9
A8/P2.0
32
P1.4/CEX1
55
D
P
0
10
AD7/P0.7
33
P1.5/CEX2
56
Reserved
11
AD6/P0.6
34
P1.6/CEX3/WAIT#
57
D
M
1
12
AD5/P0.5
35
P1.7/CEX4/A17/WCLK
58
D
P
1
13
AD4/P0.4
36
V
CC
59
OVRI#
/D
M5
14
AD3/P0.3
37
V
SS
60
UPWEN#
/D
P5
15
AD2/P0.2
38
XTAL1
61
Reserved
/OVRI#
16
AD1/P0.1
39
XTAL2
62
Reserved
/UPWEN#
17
AD0/P0.0
40
AV
CC
63
Reserved
18
V
SSP
41
RST
64
Reserved
19
V
CCP
42
PLLSEL1
65
PSEN#
20
P3.0/RXD
43
PLLSEL2
66
ALE
21
P3.1/TXD
44
PLLSEL0
67
EA#
22
P3.2/INT0#
45
D
M
2
68
V
CC
23
P3.3/INT1#
46
D
P
2
Specific to the 8
x
930HD/HE
Specific to the 8
x
930HF/HG
ADVANCE INFORMATION
9
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Table 7. 64-pin SDIP Pin Assignment
Pin
Name
Pin
Name
Pin
Name
1
V
CCP
23
RST
45
EA#
2
P3.0/RXD
24
PLLSEL1
46
V
CC
3
P3.1/TXD
25
PLLSEL2
47
V
SS
4
P3.2/INT0#
26
PLLSEL0
48
A15/P2.7
5
P3.3/ INT1#
27
DM2
49
A14/P2.6
6
P3.4/T0
28
DP2
50
A13/P2.5
7
P3.5/T1
29
DM3
51
A12/P2.4
8
P3.6/WR#
30
DP3
52
A11/P2.3
9
P3.7/A16/RD#
31
SOF#
53
A10/P2.2
10
P1.0/T2
32
V
CCP
54
A9/P2.1
11
P1.1/T2EX
33
V
SSP
55
A8/P2.0
12
P1.2/ECI
34
ECAP
56
AD7/P0.7
13
P1.3/CEX0
35
DM0
57
AD6/P0.6
14
P1.4/CEX1
36
DP0
58
AD5/P0.5
15
P1.5/CEX2
37
DM1
59
AD4/P0.4
16
P1.6/CEX3/WAIT#
38
DP1
60
AD3/P0.3
17
P1.7/CEX4/A17/WCLK
39
Reserved
/D
M5
61
AD2/P0.2
18
V
CC
40
Reserved
/D
P5
62
AD1/P0.1
19
V
SS
41
OVRI#
63
AD0/P0.0
20
XTAL1
42
UPWEN#
64
V
SSP
21
XTAL2
43
PSEN#
22
AVCC
44
ALE
Specific to the 8
x
930HD/HE
Specific to the 8
x
930HF/HG
10
ADVANCE INFORMATION
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Table 8. 68-pin PLCC Signal Assignments Arranged by Functional Category
Address & Data
Input/Output
USB
Name
Pin
Name
Pin
Name
Pin
AD0/P0.0
17
P1.0/T2
28
PLLSEL0
44
AD1/P0.1
16
P1.1/T2EX
29
PLLSEL1
42
AD2/P0.2
15
P1.2/ECI
30
PLLSEL2
43
AD3/P0.3
14
P1.3/CEX0
31
D
M
0
54
AD4/P0.4
13
P1.4/CEX1
32
D
P
0
55
AD5/P0.5
12
P1.5/CEX2
33
D
M
1
57
AD6/P0.6
11
P1.6/CEX3/WAIT#
34
D
P
1
58
AD7/P0.7
10
P1.7/CEX4/A17/WCLK
35
D
M
2
45
A8/P2.0
9
P3.0/RXD
20
D
P
2
46
A9/P2.1
8
P3.1/TXD
21
D
M
3
48
A10/P2.2
7
P3.2/INT0#
22
D
P
3
49
A11/P2.3
6
P3.3/INT1#
23
SOF#
50
A12/P2.4
5
P3.4/T0
24
ECAP
53
A13/P2.5
4
P3.5/T1
25
OVRI#
59
/
61
A14/P2.6
3
P3.6/WR#
26
UPWEN#
60
/
62
A15/P2.7
2
P3.7/RD#/A16
27
D
M5
59
P3.7/RD#/A16
27
D
P5
60
P1.7/CEX4/A17/WCLK
35
Processor Control
Power & Ground
Bus Control & Status
Name
Pin
Name
Pin
Name
Pin
P3.2/INT0#
22
V
CC
36, 68
P3.6/WR#
26
P3.3/INT1#
23
V
CCP
19, 51
P3.7/RD#/A16
27
RST
41
AV
CC
40
PSEN#
65
XTAL1
38
V
SS
1, 37
ALE
66
XTAL2
39
V
SSP
18, 52
EA#
67
Specific to the 8
x
930HD/HE
Specific to the 8
x
930HF/HG
ADVANCE INFORMATION
11
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Table 9. 64-pin SDIP Signal Assignments Arranged by Functional Category
Address & Data
Input/Output
USB
Name
Pin
Name
Pin
Name
Pin
AD0/P0.0
63
P1.0/T2
10
PLLSEL0
26
AD1/P0.1
62
P1.1/T2EX
11
PLLSEL1
24
AD2/P0.2
61
P1.2/ECI
12
PLLSEL2
25
AD3/P0.3
60
P1.3/CEX0
13
D
M
0
35
AD4/P0.4
59
P1.4/CEX1
14
D
P
0
36
AD5/P0.5
58
P1.5/CEX2
15
D
M
1
37
AD6/P0.6
57
P1.6/CEX3/WAIT#
16
D
P
1
38
AD7/P0.7
56
P1.7/CEX4/A17/WCLK
17
D
M
2
27
A8/P2.0
55
P3.0/RXD
2
D
P
2
28
A9/P2.1
54
P3.1/TXD
3
D
M
3
29
A10/P2.2
53
P3.2/INT0#
4
D
P
3
30
A11/P2.3
52
P3.3/INT1#
5
SOF#
31
A12/P2.4
51
P3.4/T0
6
ECAP
34
A13/P2.5
50
P3.5/T1
7
OVRI#
41
A14/P2.6
49
P3.6/WR#
8
UPWEN#
42
A15/P2.7
48
P3.7/A16/RD#
9
Reserved
/D
M5
39
P3.7/A16/RD#
9
Reserved
/D
P5
40
P1.7/CEX4/A17/WCLK
17
Processor Control
Power & Ground
Bus Control & Status
Name
Pin
Name
Pin
Name
Pin
P3.2/INT0#
4
V
CC
46
P3.6/WR#
8
P3.3/INT1#
5
V
CCP
32
P3.7/RD#/A16
9
RST
23
AV
CC
22
PSEN#
43
XTAL1
20
V
SS
47
ALE
44
XTAL2
21
V
SSP
64
EA#
45
Specific to the 8
x
930HD/HE
Specific to the 8
x
930HF/HG
12
ADVANCE INFORMATION
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
4.0
SIGNALS
Table 10. Signal Description (Sheet 1 of 4)
Signal
Name
Type
Description
Alternate
Function
A17
O
Address Line 17. Output to memory as 18th external address
bit in extended bus applications. Selected with bits RD1:0 in
configuration byte UCONFIG0. See Table 11 and RD#, WR#,
and PSEN#.
P1.7/CEX4/WCLK
A16
O
Address Line 16. Output to memory as 17th external address
bit in extended bus applications. Selected with bits RD1:0 in
configuration byte UCONFIG0. See Table 11 and RD#, WR#,
and PSEN#.
RD#
A15:8
O
Address Lines. Upper address lines for external memory.
Description is for nonpage mode configuration. For page mode
configuration, data (D7:0) is multiplexed with the upper address
byte (A15:8).
P2.7:0
AD7:0
I/O
Address/Data Lines. Multiplexed lower address lines and data
lines for external memory. Description is for nonpage mode
configuration. For page mode configuration, data (D7:0) is
multiplexed with the upper address byte (A15:8).
P0.7:0
ALE
O
Address Latch Enable. ALE signals the start of an external
bus cycle and indicates that valid address information is
available on lines A15:8 and AD7:0. An external latch can use
ALE to demultiplex the address from the address/data bus.
--
AV
CC
PWR
Analog V
CC
. A separate V
CC
input for the phase-locked loop
circuitry.
--
CEX2:0
CEX3
CEX4
I/O
Programmable Counter Array (PCA) Input/Output Pins.
These are input signals for the PCA capture mode and output
signals for the PCA compare mode and PCA PWM mode.
P1.5:3
P1.6/WAIT#
P1.7/A17/WCLK
D
M
0
, D
P
0
I/O
USB Port 0. D
P
0
and D
M
0
are the data plus and data minus
lines of USB port 0, the upstream differential port. These lines
do not have internal pullup resistors. Provide an external 1.5
K
pullup resistor at D
P
0
to indicate the connection of a
fullspeed device.
NOTE:
D
P
0
low and D
M
0
low signals an SE0 (USB reset),
causing the 8
x
930H
x
to stay in reset.
--
D
M
1
, D
P
1
D
M
2
, D
P
2
D
M
3
, D
P
3
D
M
5
, D
P
5
I/O
USB Ports 1, 2, 3, and 5. D
P
1
, D
P
2
, D
P
3
, D
M
1
, D
M
2
, D
M
3
, D
M
5,
and D
P
5
are the data plus and data minus lines of USB ports 1,
2, 3, and 5, the four downstream differential ports. These lines
have no internal pulldown resistors. Provide an external 15 K
pulldown resistor at each of these pins. (See "Unused
Downstream Ports" on page 33.)
--
ADVANCE INFORMATION
13
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
EA#
I
External Access. Directs program memory accesses to on-
chip or off-chip code memory. When EA# is connected to
ground, all program memory accesses are off-chip. When EA#
is connected to V
CC
, program accesses on-chip ROM if the
address is within the range of the on-chip ROM; otherwise, the
access is off-chip. The value of EA# is latched at reset. For
devices without on-chip ROM, EA# must be connected to
ground.
--
ECAP
I
External Capacitor. Connect a 1 F or larger capacitor
between this pin and V
SS
to ensure proper operation of the
differential line drivers.
--
ECI
I
PCA External Clock Input. External clock input to the 16-bit
PCA timer.
P1.2
INT1:0#
I
External Interrupts 0 and 1. These inputs set the IE1:0
interrupt flags in the TCON register. Bits IT1:0 in TCON select
the triggering method: edge-triggered (high-to-low) or level
triggered (active low). INT1:0 also serves as external run
control for timer1:0 when selected by GATE1:0# in TCON.
P3.3:2
OVRI#
I
Overcurrent Sense. Senses input to indicate an overcurrent
condition for a bus-powered USB device on an external
downstream port. Active low.
--
P0.7:0
I/O
Port 0. This is an 8-bit, open-drain, bidirectional I/O port.
AD7:0
P1.0
P1.1
P1.2
P1.5:3
P1.6
P1.7
I/O
Port 1. This is an 8-bit, bidirectional I/O port with internal pull-
ups.
T2
T2EX
ECI
CEX2:0
CEX3/WAIT#
CEX4/A17/WCLK
P2.7:0
I/O
Port 2. An 8-bit, bidirectional I/O port with internal pull-ups.
A15:8
P3.0
P3.1
P3.3:2
P3.5:4
P3.6
P3.7
I/O
Port 3. An 8-bit, bidirectional I/O port with internal pull-ups.
RXD
TXD
INT1:0#
T1:0
WR#
RD#/A16
PLLSEL2:0
I
Phase-locked Loop Select. Three-bit code selects USB data
rate (see Table 13 on page 17).
--
PSEN#
O
Program Store Enable. Read signal output. Asserted for the
memory address range determined by bits RD1:0 in configu-
ration byte UCONFIG0 (see RD# and Table 11).
--
RD#
O
Read. Read signal output to external data memory. Asserted
only for RD1:0 = 11. See configuration byte UCONFIG0. (Also
see PSEN# and Table 11).
P3.7/A16
Table 10. Signal Description (Sheet 2 of 4)
Signal
Name
Type
Description
Alternate
Function
14
ADVANCE INFORMATION
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
RST
I
Reset. Reset input to the chip. Holding this pin high for 64
oscillator periods while the oscillator is running resets the
device. The port pins are driven to their reset conditions when a
voltage greater than V
IH1
is applied, whether or not the
oscillator is running. This pin has an internal pulldown resistor;
connecting a capacitor between this pin and Vcc implements
power-on reset.
Asserting RST when the chip is in idle mode or powerdown
mode returns the chip to normal operation.
--
RXD
I/O
Receive Serial Data. RXD sends and receives data in serial
I/O mode 0 and receives data in serial I/O modes 1, 2, and 3.
P3.0
SOF#
O
Start of Frame. Start of frame pulse. Active low. Asserted for 8
states (see Table 13) when frame timer is locked to USB frame
timing and when SOF token or artificial SOF is detected.
--
T1:0
I
Timer 1:0 External Clock Input. When timer 1:0 operates as a
counter, a falling edge on the T1:0 pin increments the count.
P3.5:4
T2
I/O
Timer 2 Clock Input/Output. For the timer 2 capture mode,
this signal is the external clock input. For the clock-out mode, it
is the timer 2 clock output.
P1.0
T2EX
I
Timer 2 External Input. In timer 2 capture mode, a falling edge
initiates a capture of the timer 2 registers. In auto-reload mode,
a falling edge causes the timer 2 registers to be reloaded. In the
up-down counter mode, this signal determines the count
direction: 1 = up, 0 = down.
P1.1
TXD
O
Transmit Serial Data. TXD outputs the shift clock in serial I/O
mode 0 and transmits serial data in serial I/O modes 1, 2, and
3.
P3.1
UPWEN#
O
USB Power Enable. A low signal on this pin applies power to
all three external downstream ports.
--
V
CC
PWR
Supply Voltage. Connect this pin to the +5V supply voltage.
--
V
CCP
PWR
Supply Voltage for I/O Buffers. Connect this pin to the +5V
supply voltage.
--
V
SS
GND
Circuit Ground. Connect this pin to ground.
--
V
SSP
GND
Circuit Ground for I/O Buffers. Connect this pin to ground.
--
WAIT#
I
Real-time Wait State Input. The real-time WAIT# input is
enabled by writing a logical `1' to the WCON.0 (RTWE) bit at
S:A7H. During bus cycles, the external memory system can
signal `system ready' to the microcontroller in real time by
controlling the WAIT# input signal on the port 1.6 input.
P1.6/CEX3
WCLK
O
Wait Clock Output. The real-time WCLK output is driven at
port 1.7 (WCLK) by writing a logical `1' to the WCON.1
(RTWCE) bit at S:A7H. When enabled, the WCLK output
produces a square wave signal with a period of TCLK.
P1.7/CEX4/A17
Table 10. Signal Description (Sheet 3 of 4)
Signal
Name
Type
Description
Alternate
Function
ADVANCE INFORMATION
15
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
RD1:0 are bits 3:2 of configuration byte UCONFIG0. Refer to Figure 4-3 on page 4-5 in the
8x930Ax,
8x930Hx Universal Serial Bus Micorcontroller User's Manual
.
WR#
O
Write. Write signal output to external memory (See Table 11).
P3.6
XTAL1
I
Oscillator Amplifier Input. When implementing the on-chip
oscillator, connect the external crystal/resonator across XTAL1
and XTAL2. If an external clock source is used, then connect it
to this pin.
--
XTAL2
O
Oscillator Amplifier Output. When implementing the on-chip
oscillator, connect the external crystal/resonator across XTAL1
and XTAL2. If an external oscillator is used, then leave XTAL2
unconnected.
--
Table 11. Memory Signal Selections (RD1:0)
RD1:0
A17/P1.7/
CEX4/WCLK
A16/P3.7/RD#
PSEN#
WR#
Features
0 0
A17
A16
Asserted for
all addresses
Asserted for writes to
all memory locations
256-Kbyte external
address space
0 1
P1.7/CEX4/WCLK
A16
Asserted for
all addresses
Asserted for writes to
all memory locations
128-Kbyte external
address space
1 0
P1.7/CEX4/WCLK
P3.7 only
Asserted for
all addresses
Asserted for writes to
all memory locations
64-Kbyte external
address space
One additional port
pin
1 1
P1.7/CEX4/WCLK
RD# asserted
for addresses
7F:FFFFH
Asserted for
addresses
80:0000H
Asserted only for
writes to MCS 51
microcontroller data
memory locations.
Compatible with MCS
51 microcontrollers.
Separate 64-Kbyte
external program
and data memories.
Table 10. Signal Description (Sheet 4 of 4)
Signal
Name
Type
Description
Alternate
Function
16
ADVANCE INFORMATION
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
5.0
ADDRESS MAP
Table 12. 8
x
930H
x
Address Map
Internal
Address)
Description
Notes
FF:FFFFH
FF:4000H
External Memory except the top eight bytes (FF:FFF8H FF:FFFFH) which are
reserved for the configuration array.
1, 2, 3
FF:FFFFH
FF:0000H
External memory or on-chip nonvolatile memory (8 Kbytes FF:0000H
FF:1FFFH, 16 Kbytes FF:0000H FF:3FFFH).
2, 4, 5
FE:FFFFH
FE:0000H
External Memory
2
FD:FFFFH
02:0000H
Reserved Addresses
6
01:FFFFH
01:0000H
External Memory
2
00:FFFFH
00:0420H
External Memory
4
00:041FH
00:0080H
On-chip RAM
4
00:007FH
00:0020H
On-chip RAM
7
00:001FH
00:0000H
Storage for R0R7 of Register File
8, 9
NOTES:
1.
18 address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration).
2.
Data in this area is accessible by indirect addressing only.
3.
Eight addresses at the top of all external memory maps are reserved for current and future device
Configuration Byte information.
4.
Data is accessible by direct and indirect addressing.
5.
Devices reset into internal or external starting locations depending on the state of EA# and configura-
tion byte information. See EA# signal description in Table 5. See also UCONFIG1:0 bit definitions in
the
8x930Ax, 8x930Hx Universal Serial Bus Micorcontroller User's Manual.
6.
This reserved area returns unspecified values. Software can execute a write to the reserved area, but
nothing is actually written.
7.
Data is accessible by direct, indirect, and bit addressing.
8.
The special function registers (SFRs) and the register file have separate internal address spaces.
9.
Data is accessible by direct, indirect, and register addressing.
ADVANCE INFORMATION
17
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
6.0
ELECTRICAL CHARACTERISTICS
6.1
Operating Frequencies
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature Under Bias................... 40C to +85C
Storage Temperature .................................. 65C to +150C
Voltage on Any Pins to V
SS
.............................0.5 V to +6.5 V
I
OL
per I/O Pin ................................................................. 15 mA
Power Dissipation (1) ..................................................... 1.5 W
OPERATING CONDITIONS
T
A
(Ambient Temperature Under Bias):
Commercial ........................................................ -0C to +70C
V
CC
/ V
CCP
(Digital Supply Voltage) ................ 4.40 V to 5.25 V
V
SS
/ V
SSP
............................................................................ 0 V
AV
CC
(Analog Supply Voltage) ...................... 4.40 V to 5.25 V
F
OSC
............................................................................. 12 MHz
NOTE:
Maximum power dissipation is based on
package heat-transfer limitations, not device
power consumption.
NOTICE: This document contains information on
products in the sampling and initial production
phases of development. The specifications are
subject to change without notice. Verify with your
local Intel sales office that you have the latest
datasheet before finalizing a design.
WARNING: Stressing the device beyond the
"Absolute Maximum Ratings" may cause
permanent damage. These are stress ratings only.
Operation beyond the "Operating Conditions" is not
recommended and extended exposure beyond the
"Operating Conditions" may affect device
reliability.
Table 13. 8
x
930H
x
Operating Frequency
PLLSEL2:0
Pin 43, 42, 44
(1)
XTAL1
Frequency
(F
OSC
)
USB Rate
(2)
Internal
Frequency
for CPU
and
Peripherals
(1/T
CLK
)
(3)
XTAL1
Clocks
per
State
(T
OSC
/state)
(5)
Comments
110
12 MHz
12 Mbps
(Full Speed)
12 MHz
(4)
1 PLL
On
NOTES:
1.
Other PLLSEL
x
combinations are not valid.
2.
The sampling rate is four times the USB rate.
3.
The AC timing specification (Table 16) defines the following symbol: CPU frequency
= F
CLK
= 1/T
CLK
.
4.
The 8
x
930H
x
CPU and peripheral frequency is 3 MHz (low clock mode) until the LC
bit in PCON is cleared by user firmware.
5.
When the CPU is operating in low clock mode (3 MHz), 1 state equals 4 T
osc.
18
ADVANCE INFORMATION
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
6.2
DC Characteristics
Table 14. DC Characteristics at Operating Conditions (Sheet 1 of 2)
Symbol
Parameter
Min
Typical
(1)
Max
Units
Test Conditions
V
IL
Input Low Voltage
(except EA#)
0.5
0.2 V
CC
0.1
V
V
IL
1
Input Low Voltage
(EA#)
0
0.2 V
CC
0.3
V
V
IH
Input High Voltage
(except XTAL1, RST)
0.2 V
CC
+ 0.9
V
CC
+ 0.5
V
V
IH
1
Input High Voltage
(XTAL1, RST)
0.7 V
CC
V
CC
+ 0.5
V
V
OL
Output Low Voltage
(port 1, 2, 3)
0.3
0.45
1.0
V
I
OL
= 100 A
(2) (3)
I
OL
= 1.6 mA
I
OL
= 3.5 mA
V
OL
1
Output Low Voltage
(port 0, ALE, PSEN#,
SOF#)
0.3
0.45
1.0
V
I
OL
= 200 A
(2) (3)
I
OL
= 3.2 mA
I
OL
= 7.0 mA
V
OH
Output High Voltage
(port 1, 2, 3, ALE,
PSEN#, SOF#)
V
CC
0.3
V
CC
0.7
V
CC
1.5
V
I
OH
= 10 A
(4)
I
OH
= 30 A
I
OH
= 60 A
V
OH
1
Output High Voltage
(port 0 in external
address space)
V
CC
0.3
V
CC
0.7
V
CC
1.5
V
I
OH
= 200 A
(4)
I
OH
= 3.2 mA
I
OH
= 7.0 mA
I
IL
Logical 0 Input
Current
(port 1,2,3)
150
A
V
IN
= 0.45 V
I
LI
Input Leakage Current
(port 0)
10
A
0.45 < V
IN
< V
CC
I
TL
Logical 1-to-0
Transition Current
(Port 1, 2,3)
-650
A
V
IN
= 2.0 V
R
RST
RST Pulldown
Resistor
40
225
K
C
IO
10
pF
F
OSC
= 12 MHz
T
A
= 25C
I
PD
Powerdown Current
Normal powerdown
USB suspend
25
145
75
175
A
ADVANCE INFORMATION
19
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
I
DL
Idle Mode I
CC
60
mA
Full
speed
(in low clock mode)
PLLSEL2:0 = 110
F
CLK
= 3 MHz
110
Full speed
(not in low clock
mode)
PLLSEL2:0 = 110
F
CLK
= 12 MHz
I
CC
Active Current
75
mA
Full speed
(in low clock mode)
PLLSEL2:0 = 110
F
CLK
= 3 MHz
170
Full speed
(not in low clock
mode)
PLLSEL2:0 = 110
F
CLK
= 12 MHz
NOTE:
1.
Typical values are obtained using V
CC
= 5.0V, T
A
= 25C and are not guaranteed.
2.
Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OH
per port pin:10 mA
Maximum I
OL
per 8-bit port:
Port 0: 26 mA
Ports 1-3: 15 mA
Maximum Total I
OL
for all output pins: 71 mA
If I
OL
exceeds the test conditions, then V
OL
may exceed the related specification. Pins are not guaran-
teed to sink current greater than the listed test conditions.
3.
Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into
the port 0 and port 2 pins when these pins change from 1 to 0. In applications where capacitive load-
ing exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qual-
ify ALE or other signals with a Schmitt trigger or CMOS-level input logic.
4.
Capacitive loading on ports 0 and 2 causes the V
OH
on ALE and PSEN to drop below the V
CC
specifi-
cation when the address lines are stabilizing.
Table 14. DC Characteristics at Operating Conditions (Sheet 2 of 2)
Symbol
Parameter
Min
Typical
(1)
Max
Units
Test Conditions
20
ADVANCE INFORMATION
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
6.3
Explanation of Timing Symbols
Table 15 defines the timing symbols used in Tables 11 through 14 and the associated timing diagrams. They
have the form T
XXYY
, where the character pairs represent a signal and its condition. Timing symbols represent
the time between two signal / condition points.
Table 15. AC Timing Symbol Definitions
Character
Signal(s)
A
Address: A17, A16, A15:8, A7:0
C
Wait Clock (WCLK), External Clock (XTAL1)
D
Data In: D7:0, RXD
L
ALE
Q
Data Out: D7:0, RXD
R
Read: RD#/PSEN#
W
Write: WR#
X
TXD
Y
WAIT#
Character
Condition
H
High
L
Low
V
Valid, Setup
X
No Longer Valid, Hold
Z
Floating (low impedance)
ADVANCE INFORMATION
21
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
6.4
System Bus AC Characteristics
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall times = 10 ns, F
OSC
= 12 MHz.
Table 16. AC Characteristics at Operating Conditions (Sheet 1 of 2)
Symbol
Parameter
CPU
Frequency
@ 12 MHz
(M, N = 0)
CPU Frequency (F
CLK
) Variable
Units
Min
Max
T
CLK
1/(CPU Frequency)
83.33
(Typical)
ns
(1) (2)
T
LHLL
ALE Pulse Width
34.66
(0.5+M)T
CLK
7
ns
(4)
T
AVLL
Address Valid to ALE Low
21.66
(0.5+M)T
CLK
20
ns
(4)
T
LLAX
Address Hold after ALE Low
4
4
ns
T
RLRH
(3)
RD# or PSEN# Pulse Width
73.33
(1+N)T
CLK
10
ns
(5)
T
WLWH
WR# Pulse Width
71.33
(1+N)T
CLK
12
ns
(5)
T
LLRL
(3)
ALE Low to RD# or PSEN#
Low
5
5
ns
T
LHAX
ALE High to Address Hold
40.33
(1+M)T
CLK
43
ns
(4)
T
RLDV
(3)
RD# or PSEN# Low to Valid
Data/Instruction In
50.33
(1+N)T
CLK
33
ns
(5)
T
RHDX
(3)
Data/Instruct. Hold After RD#
or PSEN# High
0
0
ns
T
RLAZ
(3)
RD# or PSEN# Low to
Address Float
0
0
ns
T
RHDZ
1
(3)
Instruct. Float After PSEN#
High
10
10
ns
T
RHDZ
2
(3)
Data Float After RD# or
PSEN# High
83.33
T
CLK
ns
T
RHLH
1
(3)
PSEN# High to ALE High
(instruction)
10
10
ns
T
RHLH
2
(3)
RD# or PSEN# High to ALE
High (data)
83.33
T
CLK
ns
T
WHLH
WR# High to ALE High
88.33
T
CLK
+ 5
ns
T
AVDV
1
Address (Port 0) Valid to Valid
Data/Instruction In
98.66
(2+M+N)T
CLK
68
ns
(4) (5)
NOTES:
1.
Refer to Table 13 for CPU frequencies versus XTAL1 frequencies.
2.
XTAL1 frequency is
0.25% for full speed and
1.5% for low speed.
3.
Specifications for PSEN# are identical to those for RD#.
4.
M = 0,1 is the extended ALE state.
5.
N = 0,1,2,3 is the RD#/PSEN#/WR# wait state.
22
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x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
T
AVDV
2
Address (Port 2) Valid to Valid
Data/Instruction In
118.66
(2+M+N)T
CLK
48
ns
(4) (5)
T
AVDV
3
Address (Port 2) Valid to Valid
Instruction In
23.33
(1+N)T
CLK
60
ns
(5)
T
AVRL
(3)
Address Valid to RD# or
PSEN# Low
37.33
(1+M)T
CLK
46
ns
(4)
T
AVWL
1
Address (Port 0) Valid to WR#
Low
37.33
(1+M)T
CLK
46
ns
(4)
T
AVWL
2
Address (Port 2) Valid to WR#
Low
66.33
(1+M)T
CLK
17
ns
(4)
T
WHQX
Data Hold after WR# High
28.66
0.5 T
CLK
13
ns
T
QVWH
Data Valid to WR# High
68.33
(1+N)T
CLK
15
ns
(5)
T
WHAX
WR# High to Address Hold
70.33
T
CLK
13
ns
Table 16. AC Characteristics at Operating Conditions (Sheet 2 of 2)
Symbol
Parameter
CPU
Frequency
@ 12 MHz
(M, N = 0)
CPU Frequency (F
CLK
) Variable
Units
Min
Max
NOTES:
1.
Refer to Table 13 for CPU frequencies versus XTAL1 frequencies.
2.
XTAL1 frequency is
0.25% for full speed and
1.5% for low speed.
3.
Specifications for PSEN# are identical to those for RD#.
4.
M = 0,1 is the extended ALE state.
5.
N = 0,1,2,3 is the RD#/PSEN#/WR# wait state.
ADVANCE INFORMATION
23
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
6.4.1
SYSTEM BUS TIMING DIAGRAMS
Figure 6. 8
x
930H
x
Code Fetch, Nonpage Mode
ALE
RD#/PSEN#
P0
A17/A16/P2
A5011-01
State 1
State 1
(next cycle)
State 2
T
LHLL
T
LLRL
T
RLRH
T
RLAZ
T
LLAX
T
AVLL
T
AVDV1
T
AVDV2
T
LHAX
Instruction In
A7:0
A17/A16/A15:8
T
RHDX
T
RHDZ1
T
RHLH1
T
AVRL
T
RLDV
ALE
RD#/PSEN#
P0
A17/A16/P2
A5011-01
State 1
State 1
(next cycle)
State 2
T
LHLL
T
LLRL
T
RLRH
T
RLAZ
T
LLAX
T
AVLL
T
AVDV1
T
AVDV2
T
LHAX
Instruction In
A7:0
A17/A16/A15:8
T
RHDX
T
RHDZ1
T
RHLH1
T
AVRL
T
RLDV
24
ADVANCE INFORMATION
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x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Figure 7. 8
x
930H
x
Data Read, Nonpage Mode
Figure 8. 8
x
930H
x
Data Write, Nonpage Mode
ALE
RD#/PSEN#
P0
A17/A16/P2
A5025-02
State 1
State 3
State 2
T
LHLL
T
LLRL
T
RLRH
T
RLAZ
T
LLAX
T
RLDV
T
AVDV1
T
AVDV2
T
LHAX
D7:0
A7:0
A17/A16/A15:8
T
RHDX
T
RHDZ2
T
RHLH2
T
AVRL
T
AVLL
T
QVWH
ALE
WR#
P0
A17/A16/P2
A5026-02
State 1
State 3
State 2
T
LHLL
T
WLWH
T
LLAX
T
LHAX
D7:0
A7:0
A17/A16/A15:8
T
WHLH
T
AVWL2
T
AVLL
T
AVWL1
T
WHAX
T
WHQX
ADVANCE INFORMATION
25
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Figure 9. 8
x
930H
x
Code Fetch, Page Mode
ALE
RD#/PSEN#
P2
A17/A16/P0
A5028-02
State 1
State 2
T
LHLL
T
LLRL
T
RLRH
T
RLAZ
T
LLAX
T
AVLL
T
AVDV1
T
AVDV2
T
LHAX
Instruction 1 In
A15:8
A17/A16/A7:0
T
RHDZ1
T
RHLH1
T
AVRL
T
RLDV
T
RHDX
Instruction 2 In
T
AVDV3
Cycle 2, Page Hit
State 1
Cycle 1, Page Miss
During a sequence of page hits, PSEN# remains low until the end of the last page hit cycle.
26
ADVANCE INFORMATION
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x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Figure 10. 8
x
930H
x
Data Read, Page Mode
Figure 11. 8
x
930H
x
Data Write, Page Mode
ALE
RD#/PSEN#
P2
A17/A16/P0
A5029-02
State 1
State 3
State 2
T
LHLL
T
LLRL
T
RLRH
T
RLAZ
T
LLAX
T
RLDV
T
AVDV1
T
AVDV2
T
LHAX
D7:0
A15:8
A17/A16/A7:0
T
RHDX
T
RHDZ2
T
AVRL
T
AVLL
T
RHLH2
T
QVWH
ALE
WR#
P2
A17/A16/P0
A5030-02
State 1
State 3
State 2
T
LHLL
T
WLWH
T
LLAX
T
LHAX
D7:0
A15:8
A17/A16/A7:0
T
WHLH
T
AVWL2
T
AVLL
T
AVWL1
T
WHAX
T
WHQX
ADVANCE INFORMATION
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8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
6.4.2
REAL-TIME WAIT STATE FUNCTION AC CHARACTERISTICS
Table 17. Real-time Wait State AC Timing Specifications
Symbol
Parameter
F
CLK
Variable
(1) (2)
Units
Min
Typ
Max
T
CLYV
WCLK Low to WAIT# Setup
0
0.5 T
CLK
13
ns
T
CLYX
WAIT# Hold after WCLK Low
(W)T
CLK
+ 5
(0.5+W)T
CLK
13
ns
T
RLYV
( 2)
PSEN# or RD# Low to WAIT# Setup
0
0.5 T
CLK
13
ns
T
RLYX
WAIT# Hold after PSEN# or RD# Low
(W)T
CLK
+ 5
(0.5+W)T
CLK
13
ns
T
WLYV
WR# Low to WAIT# Setup
0
0.5 T
CLK
13
ns
T
WLYX
WAIT# Hold after WR# Low
(W)T
CLK
+ 5
(0.5+W)T
CLK
13
ns
NOTES:
1.
W is the number of real-time wait states (0, 1, 2, ... highest possible number).
2.
The real-time wait function has a critical timing for instruction reads. It is not advisable to use this fea-
ture for instruction reads during page mode.
28
ADVANCE INFORMATION
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x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
6.4.3
REAL-TIME WAIT STATE FUNCTION TIMING DIAGRAMS
Figure 12. External Code Fetch/Data Read (Nonpage Mode, Real-time Wait State)
Figure 13. External Data Write (Nonpage Mode, Real-time Wait State)
A7:0
WCLK
ALE
RD#/PSEN#
WAIT#
P0
P2
A15:8
A5000-02
State 1
State 2
State 3
State 1 (next cycle)
T
CLYX
min
T
CLYV
A7:0
D7:0
stretched
A15:8
stretched
RD#/PSEN# stretched
T
CLYX
max
T
RLYV
T
RLYX
max
T
RLYX
min
A7:0
WCLK
ALE
WR#
T
WLYV
WAIT#
P0
P2
A5002-02
State 1
State 2
State 3
State 4
T
CLYX
min
T
CLYV
D7:0
stretched
A15:8
stretched
WR# stretched
T
WLYX
max
T
WLYX
min
T
CLYX
max
ADVANCE INFORMATION
29
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Figure 14. External Data Read (Page Mode, Real-time Wait State)
Figure 15. External Data Write (Page Mode, Real-time Wait State)
A15:8
WCLK
ALE
RD#/PSEN#
WAIT#
P2
P0
A7:0
A5001-02
State 1
State 2
State 3
State 1 (next cycle)
T
CLYX
min
T
CLYV
A15:8
D7:0
stretched
A7:0
stretched
RD#/PSEN# stretched
T
CLYX
max
T
RLYV
T
RLYX
max
T
RLYX
min
A15:8
WCLK
ALE
WR#
T
WLYV
WAIT#
P2
P0
A5003-02
State 1
State 2
State 3
State 4
T
CLYX
min
T
CLYV
D7:0
stretched
A7:0
stretched
WR# stretched
T
WLYX
max
T
WLYX
min
T
CLYX
max
30
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x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
6.5
AC Characteristics -- Synchronous Mode 0
Figure 16. Serial Port Waveform -- Synchronous Mode 0
6.6
External Clock Drive
Figure 17. External Clock Drive Waveforms
Table 18. Serial Port Timing -- Synchronous Mode 0
Symbol
Parameter
Min
Max
Units
T
XLXL
Serial Port Clock Cycle Time
6 T
OSC
ns
T
QVXH
Output Data Setup to Clock Rising Edge
5 T
OSC
133
ns
T
XHQX
Output Data Hold after Clock Rising Edge
T
OSC
50
ns
T
XHDX
Input Data Hold after Clock Rising Edge
0
ns
T
XHDV
Clock Rising Edge to Input Data Valid
5 T
OSC
133
ns
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
RXD
(In)
RXD
(Out)
TXD
0
1
2
3
4
5
6
7
TQVXH
TXLXL
TXHDX
TXHQX
TXHDV
A2592-02
Set TI
Set RI
TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit.
0.7 V
CC
A4119-01
0.45 V
V
CC
0.5
0.2 V
CC
0.1
T
CHCL
T
CLCX
T
CLCL
T
CLCH
T
CHCX
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8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Table 19. External Clock Drive
6.7
Testing Waveforms
Figure 18. AC Testing Input, Output Waveforms
Figure 19. Float Waveforms
Symbol
Parameter
Min
Max
Units
1/T
OSC
Oscillator Frequency (F
OSC
)
6
12
MHz
T
CHCX
High Time
0.35 T
OSC
0.65 T
OSC
ns
T
CLCX
Low Time
0.35 T
OSC
0.65 T
OSC
ns
T
CLCH
Rise Time
10
ns
T
CHCL
Fall Time
10
ns
AC inputs during testing are driven at V
CC
0.5V for a logic 1
and 0.45 V for a logic 0. Timing measurements are made at
0.45 V
Inputs
Outputs
A4118-01
V
IH MIN
V
OL MAX
V
CC
0.5
0.2 V
CC
+ 0.9
0.2 V
CC
0.1
a min of V
IH
for a logic 1 and V
OL
for a logic 0.
V
LOAD
+ 0.1 V
V
LOAD
0.1 V
Timing Reference
Points
V
LOAD
V
OH
0.1 V
V
OL
+ 0.1 V
For timing purposes, a port pin is no longer floating when a
100 mV change from load voltage occurs and begins to float
when a 100 mV change from the loading V
OH
/V
OL
level occurs
with I
OL/
I
OH
=
20 mA.
A4117-01
32
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x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
7.0
THERMAL CHARACTERISTICS
The microcontroller operates over the commercial
temperature range from 0
o
C to 70
o
C. All thermal
impedance data (see Table 20) is approximate for
static air conditions at 1 watt of power dissipation.
Values change depending on operating conditions
and application requirements. The Intel
Packaging
Handbook
(order number 240800) describes Intel's
thermal impedance test methodology. The
Components Quality and Reliability Handbook
(order number 210997) provides quality and
reliability information.
8.0
DESIGN CONSIDERATIONS
8.1
External Bus Timing and
Peripheral Timing Affected by
PLLSEL2:0 Selection
PLLSEL2 (pin 43), PLLSEL1 (pin 42), and PLLSEL0
(pin 44) determine the 8
x
930H
x
internal CPU
operating frequency. See Table 13. Operate the
8
x
930H
x
at full speed by setting PLLSEL2:0 to 110.
This provides an internal clock frequency of 12 MHz
(F
CLK
= F
OSC
) and sets the microcontroller state time
equal to one oscillator period (T
OSC
).
The CPU operating frequency influences the timing
of all on-chip peripherals. Refer to the
8X930Ax
,
8X930H
x Universal Serial Bus Microcontroller
User's Manual
for peripheral timing formulas (refer
to Table 1 on page 1 for ordering information).
8.2
Low Clock Mode Frequency
The internal clock F
CLK
distributed to the CPU and
peripherals is 3 MHz. Peripheral timing and external
bus accesses (including instruction fetch and data
read/write) are affected. Refer to Table 13 for clock
rates.
8.3
Setting RXFFRC Bit Clears Only
the Oldest Packet in the FIFO
If the receive FIFO is set as a dual packet mode,
then it can receive two packets. Setting RXFFRC (in
RXCON registers) to indicate FIFO Read Complete
will not flush the entire FIFO; it will flush only the
oldest packet. The read marker will be advanced to
the location of the read pointer.
8.4
Series Resistor Requirement for
Impedance Matching
Per USB rev. 1.0 specification (page 111, section
7.1.1.1), the impedance of the differential driver
must be between 29
and 44
. To match the cable
impedance, a series resistor of 27
to 33
should
be connected to each USB line; i.e., on D
P
0
(pin 55)
and on D
M
0
(pin 54). If the USB line is improperly
terminated or not matched, then signal fidelity will
suffer. This condition can be seen on the oscillo-
scopes as excessive overshoot and undershoot.
This condition can potentially introduce bit errors.
8.5
Pullup Resistor Requirement
for 8
x
930H
x
Hub devices
The USB specification requires a pullup resistor to
allow the host to identify which devices are low
speed and which are full speed in order to commu-
nicate at the appropriate data rate. For 8
x
930H
x
hub devices (12 Mbps), use a 1.5K
pullup resistor
(to 3.0 V 3.6 V) on the D
P
0
line.
8.6
Powerdown Mode Cannot Be
Invoked Before USB Suspend
If the 8
x
930H
x
is put into powerdown mode before
receiving a USB suspend signal from the host, then
a USB resume will not properly wake up the
8
x
930H
x
from powerdown model.
Table 20. Thermal Characteristics
Package Type
JA
JC
68-pin PLCC
N/A
N/A
ADVANCE INFORMATION
33
8
x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
8.7
Unused Downstream Ports
If the USB downstream ports are not used, it is still
required that the two data lines be pulled low
externally (similar to a disconnect) so that the inputs
are not floating. This will eliminate the possibility of
induced system noise. When migrating from the
8
x
930HD/HE (3 external downstream port device)
to the 8
x
930HF/HG (4 external downstream port
device), and the additional USB port is not being
used in the application, D
M5
and D
P5
will still require
15K external pulldown resistors. Do not leave the
unused port disconnected.
9.0
8
x
930H
x
ERRATA
The 8
x
930H
x
may contain design defects or errors
known as errata. Characterized errata that may
cause the 8
x
930H
x
's operational behavior to
deviate from published specifications are
documented in a specification update (order
number 272962). Specification updates can be
obtained from your local Intel sales office or from
the World Wide Web (
www.intel.com
).
10.0 DATASHEET REVISION HISTORY
Datasheets are changed as new device information
becomes available. Verify with your local Intel sales
office that you have the latest version before
finalizing a design or ordering devices.
This (-003) revision of the 8
x
930H
x
datasheet
replaces earlier product information. The following
changes were made in this revision:
1. Added the 8
x
930HF/HG 4 external
downstream port device.
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