Other brands and names are the property of their respective owners

Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata

April 1996

INTEL CORPORATION 1996

Order Number 272322-004

8XC51FX

CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS

Commercial Express

87C51FA 83C51FA 80C51FA 87C51FB 83C51FB 87C51FC 83C51FC

See Table 1 for Proliferation Options

High Performance CHMOS
EPROM ROM CPU

12 24 33 MHz Operation

Three 16-Bit Timer Counters

Programmable Counter Array with

High Speed Output
Compare Capture
Pulse Width Modulator
Watchdog Timer Capabilities

Up Down Timer Counter

Three Level Program Lock System

8K 16K 32K On-Chip Program Memory

256 Bytes of On-Chip Data RAM

Improved Quick Pulse Programming
Algorithm

Boolean Processor

32 Programmable I O Lines

7 Interrupt Sources

Four Level Interrupt Priority

Programmable Serial Channel with

Framing Error Detection
Automatic Address Recognition

TTL Compatible Logic Levels

64K External Program Memory Space

64K External Data Memory Space

MCS

51 Controller Compatible

Instruction Set

Power Saving Idle and Power Down
Modes

ONCE (On-Circuit Emulation) Mode

Extended Temperature Range Except
for 33 MHz Offering (

40 C to

85 C)

MEMORY ORGANIZATION

Device

ROM

Version

EPROM

ROMLESS

Version

ROM

Bytes

RAM

EPROM

Bytes

83C51FA

87C51FA

80C51FA

256

83C51FB

87C51FB

80C51FA

16K

256

83C51FC

87C51FC

80C51FA

32K

256

These devices can address up to 64 Kbytes of external program data memory

The Intel 87C51FA 8XC51FB 8XC51FC is a single-chip control oriented microcontroller which is fabricated on
Intel's reliable CHMOS III-E technology The Intel 83C51FA 80C51FA is fabricated on CHMOS III technology
Being a member of the MCS

51 controller family the 8XC51FA 8XC51FB 8XC51FC uses the same powerful

instruction set has the same architecture and is pin-for-pin compatible with the existing MCS 51 controller
products The 8XC51FA 8XC51FB 8XC51FC is an enhanced version of the 8XC52 8XC54 8XC58 Its added
features make it an even more powerful microcontroller for applications that require Pulse Width Modulation
High Speed I O and up down counting capabilities such as motor control

For the remainder of this document the 8XC51FA 8XC51FB 8XC51FC will be referred to as the 8XC51FX
unless information applies to a specific device

8XC51FX

PIN DESCRIPTIONS

Supply voltage

Circuit ground

SS1

Secondary ground (not on DIP devices or any

83C51FA 80C51FA device)

Provided to reduce

ground bounce and improve power supply by-pass-
ing

NOTE

This pin is not a substitution for the V

pin (Con-

nection not necessary for proper operation )

Port 0

Port 0 is an 8-bit open drain bidirectional

I O port As an output port each pin can sink several
LS TTL inputs Port 0 pins that have 1's written to
them float and in that state can be used as high-im-
pedance inputs

Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory In this application it uses strong inter-
nal pullups when emitting 1's and can source and
sink several LS TTL inputs

Port 0 also receives the code bytes during EPROM
programming and outputs the code bytes during
program verification External pullup resistors are re-
quired during program verification

Port 1

Port 1 is an 8-bit bidirectional I O port with

internal pullups The Port 1 output buffers can drive
LS TTL inputs Port 1 pins that have 1's written to
them are pulled high by the internal pullups and in
that state can be used as inputs As inputs Port 1
pins that are externally pulled low will source current
(I

on the data sheet) because of the internal pull-

ups

In addition Port 1 serves the functions of the follow-
ing special features of the 8XC51FX

Port Pin

Alternate Function

P1 0

T2 (External Count Input to Timer
Counter 2) Clock Out

P1 1

T2EX (Timer Counter 2 Capture
Reload Trigger and Direction Control)

P1 2

ECI (External Count Input to the PCA)

P1 3

CEX0 (External I O for Compare
Capture Module 0)

P1 4

CEX1 (External I O for Compare
Capture Module 1)

P1 5

CEX2 (External I O for Compare
Capture Module 2)

P1 6

CEX3 (External I O for Compare
Capture Module 3)

P1 7

CEX4 (External I O for Compare
Capture Module 4)

Port 1 receives the low-order address bytes during
EPROM programming and verifying

Port 2

Port 2 is an 8-bit bidirectional I O port with

internal pullups The Port 2 output buffers can drive
LS TTL inputs Port 2 pins that have 1's written to
them are pulled high by the internal pullups and in
that state can be used as inputs As inputs Port 2
pins that are externally pulled low will source current
(I

on the data sheet) because of the internal pull-

ups

Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX

DPTR) In this application it

uses strong internal pullups when emitting 1's Dur-
ing accesses to external Data Memory that use 8-bit
addresses (MOVX

Ri) Port 2 emits the contents of

the P2 Special Function Register

Some Port 2 pins receive the high-order address bits
during EPROM programming and program verifica-
tion

Port 3

Port 3 is an 8-bit bidirectional I O port with

internal pullups The Port 3 output buffers can drive
LS TTL inputs Port 3 pins that have 1's written to
them are pulled high by the internal pullups and in
that state can be used as inputs As inputs Port 3
pins that are externally pulled low will source current
(I

on the data sheet) because of the pullups

8XC51FX

Port 3 also serves the functions of various special
features of the MCS-51 Family as listed below

Port Pin

Alternate Function

P3 0

RXD (serial input port)

P3 1

TXD (serial output port)

P3 2

INT0 (external interrupt 0)

P3 3

INT1 (external interrupt 1)

P3 4

T0 (Timer 0 external input)

P3 5

T1 (Timer 1 external input)

P3 6

WR (external data memory write strobe)

P3 7

RD (external data memory read strobe)

RST

Reset input A high on this pin for two machine

cycles while the oscillator is running resets the de-
vice The port pins will be driven to their reset condi-
tion when a minimum V

IH1

voltage is applied wheth-

er the oscillator is running or not An internal pull-
down resistor permits a power-on reset with only a
capacitor connected to V

ALE

Address Latch Enable output pulse for latching

the low byte of the address during accesses to ex-
ternal memory This pin (ALE PROG) is also the
program pulse input during EPROM programming for
the 87C51FX

In normal operation ALE is emitted at a constant
rate of

the oscillator frequency and may be used

for external timing or clocking purposes Note how-
ever that one ALE pulse is skipped during each ac-
cess to external Data Memory

If desired ALE operation can be disabled by setting
bit 0 of SFR location 8EH With this bit set the pin is
weakly pulled high However the ALE disable fea-
ture will be suspended during a MOVX or MOVC in-
struction idle mode power down mode and ICE
mode The ALE disable feature will be terminated by
reset When the ALE disable feature is suspended or
terminated the ALE pin will no longer be pulled up
weakly Setting the ALE-disable bit has no affect if
the microcontroller is in external execution mode

Throughout the remainder of this data sheet ALE
will refer to the signal coming out of the ALE PROG
pin and the pin will be referred to as the ALE PROG
pin

PSEN

Program Store Enable is the read strobe to

external Program Memory

When the 8XC51FX is executing code from external
Program Memory PSEN is activated twice each ma-
chine cycle except that two PSEN activations are
skipped during each access to external Data Memo-
ry

EA V

External Access enable

EA must be

strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
0000H to 0FFFH Note however that if either of the
Program Lock bits are programmed EA will be inter-
nally latched on reset

EA should be strapped to V

for internal program

executions

This pin also receives the programming supply volt-
age (V

) during EPROM programming

XTAL1

Input to the inverting oscillator amplifier

XTAL2

Output from the inverting oscillator amplifi-

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output respec-
tively of a inverting amplifier which can be config-
ured for use as an on-chip oscillator as shown in
Figure 3 Either a quartz crystal or ceramic resonator
may be used More detailed information concerning
the use of the on-chip oscillator is available in Appli-
cation Note AP-155 ``Oscillators for Microcontrol-
lers ''

To drive the device from an external clock source
XTAL1 should be driven while XTAL2 floats as
shown in Figure 4 There are no requirements on the
duty cycle of the external clock signal since the in-
put to the internal clocking circuitry is through a
divide-by-two flip-flop but minimum and maximum
high and low times specified on the data sheet must
be observed

An external oscillator may encounter as much as a
100 pF load at XTAL1 when it starts up This is due
to interaction between the amplifier and its feedback
capacitance Once the external signal meets the V

and V

specifications the capacitance will not ex-

ceed 20 pF

8XC51FX

272322 � 3

C1 C2 e 30 pF

10 pF for Crystals

For Ceramic Resonators contact resonator manufacturer

Figure 3 Oscillator Connections

272322 � 4

Figure 4 External Clock Drive Configuration

IDLE MODE

The user's software can invoke the Idle Mode When
the microcontroller is in this mode power consump-
tion is reduced The Special Function Registers and
the onboard RAM retain their values during Idle but
the processor stops executing instructions

Idle

Mode will be exited if the chip is reset or if an en-
abled interrupt occurs The PCA timer counter can
optionally be left running or paused during Idle
Mode

POWER DOWN MODE

To save even more power a Power Down mode can
be invoked by software In this mode the oscillator
is stopped and the instruction that invoked Power

Down is the last instruction executed The on-chip
RAM and Special Function Registers retain their val-
ues until the Power Down mode is terminated

On the 8XC51FX either hardware reset or external
interrupt can cause an exit from Power Down Reset
redefines all the SFRs but does not change the on-
chip RAM An external interrupt allows both the
SFRs and the on-chip RAM to retain their values

To properly terminate Power Down the reset or ex-
ternal interrupt should not be executed before V

restored to its normal operating level and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms)

With an external interrupt INT0 or INT1 must be en-
abled and configured as level-sensitive Holding the
pin low restarts the oscillator but bringing the pin
back high completes the exit Once the interrupt is
serviced the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down

DESIGN CONSIDERATION

Ambient light is known to affect the internal RAM
contents during operation If the 87C51FX appli-
cation requires the part to be run under ambient
lighting an opaque label should be placed over
the window to exclude light

When the idle mode is terminated by a hardware
reset the device normally resumes program exe-
cution from where it left off up to two machine
cycles before the internal reset algorithm takes
control On-chip hardware inhibits access to inter-
nal RAM in this event but access to the port pins
is not inhibited To eliminate the possibility of an
unexpected write when Idle is terminated by re-
set the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory

Table 2 Status of the External Pins during Idle and Power Down

Mode

Program

ALE

PSEN

PORT0

PORT1

PORT2

PORT3

Memory

Idle

Internal

Data

Idle

External

Float

Data

Address

Data

Power Down

Internal

Data

Power Down

External

Float

Data

NOTE
For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors
Handbook Volume I and Application Note AP-252 (Embedded Applications Handbook) ``Designing with the 80C51BH ''

8XC51FX

ONCE MODE

The ONCE (``On-Circuit Emulation'') Mode facilitates
testing

and

debugging

systems

using

the

8XC51FX without the 8XC51FX having to be re-
moved from the circuit The ONCE Mode is invoked
by

1) Pull ALE low while the device is in reset and

PSEN is high

2) Hold ALE low as RST is deactivated

While the device is in ONCE Mode the Port 0 pins
float and the other port pins and ALE and PSEN are
weakly pulled high The oscillator circuit remains ac-
tive While the 8XC51FX is in this mode an emulator
or test CPU can be used to drive the circuit Normal
operation is restored when a normal reset is applied

8XC51FX EXPRESS

The Intel EXPRESS system offers enhancements to
the operational specifications of the MCS-51 family
of microcontrollers These EXPRESS products are
designed to meet the needs of those applications
whose operating requirements exceed commercial
standards

The EXPRESS program includes the commercial
standard temperature range with burn-in and an ex-
tended temperature range with or without burn-in

With the commercial standard temperature range
operational characteristics are guaranteed over the
temperature range of 0 C to 70 C With the extend-
ed temperature range option operational character-
istics are guaranteed over the range of b40 C to

85 C

The optional burn-in is dynamic for a minimum time
of 168 hours at 125 C with V

6 9V

0 25V

following guidelines in MlL-STD-883 Method 1015

Package types and EXPRESS versions are identified
by a one- or two-letter prefix to the part number The
prefixes are listed in Table 3

For the extended temperature range option this
data sheet specifies the parameters which deviate
from their commercial temperature range limits

NOTE

Intel offers Express Temperature specifica-
tions for all 8XC51FX speed options except
for 33 MHz

Table 3 Prefix Identification

Prefix

Package Type

Temperature Range

Burn-In

Cerdip

Commercial

PLCC

Commercial

Plastic

Commercial

QFP

Commercial

Cerdip

Extended

Yes

PLCC

Extended

Yes

Plastic

Extended

Yes

QFP

Extended

Yes

Cerdip

Extended

PLCC

Extended

Plastic

Extended

QFP

Extended

NOTE
Contact distributor or local sales office to match EXPRESS prefix with proper device

EXAMPLES
P87C51FC indicates 87C51FC in a plastic package and specified for commercial temperature range without burn-in
LD87C51FC indicates 87C51FC in a cerdip package and specified for extended temperature range with burn-in

8XC51FX

ABSOLUTE MAXIMUM RATINGS

Ambient Temperature Under Bias b40 C to a85 C

Storage Temperature

65 C to a150 C

Voltage on EA V

Pin to V

0V to a13 0V

Voltage on Any Other Pin to V

0 5V to a6 5V

per I O Pin

15 mA

Power Dissipation

1 5W

(based on PACKAGE heat transfer limitations not
device power consumption)

NOTICE This data sheet contains preliminary infor-
mation on new products in production It is valid for
the devices indicated in the revision history The
specifications are subject to change without notice

WARNING Stressing the device beyond the ``Absolute

Maximum Ratings'' may cause permanent damage
These are stress ratings only Operation beyond the
``Operating Conditions'' is not recommended and ex-
tended exposure beyond the ``Operating Conditions''
may affect device reliability

OPERATING CONDITIONS

Symbol

Description

Min

Max

Units

Ambient Temperature Under Bias

Commercial

Express

Supply Voltage
8XC51FX-33

4 5

5 5

All Others

4 0

6 0

OSC

Oscillator Frequency

8XC51FX

3 5

8XC51FX-1

3 5

MHz

8XC51FX-2

0 5

8XC51FX-24

3 5

8XC51FX-33

3 5

DC CHARACTERISTICS

(Over Operating Conditions)

All parameter values apply to all devices unless otherwise indicated

Symbol

Parameter

Min

Typical

Max

Units

Test Conditions

(Note 4)

Input Low Voltage

0 5

0 2 V

0 1

IL1

Input Low Voltage EA

0 2 V

0 3

Input High Voltage

0 2 V

0 9

0 5

(Except XTAL1 RST)

IH1

Input High Voltage

0 7 V

0 5

(XTAL1 RST)

Output Low Voltage (Note 5)

0 3

100 mA

(Ports 1 2 and 3)

0 45

1 6 mA (Note 1)

1 0

3 5 mA

OL1

Output Low Voltage (Note 5)

0 3

200 mA

(Port 0 ALE PROG PSEN)

0 45

3 2 mA (Note 1)

1 0

7 0 mA

Output High Voltage

0 3

e b

10 mA

(Ports 1 2 and 3

0 7

e b

30 mA (Note 2)

ALE PROG and PSEN)

1 5

e b

60 mA

OH1

Output High Voltage

0 3

e b

200 mA

(Port 0 in External Bus Mode)

0 7

e b

3 2 mA (Note 2)

1 5

e b

7 0 mA

83C51FA 80C51FA (Express)

e b

6 0 mA

Logical 0 Input Current

0 45V

(Ports 1 2 and 3)

8XC51FX

DC CHARACTERISTICS

(Over Operating Conditions)

All parameter values apply to all devices unless otherwise indicated (Continued)

Symbol

Parameter

Min

Typical

Max

Units

Test Conditions

(Note 4)

Input leakage Current (Port 0)

or V

Logical 1 to 0 Transition Current

(Ports 1 2 and 3)
Express

750

Commercial

650

RRST

RST Pulldown Resistor

225

CIO

Pin Capacitance

1MHz 25 C

Power Supply Current

(Note 3)

Active Mode

At 12 MHz (Figure 5)

At 16 MHz

At 24 MHz

At 33 MHz

Idle Mode

At 12 MHz (Figure 5)

7 5

At 16 MHz

9 5

At 24 MHz

13 5

At 33 MHz

Power Down Mode

NOTES
1 Capacitive loading on Ports 0 and 2 may cause noise pulses above 0 4V to be superimposed on the V

s of ALE and

Ports 1 2 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to 0 In applications where capacitance loading exceeds 100 pF the noise pulses on these signals may
exceed 0 8V It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic
2 Capacitive loading on Ports 0 and 2 cause the V

on ALE and PSEN to drop below the 0 9 V

specification when the

address lines are stabilizing
3 See Figures 6 � 9 for test conditions Minimum V

for power down is 2V

4 Typicals are based on limited number of samples and are not guaranteed The values listed are at room temperature and 5V
5 Under steady state (non-transient) conditions I

must be externally limited as follows

Maximum I

per port pin

10 mA

Maximum I

per 8-bit port -

Port 0

26 mA

Ports 1 2 and 3

15 mA

Maximum total I

for all output pins

71 mA

If I

exceeds the test condition V

may exceed the related specification Pins are not guaranteed to sink current greater

than the listed test conditions

272322 � 5

Note
I

max at 33 MHz is at 5V

10% V

while I

max at 24 MHz and below is at 5V

20% V

Figure 5 8XC51FA FB FC I

vs Frequency

8XC51FX

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has 5 characters The first char-
acter is always a `T' (stands for time) The other
characters depending on their positions stand for
the name of a signal or the logical status of that
signal The following is a list of all the characters and
what they stand for

A Address

C Clock

D Input Data

H Logic level HIGH

I Instruction (program memory contents)

L Logic level LOW or ALE

P PSEN

Q Output Data

R RD signal

T Time

V Valid

W WR signal

X No longer a valid logic level

Z Float

For example

TAVLL e Time from Address Valid to ALE Low

TLLPL e Time from ALE Low to PSEN Low

AC CHARACTERISTICS

(Over Operating Conditions Load Capacitance for Port 0 ALE PROG and

PSEN e 100 pF Load Capacitance for All Other Outputs e 80 pF)

EXTERNAL MEMORY CHARACTERISTICS

All parameter values apply to all devices unless otherwise indicated In this table 8XC51FX refers to
8XC51FX 8XC51FX-1 and 8XC51FX-2

Symbol

Parameter

Oscillator

Units

12 MHz

24 MHz

33 MHz

Variable

Min Max Min Max Min Max

Min

Max

1 TCLCL Oscillator Frequency

MHz

8XC51FX

3 5

8XC51FX-1

3 5

8XC51FX-2

0 5

8XC51FX-24

3 5

8XC51FX-33

3 5

TLHLL

ALE Pulse Width

127

2TCLCLb40

TAVLL

Address Valid to ALE Low
8XC51FX

TCLCLb40

8XC51FX-24

TCLCLb30

8XC51FX-33

TCLCLb25

TLLAX

Address Hold After ALE Low
8XC51FX -24

TCLCLb30

8XC51FX-33

TCLCLb25

TLLIV

ALE Low to Valid Instr In
8XC51FX

234

4TCLCLb100

8XC51FX-24

4TCLCLb75

8XC51FX-33

4TCLCLb65

TLLPL

ALE Low to PSEN Low
8XC51FX -24

TCLCLb30

8XC51FX-33

TCLCLb25

TPLPH

PSEN Pulse Width

205

3TCLCLb45

TPLIV

PSEN Low to Valid Instr In
8XC51FX

145

3TCLCLb105

8XC51FX-24

3TCLCLb90

8XC51FX-33

3TCLCLb55

TPXIX

Input Instr Hold after PSEN

8XC51FX

EXTERNAL MEMORY CHARACTERISTICS

(Continued)

All parameter values apply to all devices unless otherwise indicated

Symbol

Parameter

Oscillator

Units

12 MHz

24 MHz

33 MHz

Variable

Min Max Min Max Min Max

Min

Max

TPXIZ

Input Instr Float After PSEN
8XC51FX

TCLCL-25

8XC51FX-24

TCLCL-20

8XC51FX-33

TCLCL-25

TAVIV

Address to Valid Instr In
8XC51FX -24

312

103

5TCLCLb105

8XC51FX-33

5TCLCLb80

TPLAZ

PSEN Low to Address Float

TRLRH RD Pulse Width

400

150

6TCLCLb100

TWLWH WR Pulse Width

400

150

6TCLCLb100

TRLDV RD Low to Valid Data In

8XC51FX

252

5TCLCLb165

8XC51FX-24

113

5TCLCLb95

8XC51FX-33

5TCLCLb90

TRHDX Data Hold After RD

TRHDZ Data Float After RD

8XC51FX 24

107

2TCLCLb60

8XC51FX-33

2TCLCLb25

TLLDV

ALE Low to Valid Data In
8XC51FX

517

8TCLCLb150

8XC51FX-24 33

243

150

8TCLCLb90

TAVDV Address to Valid Data In

8XC51FX

585

9TCLCLb165

8XC51FX-24 33

285

180

9TCLCLb90

TLLWL

ALE Low to RD or WR Low

200 300

175

140

3TCLCLb50

3TCLCLa50

TAVWL Address to RD or WR Low

8XC51FX

203

4TCLCLb130

8XC51FX-24

4TCLCLb90

8XC51FX-33

4TCLCLb75

TQVWX Data Valid to WR Transition

8XC51FX

TCLCLb50

8XC51FX-24 33

TCLCLb30

TWHQX Data Hold After WR

8XC51FX

TCLCLb50

8XC51FX-24

TCLCLb35

8XC51FX-33

TCLCLb27

TQVWH Data Valid to WR High

8XC51FX

433

7TCLCLb150

8XC51FX-24 33

222

142

7TCLCLb70

TRLAZ

RD Low to Address Float

TWHLH RD or WR High to ALE High

8XC51FX

123

TCLCLb40

TCLCLa40

8XC51FX-24

TCLCLb30

TCLCLa30

8XC51FX-33

TCLCLb25

TCLCLa25

8XC51FX

EXTERNAL CLOCK DRIVE

Symbol

Parameter

Min

Max

Units

1 TCLCL

Oscillator Frequency

MHz

8XC51FX

3 5

MHz

8XC51FX-1

3 5

MHz

8XC51FX-2

0 5

MHz

8XC51FX-24

3 5

MHz

8XC51FX-33

3 5

MHz

TCHCX

High Time

8XC51FX-24 33

0 35 T

OSC

0 65 T

OSC

TCLCX

Low Time

8XC51FX-24 33

0 35 T

OSC

0 65 T

OSC

TCLCH

Rise Time

8XC51FX-24

8XC51FX-33

TCHCL

Fall Time

8XC51FX-24

8XC51FX-33

EXTERNAL CLOCK DRIVE WAVEFORM

272322 � 13

AC TESTING INPUT OUTPUT WAVEFORMS

272322 � 14

AC Inputs during testing are driven at V

0 5V for a Logic ``1''

and 0 45V for a Logic ``0'' Timing measurements are made at V

min for a Logic ``1'' and V

max for a Logic ``0''

FLOAT WAVEFORMS

272322 � 15

For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs and begins to float
when a 100 mV change from the loaded V

level occurs

20 mA

8XC51FX

PROGRAMMING THE EPROM OTP

To be programmed the part must be running with a
4 to 6 MHz oscillator (The reason the oscillator
needs to be running is that the internal bus is being
used to transfer address and program data to appro-
priate internal EPROM locations ) The address of an
EPROM location to be programmed is applied to
Port 1 and pins P2 0 - P2 4 of Port 2 while the code
byte to be programmed into that location is applied
to Port 0 The other Port 2 and 3 pins RST PSEN
and EA V

should be held at the ``Program'' levels

indicated in Table 4 ALE PROG is pulsed low to
program the code byte into the addressed EPROM
location The setup is shown in Figure 10

Normally EA V

is held at logic high until just be-

fore ALE PROG is to be pulsed Then EA V

raised to V

ALE PROG is pulsed low and then

EA V

is returned to a valid high voltage The volt-

age on the EA V

pin must be at the valid EA V

high level before a verify is attempted Waveforms
and detailed timing specifications are shown in later
sections of this data sheet

NOTE

EA V

pin must not be allowed to go above the

maximum specified V

level for any amount of

time Even a narrow glitch above that voltage lev-
el can cause permanent damage to the device
The V

source should be well regulated and free

of glitches

Table 4 EPROM Programming Modes

Mode

RST

PSEN

ALE

P2 6

P2 7

P3 3

P3 6

P3 7

PROG

Program Code Data

12 75V

Verify Code Data

Program Encryption

12 75V

Array Address 0 � 3FH

Program Lock

Bit 1

12 75V

Bits

Bit 2

12 75V

Bit 3

12 75V

Read Signature Byte

272322 � 20

See Table 4 for proper input on these pins

Figure 10 Programming the EPROM

8XC51FX

PROGRAMMING ALGORITHM

Refer to Table 4 and Figures 10 and 11 for address
data and control signals set up To program the
87C51FX the following sequence must be exercised

1 Input the valid address on the address lines

2 Input the appropriate data byte on the data

lines

3 Activate the correct combination of control sig-

nals

4 Raise EA V

from V

to 12 75V

0 25V

5 Pulse ALE PROG 5 times for the EPROM ar-

ray and 25 times for the encryption table and
the lock bits

Repeat 1 through 5 changing the address and data
for the entire array or until the end of the object file is
reached

PROGRAM VERIFY

Program verify may be done after each byte or block
of bytes is programmed In either case a complete
verify of the programmed array will ensure reliable
programming of the 87C51FX

The lock bits cannot be directly verified Verification
of the lock bits is done by observing that their fea-
tures are enabled

272322 � 21

Figure 11 Programming Signals Waveforms

ROM and EPROM Lock System

The 87C51FX program lock system

when pro-

grammed protects the onboard program against
software piracy

The 83C51FX has a one-level program lock system
and a 64-byte encryption table See line 2 of Table
5 If program protection is desired the user submits
the encryption table with their code and both the

lock-bit and encryption array are programmed by the
factory The encryption array is not available without
the lock bit For the lock bit to be programmed the
user must submit an encryption table The 83C51FA
does not have protection features

The 87C51FX has a 3-level program lock system
and a 64-byte encryption array Since this is an
EPROM device all locations are user-programma-
ble See Table 5

Table 5 Program Lock Bits and the Features

Program Lock Bits

ProtectIon Type

LB1

LB2

LB3

No Program Lock features enabled (Code verify will still be encrypted by the
Encryption Array if programmed )

MOVC instructions executed from external program memory are disabled from
fetching code bytes from internal memory EA is sampled and latched on Reset and
further programming of the EPROM is disabled

Same as 2 also verify is disabled

Same as 3 also external execution is disabled

Any other combination of the lock bits is not defined

8XC51FX

Encryption Array

Within the EPROM array are 64 bytes of Encryption
Array that are initially unprogrammed (all 1's) Every
time that a byte is addressed during a verify 6 ad-
dress lines are used to select a byte of the Encryp-
tion Array

This byte is then exclusive-NOR'ed

(XNOR) with the code byte creating an Encryption
Verify byte The algorithm with the array in the un-
programmed state (all 1's) will return the code in its
original unmodified form For programming the En-
cryption Array refer to Table 4 (Programming the
EPROM)

When using the encryption array one important fac-
tor needs to be considered If a code byte has the
value 0FFH verifying the byte will produce the en-
cryption byte value lf a large block (

64 bytes) of

code is left unprogrammed a verification routine will
display the contents of the encryption array For this
reason all unused code bytes should be pro-
grammed with some value other than 0FFH and not
all of them the same value This will ensure maxi-
mum program protection

Program Lock Bits

The 87C51FX has 3 programmable lock bits that
when programmed according to Table 5 will provide
different levels of protection for the on-chip code
and data

Erasing the EPROM also erases the encryption ar-
ray and the program lock bits returning the part to
full functionality

Reading the Signature Bytes

The 87C51FX has 3 signature bytes in locations
30H 31H and 60H The 83C51FA has 2 signature

bytes in locations 30H and 31H To read these bytes
follow the procedure for EPROM verify but activate
the control lines provided in Table 4 for Read Signa-
ture Byte

Location

Device

Contents

30H

All

89H

31H

All

58H

60H

83C51FA

7AH FAH

87C51FA

FAH

83C51FB

7BH FBH

87C51FB

FBH

83C51FC

7CH FCH

87C51FC

FCH

Erasure Characteristics (Windowed
Packages Only)

Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelength shorter than
approximately 4 000 Angstroms Since sunlight and
fluorescent lighting have wavelengths in this range
exposure to these light sources over an extended
time (about 1 week in sunlight or 3 years in room-
level fluorescent lighting) could cause inadvertent
erasure If an application subjects the device to this
type of exposure it is suggested that an opaque la-
bel be placed over the window

The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrat-
ed dose of at least 15 W-sec cm Exposing the
EPROM to an ultraviolet lamp of 12 000 mW cm rat-
ing for 30 minutes at a distance of about 1 inch
should be sufficient

Erasure leaves all the EPROM Cells in a 1's state

8XC51FX

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS

21 C to 27 C V

20% V

0V)

Symbol

Parameter

Min

Max

Units

Programming Supply Voltage

12 5

13 0

Programming Supply Current

1 TCLCL

Oscillator Frequency

MHz

TAVGL

Address Setup to PROG Low

48TCLCL

TGHAX

Address Hold after PROG

48TCLCL

TDVGL

Data Setup to PROG Low

48TCLCL

TGHDX

Data Hold after PROG

48TCLCL

TEHSH

P2 7 (ENABLE) High to V

48TCLCL

TSHGL

Setup to PROG Low

TGHSL

Hold after PROG

TGLGH

PROG Width

110

TAVQV

Address to Data Valid

48TCLCL

TELQV

ENABLE Low to Data Valid

48TCLCL

TEHQZ

Data Float after ENABLE

48TCLCL

TGHGL

PROG High to PROG Low

EPROM PROGRAMMING AND VERIFICATION WAVEFORMS

272322 � 18

NOTE

5 pulses for the EPROM array 25 pulses for the encryption table and lock bits

8XC51FX

Thermal Impedance

All thermal impedance data is approximate for static
air conditions at 1W of power dissipation Values will
change depending on operating conditions and ap-
plications See the Intel Packaging Handbook (Order
No 240800) for a description of Intel's thermal im-
pedance test methodology

Package

Device

45 C W 16 C W All

36 C W 13 C W 80C51FA 83C51FA

8XC51FC

45 C W 15 C W 87C51FA 8XC51FB

46 C W 16 C W All

97 C W 24 C W FA
96 C W 24 C W FB
87 C W 18 C W FC

DATA SHEET REVISION HISTORY

Data sheets are changed as new device information becomes available Verify with your local Intel sales office
that you have the latest version before finalizing a design or ordering devices

The following differences exist between this datasheet (272322-003) and the previous version (272322-002)

1 Removed 8XC51FX-3 and 8XC51FX-20 replaced with 8XC51FX-24

2 Included 8XC51FX-24 and 8XC51FX-33 devices

3 80C51FA and 83C51FA now have the same features as 87C51FA 8XC51FB and 8XC51FC same DC spec

used for all devices

The following differences exist between the ``-002'' and ``-001'' version of 8XC51FX datasheet

1 Removed 8XC51FX-L from datasheet

2 Include V

OH1

for 83C51FA (Express) 80C51FA (Express)

This 8XC51FX datasheet (272322-001) replaces the following datasheets

87C51FA 83C51FA 80C51FA

270258-007

83C51FA 80C51FA EXPRESS

270620-001

87C51FA EXPRESS

270619-001

87C51FA-20 -3

272081-002

87C51FB 83C51FB

270563-005

87C51FB-20 -3 83C51FB-20 -3

272080-002

87C51FB 83C51FB EXPRESS

270767-002

87C51FC 83C51FC

270789-004

87C51FC 83C51FC EXPRESS

270903-001

87C51FC-20 -3 83C51FC-20 -3

272028-002

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: 8XC51FX-2

Document Outline

协谢械泻褌褉芯薪薪褘泄 泻芯屑锌芯薪械薪褌: 8XC51FX-2

Document Outline

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: 8XC51FX-2