80960JA/JF/JD/JT 3.3 V EMBEDDED
32-BIT MICROPROCESSOR

Advance Information Datasheet

Product Features

Pin/Code Compatible with all 80960Jx
Processors

High-Performance Embedded Architecture

-- One Instruction/Clock Execution

-- Core Clock Rate is:

80960JA/JF 1x the Bus Clock
80960JD 2x the Bus Clock
80960JT 3x the Bus Clock

-- Load/Store Programming Model

-- Sixteen 32-Bit Global Registers

-- Sixteen 32-Bit Local Registers (8 sets)

-- Nine Addressing Modes

-- User/Supervisor Protection Model

Two-Way Set Associative Instruction
Cache

-- 80960JA - 2 Kbyte

-- 80960JF/JD - 4 Kbyte

-- 80960JT - 16 Kbyte

-- Programmable Cache-Locking

Mechanism

Direct Mapped Data Cache

-- 80960JA - 1 Kbyte

-- 80960JF/JD - 2 Kbyte

-- 80960JT - 4 Kbyte

-- Write Through Operation

On-Chip Stack Frame Cache

-- Seven Register Sets Can Be Saved

-- Automatic Allocation on Call/Return

-- 0-7 Frames Reserved for High-Priority

Interrupts

On-Chip Data RAM

-- 1 Kbyte Critical Variable Storage

-- Single-Cycle Access

3.3 V Supply Voltage

-- 5 V Tolerant Inputs

-- TTL Compatible Outputs

High Bandwidth Burst Bus

-- 32-Bit Multiplexed Address/Data

-- Programmable Memory Configuration

-- Selectable 8-, 16-, 32-Bit Bus Widths

-- Supports Unaligned Accesses

-- Big or Little Endian Byte Ordering

High-Speed Interrupt Controller

-- 31 Programmable Priorities

-- Eight Maskable Pins plus NMI

-- Up to 240 Vectors in Expanded Mode

Two On-Chip Timers

-- Independent 32-Bit Counting

-- Clock Prescaling by 1, 2, 4 or 8

-- lnternal Interrupt Sources

Halt Mode for Low Power

IEEE 1149.1 (JTAG) Boundary Scan
Compatibility

Packages

-- 132-Lead Pin Grid Array (PGA)

-- 132-Lead Plastic Quad Flat Pack

(PQFP)

-- 196-Ball Mini Plastic Ball Grid Array

(MPBGA)

Order Number: 273159-001

March, 1998

Notice: This document contains information on products in the sampling and initial production
phases of development. The specifications are subject to change without notice. Verify with your
local Intel sales office that you have the latest datasheet before finalizing a design.

80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The

80960JA/JF/JD/JT 3.3 V Microprocessor may contain design defects or errors known as errata which may cause the product to deviate from

published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.

*Third-party brands and names are the property of their respective owners.

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

Contents

1.0

Introduction

.................................................................................................................. 7

2.0

80960Jx Overview

...................................................................................................... 7

2.1

80960 Processor Core .......................................................................................... 9

2.2

Burst Bus............................................................................................................. 10

2.3

Timer Unit............................................................................................................ 10

2.4

Priority Interrupt Controller .................................................................................. 10

2.5

Instruction Set Summary ..................................................................................... 11

2.6

Faults and Debugging ......................................................................................... 11

2.7

Low Power Operation.......................................................................................... 11

2.8

Test Features ...................................................................................................... 12

2.9

Memory-Mapped Control Registers .................................................................... 12

2.10

Data Types and Memory Addressing Modes ...................................................... 12

3.0

Package Information

............................................................................................... 14

3.1

Pin Descriptions .................................................................................................. 16
3.1.1

Functional Pin Definitions....................................................................... 16

3.1.2

80960Jx 132-Lead PGA Pinout.............................................................. 22

3.1.3

80960Jx 132-Lead PQFP Pinout............................................................ 26

3.1.4

80960Jx 196-Ball MPBGA Pinout .......................................................... 29

3.2

Package Thermal Specifications ......................................................................... 34

3.3

Thermal Management Accessories..................................................................... 38
3.3.1

Heatsinks................................................................................................ 38

4.0

Electrical Specifications

........................................................................................ 39

4.1

Absolute Maximum Ratings................................................................................. 39

4.2

Operating Conditions........................................................................................... 39

4.3

Connection Recommendations ........................................................................... 40

4.4

VCC5 Pin Requirements (VDIFF) ....................................................................... 40

4.5

VCCPLL Pin Requirements................................................................................. 41

4.6

DC Specifications ................................................................................................ 42

4.7

AC Specifications ................................................................................................ 44
4.7.1

AC Test Conditions and Derating Curves .............................................. 47

4.7.2

AC Timing Waveforms ........................................................................... 52

5.0

Bus Functional Waveforms

.................................................................................. 58

5.1

Basic Bus States ................................................................................................. 68

5.2

Boundary-Scan Register ..................................................................................... 69

6.0

Device Identification

............................................................................................... 74

7.0

Revision History

....................................................................................................... 77

80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

Figures

80960Jx Microprocessor Package Options...........................................................7

80960Jx Block Diagram ........................................................................................9

132-Lead Pin Grid Array Bottom View - Pins Facing Up.....................................22

132-Lead Pin Grid Array Top View - Pins Facing Down .....................................23

132-Lead PQFP - Top View ................................................................................26

196-Ball Mini Plastic Ball Grid Array Bottom View - Balls Facing Up ..................29

196-Ball Mini Plastic Ball Grid Array Top View - Balls Facing Down ..................30

VCC5 Current-Limiting Resistor ..........................................................................40

VCCPLL Lowpass Filter ......................................................................................41

AC Test Load ......................................................................................................47

Output Delay or Hold vs. Load Capacitance .......................................................48

vs. AD Bus Load Capacitance......................................................................48

80960JA/JF I

Active (Power Supply) vs. Frequency .......................................49

80960JA/JF I

Active (Thermal) vs. Frequency ................................................49

80960JD I

Active (Power Supply) vs. Frequency............................................50

80960JD I

Active (Thermal) vs. Frequency.....................................................50

80960JT I

Active (Power Supply) vs. Frequency ...........................................51

80960JT I

Active (Thermal) vs. Frequency .....................................................51

CLKIN Waveform ................................................................................................52

OV1

Output Delay Waveform .............................................................................52

Output Float Waveform ................................................................................53

IS1

and T

IH1

Input Setup and Hold Waveform ...................................................53

IS2

and T

IH2

Input Setup and Hold Waveform ...................................................53

IS3

and T

IH3

Input Setup and Hold Waveform ...................................................54

IS4

and T

IH4

Input Setup and Hold Waveform ...................................................54

, T

LXL

and T

LXA

Relative Timings Waveform.................................................55

DT/R and DEN Timings Waveform .....................................................................55

TCK Waveform....................................................................................................56

BSIS1

and T

BSIH1

Input Setup and Hold Waveforms .........................................56

BSOV1

and T

BSOF1

Output Delay and Output Float Waveform..........................56

BSOV2

and T

BSOF2

Output Delay and Output Float Waveform..........................57

BSIS2

and T

BSIH2

Input Setup and Hold Waveform ...........................................57

Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus .........58

Burst Read and Write Transactions Without Wait States, 32-Bit Bus .................59

Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus...........................60

Burst Read and Write Transactions Without Wait States, 8-Bit Bus ...................61

Burst Read and Write Transactions With 1, 0 Wait States and
Extra Tr State on Read, 16-Bit Bus .....................................................................62

Double Word Read Bus Request, Misaligned One Byte From
Quad Word Boundary, 32-Bit Bus, Little Endian .................................................63

HOLD/HOLDA Waveform For Bus Arbitration ....................................................64

Cold Reset Waveform .........................................................................................65

Warm Reset Waveform .......................................................................................66

Entering the ONCE State ....................................................................................67

Bus States with Arbitration ..................................................................................68

Summary of Aligned and Unaligned Accesses (32-Bit Bus) ...............................72

Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) ...........73

80960JT Device Identification Register...............................................................74

80960JD Device Identification Register ..............................................................75

80960JA/JF Device Identification Register .........................................................76

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

Tables

80960Jx Instruction Set....................................................................................... 13

Pin Description Nomenclature............................................................................. 16

Pin Description -- External Bus Signals ............................................................. 17

Pin Description -- Processor Control Signals, Test Signals and Power ............. 20

Pin Description -- Interrupt Unit Signals ............................................................. 21

132-Lead PGA Pinout -- In Signal Order............................................................ 24

132-Lead PGA Pinout -- In Pin Order ................................................................ 25

132-Lead PQFP Pinout -- In Signal Order ......................................................... 27

132-Lead PQFP Pinout -- In Pin Order .............................................................. 28

196-Ball MPBGA Pinout -- In Signal Order ........................................................ 31

196-Ball MPBGA Pinout -- In Pin Order ............................................................. 33

132-Lead PGA Package Thermal Characteristics............................................... 35

196-Ball MPBGA Package Thermal Characteristics ........................................... 35

132-Lead PQFP Package Thermal Characteristics ............................................ 36

Maximum T

at Various Airflows in °C (80960JT) ............................................... 36

Maximum T

at Various Airflows in °C (80960JD) .............................................. 37

Maximum T

at Various Airflows in °C (80960JA/JF).......................................... 37

Absolute Maximum Ratings................................................................................. 39

80960Jx Operating Conditions ............................................................................ 39

VDIFF Parameters .............................................................................................. 40

80960Jx DC Characteristics................................................................................ 42

80960Jx I

Characteristics................................................................................ 42

80960Jx AC Characteristics ................................................................................ 44

Note Definitions for Table 23, 80960Jx AC Characteristics (pg. 44) ................... 47

Boundary-Scan Register Bit Order...................................................................... 69

Natural Boundaries for Load and Store Accesses .............................................. 70

Summary of Byte Load and Store Accesses....................................................... 70

Summary of Short Word Load and Store Accesses............................................ 70

Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)........................... 71

80960Jx Device Type and Stepping Reference .................................................. 74

Fields of 80960JT Device ID ............................................................................... 75

80960JT Device ID Model Types ........................................................................ 75

Fields of 80960JD Device ID............................................................................... 76

80960JD Device ID Model Types........................................................................ 76

Fields of 80960JA/JF Device ID .......................................................................... 77

80960JA/JF Device ID Model Types ................................................................... 77

Data Sheet Revision History ............................................................................... 77

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

1.0

Introduction

This document contains information for the 80960Jx microprocessor, including electrical
characteristics and package pinout information. Detailed functional descriptions -- other than
parametric performance -- are published in the i960

Jx Microprocessor Developer's Manual

(272483).

Throughout this data sheet, references to "80960Jx" indicate features that apply to all of the
following:

80960JA -- 3.3 V (5 V Tolerant), 2 Kbyte instruction cache, 1 Kbyte data cache

80960JF -- 3.3 V (5 V Tolerant), 4 Kbyte instruction cache, 2 Kbyte data cache

80960JD -- 3.3 V (5 V Tolerant), 4 Kbyte instruction cache, 2 Kbyte data cache and clock
doubling

80960JT -- 3.3 V (5 V Tolerant), 16 Kbyte instruction cache, 4 Kbyte data cache and clock
tripling

2.0

80960Jx Overview

The 80960Jx offers high performance to cost-sensitive 32-bit embedded applications. The 80960Jx
is object code compatible with the 80960 Core Architecture and is capable of sustained execution
at the rate of one instruction per clock. This processor's features include generous instruction
cache, data cache and data RAM. It also boasts a fast interrupt mechanism and dual-programmable
timer units.

The 80960Jx's clock multiplication operates the processor core at two or three times the bus clock
rate to improve execution performance without increasing the complexity of board designs.

Memory subsystems for cost-sensitive embedded applications often impose substantial wait state
penalties. The 80960Jx integrates considerable storage resources on-chip to decouple CPU
execution from the external bus.

Figure 1.

80960Jx Microprocessor Package Options

i960

© 19xx

A80960JX

NG80960JX

XXXXXXXXSS

XXXXXXXX SS

© 19xx

GD80960JX
XXXXXXXSS

132-Pin PGA

132-Pin PQFP

136-Ball MPBGA

80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

The 80960Jx rapidly allocates and deallocates local register sets during context switches. The
processor needs to flush a register set to the stack only when it saves more than seven sets to its
local register cache.

A 32-bit multiplexed burst bus provides a high-speed interface to system memory and I/O. A full
complement of control signals simplifies the connection of the 80960Jx to external components.
The user programs physical and logical memory attributes through memory-mapped control
registers (MMRs) -- an extension not found on the i960 Kx, Sx or Cx processors. Physical and
logical configuration registers enable the processor to operate with all combinations of bus width
and data object alignment. The processor supports a homogeneous byte ordering model.

This processor integrates two important peripherals: a timer unit, and an interrupt controller. These
and other hardware resources are programmed through memory-mapped control registers, an
extension to the familiar 80960 architecture.

The timer unit (TU) offers two independent 32-bit timers for use as real-time system clocks and
general-purpose system timing. These operate in either single-shot or auto-reload mode and can
generate interrupts.

The interrupt controller unit (ICU) provides a flexible, low-latency means for requesting interrupts.
The ICU provides full programmability of up to 240 interrupt sources into 31 priority levels. The
ICU takes advantage of a cached priority table and optional routine caching to minimize interrupt
latency. Clock doubling reduces interrupt latency by 40% compared to the 80960JA/JF, and clock
tripling reduces interrupt latency by 20% compared to the 80960JD. Local registers may be
dedicated to high-priority interrupts to further reduce latency. Acting independently from the core,
the ICU compares the priorities of posted interrupts with the current process priority, off-loading
this task from the core. The ICU also supports the integrated timer interrupts.

The 80960Jx features a Halt mode designed to support applications where low power consumption
is critical. The halt instruction shuts down instruction execution, resulting in a power savings of up
to 90 percent.

The 80960Jx's testability features, including ONCE (On-Circuit Emulation) mode and Boundary
Scan (JTAG), provide a powerful environment for design debug and fault diagnosis.

The Solutions960

program features a wide variety of development tools which support the i960

processor family. Many of these tools are developed by partner companies; some are developed by
Intel, such as profile-driven optimizing compilers. For more information on these products, contact
your local Intel representative.

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

2.1

80960 Processor Core

The 80960Jx family is a scalar implementation of the 80960 Core Architecture. Intel designed this
processor core as a very high performance device that is also cost-effective. Factors that contribute
to the core's performance include:

Core operates at the bus speed with the 80960JA/JF

Core operates at two or three times the bus speed with the 80960JD and 80960JT respectively

Single-clock execution of most instructions

Independent Multiply/Divide Unit

Efficient instruction pipeline minimizes pipeline break latency

128-bit register bus speeds local register caching

Two-way set associative, integrated instruction cache

Direct-mapped, integrated data cache

1 Kbyte integrated data RAM delivers zero wait state program data

Figure 2.

80960Jx Block Diagram

Programmable

Interrupt Controller

Control

Address/

Instruction Sequencer

Physical Region

Configuration

Interrupt
Port

1K Data RAM

Memory

Interface

Execution

Multiply

Unit

Divide

Unit

Memory-Mapped

Data Bus

Global / Local

SRC2 DEST

SRC1

address

Control

effective

Constants

Generation

Unit

Address

32-bit Address

32-bit Data

Bus Request

Queues

and

Two 32-Bit

Timers

8-Set

Local Register Cache

SRC1

SRC2

DEST

PLL, Clocks,
Power Mgmt

Boundary Scan

Controller

TAP

CLKIN

RC1

RC2

SRC1

DES

32-bit buses

address / data

Instruction Cache

80960JA - 2K

80960JF/JD - 4K

80960JT - 16K

Two-Way Set Associative

Direct Mapped

Data Cache

80960JA - 1K

80960JF/JD - 2K

80960JT - 4K

128

3 Independent 32-Bit SRC1, SRC2, and DEST Buses

Bus

Control Unit

80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

2.2

Burst Bus

A 32-bit high-performance Bus Controller Unit (BCU) interfaces the 80960Jx to external memory
and peripherals. The BCU fetches instructions and transfers data at the rate of up to four 32-bit
words per six clock cycles. The external address/data bus is multiplexed.

Users may configure the 80960Jx's bus controller to match an application's fundamental memory
organization. Physical bus width is register-programmed for up to eight regions. Byte ordering and
data caching are programmed through a group of logical memory templates and a defaults register.

The BCU's features include:

Multiplexed external bus to minimize pin count

32-, 16- and 8-bit bus widths to simplify I/O interfaces

External ready control for address-to-data, data-to-data and data-to-next-address wait state types

Support for big or little endian byte ordering to facilitate the porting of existing program code

Unaligned bus accesses performed transparently

Three-deep load/store queue to decouple the bus from the core

Upon reset, the 80960Jx conducts an internal self-test. Then, before executing its first instruction, it
performs an external bus confidence test by performing a checksum on the first words of the
initialization boot record (IBR).

The user may examine the contents of the caches by executing special cache control instructions.

2.3

Timer Unit

The timer unit (TU) contains two independent 32-bit timers that are capable of counting at several
clock rates and generating interrupts. Each is programmed by use of the TU registers. These
memory-mapped registers are addressable on 32-bit boundaries. The timers have a single-shot
mode and auto-reload capabilities for continuous operation. Each timer has an independent
interrupt request to the 80960Jx's interrupt controller. The TU can generate a fault when
unauthorized writes from user mode are detected. Clock prescaling is supported.

2.4

Priority Interrupt Controller

A programmable interrupt controller manages up to 240 external sources through an 8-bit external
interrupt port. Alternatively, the interrupt inputs may be configured for individual edge- or
level-triggered inputs. The interrupt unit (IU) also accepts interrupts from the two on-chip timer
channels and a single Non-Maskable Interrupt (NMI) pin. Interrupts are serviced according to their
priority levels relative to the current process priority.

Low interrupt latency is critical to many embedded applications. As part of its highly flexible
interrupt mechanism, the 80960Jx exploits several techniques to minimize latency:

Interrupt vectors and interrupt handler routines can be reserved on-chip

The interrupt stack can be placed in cacheable memory space

Interrupt microcode executes at two or three times the bus frequency for the 80960JD and
80960JT respectively

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

2.5

Instruction Set Summary

The 80960Jx adds several new instructions to the i960 core architecture. The new instructions are:

Conditional Move

Conditional Add

Conditional Subtract

Byte Swap

Halt

Cache Control

Interrupt Control

Table 1 identifies the instructions that the 80960Jx supports. Refer to the i960

Jx Microprocessor

Developer's Manual (272483) for a detailed description of each instruction.

2.6

Faults and Debugging

The 80960Jx employs a comprehensive fault model. The processor responds to faults by making
implicit calls to a fault handling routine. Specific information collected for each fault allows the
fault handler to diagnose exceptions and recover appropriately.

The processor also has built-in debug capabilities. In software, the 80960Jx may be configured to
detect as many as seven different trace event types. Alternatively, mark and fmark instructions
can generate trace events explicitly in the instruction stream. Hardware breakpoint registers are
also available to trap on execution and data addresses.

2.7

Low Power Operation

Intel fabricates the 80960Jx using an advanced sub-micron manufacturing process. The processor's
sub-micron topology provides the circuit density for optimal cache size and high operating speeds
while dissipating modest power. The processor also uses dynamic power management to turn off
clocks to unused circuits.

Users may program the 80960Jx to enter Halt mode for maximum power savings. In Halt mode,
the processor core stops completely while the integrated peripherals continue to function, reducing
overall power requirements up to 90 percent. Processor execution resumes from internally or
externally generated interrupts.

80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

2.8

Test Features

The 80960Jx incorporates numerous features which enhance the user's ability to test both the
processor and the system to which it is attached. These features include ONCE (On-Circuit
Emulation) mode and Boundary Scan (JTAG).

The 80960Jx provides testability features compatible with IEEE Standard Test Access Port and
Boundary Scan Architecture (IEEE Std. 1149.1).

One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins (ONCE
mode). ONCE mode can also be initiated at reset without using the boundary scan mechanism.

ONCE mode is useful for board-level testing. This feature allows a mounted 80960Jx to
electrically "remove" itself from a circuit board. This allows for system-level testing where a
remote tester -- such as an in-circuit emulator -- can exercise the processor system.

The provided test logic does not interfere with component or circuit board behavior and ensures
that components function correctly, connections between various components are correct, and
various components interact correctly on the printed circuit board.

The JTAG Boundary Scan feature is an attractive alternative to conventional "bed-of-nails" testing.
It can examine connections which might otherwise be inaccessible to a test system.

2.9

Memory-Mapped Control Registers

The 80960Jx, though compliant with i960 series processor core, has the added advantage of
memory-mapped, internal control registers not found on the i960 Kx, Sx or Cx processors. These
give software the interface to easily read and modify internal control registers.

Each of these registers is accessed as a memory-mapped, 32-bit register. Access is accomplished
through regular memory-format instructions. The processor ensures that these accesses do not
generate external bus cycles.

2.10

Data Types and Memory Addressing Modes

As with all i960 family processors, the 80960Jx instruction set supports several data types and formats:

Bit

Bit fields

Integer (8-, 16-, 32-, 64-bit)

Ordinal (8-, 16-, 32-, 64-bit unsigned integers)

Triple word (96 bits)

Quad word (128 bits)

The 80960Jx provides a full set of addressing modes for C and assembly programming:

Two Absolute modes

Five Register Indirect modes

Index with displacement

IP with displacement

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

Table 1.

80960Jx Instruction Set

Data Movement

Arithmetic

Logical

Bit, Bit Field and Byte

Load

Store

Move

*Conditional Select

Load Address

Add

Subtract

Multiply

Divide

Remainder

Modulo

Shift

Extended Shift

Extended Multiply

Extended Divide

Add with Carry

Subtract with Carry

*Conditional Add

*Conditional Subtract

Rotate

And

Not And

And Not

Exclusive Or

Not Or

Or Not

Nor

Exclusive Nor

Not

Nand

Set Bit

Clear Bit

Not Bit

Alter Bit

Scan For Bit

Span Over Bit

Extract

Modify

Scan Byte for Equal

*Byte Swap

Comparison

Branch

Call/Return

Fault

Compare

Conditional Compare

Compare and Increment

Compare and Decrement

Test Condition Code

Check Bit

Unconditional Branch

Conditional Branch

Compare and Branch

Call

Call Extended

Call System

Return

Branch and Link

Conditional Fault

Synchronize Faults

Debug

Processor Management

Atomic

Modify Trace Controls

Mark

Force Mark

Flush Local Registers

Modify Arithmetic
Controls

Modify Process Controls

*Halt

System Control

*Cache Control

*Interrupt Control

Atomic Add

Atomic Modify

Asterisk (*) denotes new 80960Jx instructions unavailable on 80960CA/CF, 80960KA/KB and 80960SA/SB implementations.

80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

3.0

Package Information

The 80960Jx is offered with four speeds and three package types. The 132-pin Pin Grid Array
(PGA) device is specified for operation at V

= 3.3 V ± 0.15 V over a case temperature range of

0° to 100°C:

A80960JT-100 (100 MHz core, 33 MHz bus)

A80960JT-75 (75 MHz core, 25 MHz bus)

A80960JD-66 (66 MHz core, 33 MHz bus)

A80960JD-50 (50 MHz core, 25 MHz bus)

A80960JD-40 (40 MHz core, 20 MHz bus)

A80960JD-33 (33 MHz core, 16 MHz bus)

A80960JA/JF-33 (33 MHz)

A80960JA/JF-25 (25 MHz)

A80960JA/JF-16 (16 MHz)

The 132-pin Plastic Quad Flatpack (PQFP) devices are specified for operation at
V

= 3.3 V ± 0.15 V over a case temperature range of 0° to 100°C:

NG80960JT-100 (100 MHz core, 33 MHz bus)

NG80960JT-75 (75 MHz core, 25 MHz bus)

NG80960JD-66 (66 MHz core, 33 MHz bus)

NG80960JD-50 (50 MHz core, 25 MHz bus)

NG80960JD-40 (40 MHz core, 20 MHz bus)

NG80960JD-33 (33 MHz core, 16 MHz bus)

NG80960JA/JF-33 (33 MHz)

NG80960JA/JF-25 (25 MHz)

NG80960JA/JF-16 (16 MHz)

An extended temperature 132-pin Plastic Quad Flatpack (PQFP) device is specified for operation
at V

= 3.3 V ± 0.15 V over a case temperature range of -40° to 100°C:

TG80960JA-25 (25 MHz)

80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

3.1

Pin Descriptions

This section describes the pins for the 80960Jx in the 132-pin ceramic Pin Grid Array (PGA)
package, 132-lead Plastic Quad Flatpack Package (PQFP) and 196-ball Mini Plastic Ball Grid
Array (MPBGA).

Section 3.1.1, "Functional Pin Definitions", describes pin function; Section 3.1.2, "80960Jx
132-Lead PGA Pinout", Section 3.1.3, "80960Jx 132-Lead PQFP Pinout" and Section 3.1.4,
"80960Jx 196-Ball MPBGA Pinout", define the signal and pin locations for the supported package
types.

3.1.1

Functional Pin Definitions

Table 2 presents the legend for interpreting the pin descriptions which follow. Pins associated with
the bus interface are described in Table 3. Pins associated with basic control and test functions are
described in Table 4. Pins associated with the Interrupt Unit are described in Table 5.

Table 2.

Pin Description Nomenclature

Symbol

Description

Input pin only.

Output pin only.

I/O

Pin can be either an input or output.

Pin must be connected as described.

Synchronous. Inputs must meet setup and hold times relative to CLKIN for proper operation.

S(E) Edge sensitive input
S(L) Level sensitive input

A (...)

Asynchronous. Inputs may be asynchronous relative to CLKIN.

A(E) Edge sensitive input
A(L) Level sensitive input

R (...)

While the processor's RESET pin is asserted, the pin:

R(1) is driven to V

R(0) is driven to V

R(Q) is a valid output
R(X) is driven to unknown state
R(H) is pulled up to V

H (...)

While the processor is in the hold state, the pin:

H(1) is driven to V

H(0) is driven to V

H(Q) Maintains previous state or continues to be a valid output
H(Z) Floats

P (...)

While the processor is halted, the pin:

P(1) is driven to V

P(0) is driven to V

P(Q) Maintains previous state or continues to be a valid output

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

Table 3.

Pin Description -- External Bus Signals (Sheet 1 of 3)

NAME

TYPE

DESCRIPTION

AD31:0

I/O

S(L)

R(X)
H(Z)
P(Q)

ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-bit data
to and from memory. During an address (

) cycle, bits 31:2 contain a physical word

address (bits 0-1 indicate SIZE; see below). During a data (T

) cycle, read or write

data is present on one or more contiguous bytes, comprising AD31:24, AD23:16,
AD15:8 and AD7:0. During write operations, unused pins are driven to determinate
values.

SIZE, which comprises bits 0-1 of the AD lines during a

cycle, specifies the

number of data transfers during the bus transaction.

AD1

AD0

Bus Transfers

0 1

Transfer

Transfers

0 3

Transfers

1 4

Transfers

When the processor enters Halt mode, if the previous bus operation was a:

write -- AD31:2 are driven with the last data value on the AD bus.

read -- AD31:4 are driven with the last address value on the AD bus; AD3:2 are
driven with the value of A3:2 from the last data cycle.

Typically, AD1:0 reflect the SIZE information of the last bus transaction (either
instruction fetch or load/store) that was executed before entering Halt mode.

ALE

R(0)
H(Z)
P(0)

ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is
asserted during a

cycle and deasserted before the beginning of the T

state. It is

active HIGH and floats to a high impedance state during a hold cycle (T

ALE

R(1)
H(Z)
P(1)

ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is the
inverted version of ALE. This signal gives the 80960Jx a high degree of compatibility
with existing 80960Kx systems.

ADS

R(1)
H(Z)
P(1)

ADDRESS STROBE indicates a valid address and the start of a new bus access.
The processor asserts ADS for the entire

cycle. External bus control logic typically

samples ADS at the end of the cycle.

A3:2

R(X)
H(Z)
P(Q)

ADDRESS3:2 comprise a partial demultiplexed address bus.

32-bit memory accesses:

the processor asserts address bits A3:2 during

. The

partial word address increments with each assertion of RDYRCV during a burst.

16-bit memory accesses:

the processor asserts address bits A3:1 during

with A1

driven on the BE1 pin. The partial short word address increments with each
assertion of RDYRCV during a burst.

8-bit memory accesses:

the processor asserts address bits A3:0 during

, with A1:0

driven on BE1:0. The partial byte address increments with each assertion of
RDYRCV during a burst.

80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

BE3:0

R(1)
H(Z)
P(1)

BYTE ENABLES select which of up to four data bytes on the bus participate in the
current bus access. Byte enable encoding is dependent on the bus width of the
memory region accessed:

32-bit bus:

BE3 enables data on AD31:24
BE2 enables data on AD23:16
BE1 enables data on AD15:8
BE0 enables data on AD7:0

16-bit bus:

BE3 becomes Byte High Enable (enables data on AD15:8)
BE2 is not used (state is high)
BE1 becomes Address Bit 1 (A1)
BE0 becomes Byte Low Enable (enables data on AD7:0)

8-bit bus:

BE3 is not used (state is high)
BE2 is not used (state is high)
BE1 becomes Address Bit 1 (A1)
BE0 becomes Address Bit 0 (A0)

The processor asserts byte enables, byte high enable and byte low enable during

Since unaligned bus requests are split into separate bus transactions, these signals
do not toggle during a burst. They remain active through the last T

cycle.

For accesses to 8- and 16-bit memory, the processor asserts the address bits in
conjunction with A3:2 described above.

WIDTH/

HLTD1:0

R(0)
H(Z)
P(1)

WIDTH/HALTED signals denote the physical memory attributes for a bus
transaction:

WIDTH/HLTD1 WIDTH/HLTD0

8 Bits Wide

16 Bits Wide

32 Bits Wide

Processor Halted

The processor floats the WIDTH/HLTD pins whenever it relinquishes the bus in
response to a HOLD request, regardless of prior operating state.

D/C

R(X)
H(Z)
P(Q)

DATA/CODE indicates that a bus access is a data access (1) or an instruction
access (0). D/C has the same timing as W/R.

0 = instruction access
1 = data access

W/R

R(0)
H(Z)

P(Q)

WRITE/READ specifies, during a

cycle, whether the operation is a write (1) or

read (0). It is latched on-chip and remains valid during T

cycles.

0 = read
1 = write

DT/R

R(0)
H(Z)

P(Q)

DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the
address/data bus. It is low during T

and T

cycles for a read; it is high during

and T

cycles for a write. DT/R never changes state when DEN is asserted.

0 = receive
1 = transmit

DEN

R(1)
H(Z)
P(1)

DATA ENABLE indicates data transfer cycles during a bus access. DEN is asserted
at the start of the first data cycle in a bus access and deasserted at the end of the
last data cycle. DEN is used with DT/R to provide control for data transceivers
connected to the data bus.

0 = data cycle
1 = not data cycle

Table 3.

Pin Description -- External Bus Signals (Sheet 2 of 3)

NAME

TYPE

DESCRIPTION

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

BLAST

R(1)
H(Z)
P(1)

BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the
last data transfer of burst and non-burst accesses. BLAST remains active as long as
wait states are inserted via the RDYRCV pin. BLAST becomes inactive after the final
data transfer in a bus cycle.

0 = last data transfer
1 = not last data transfer

RDYRCV

S(L)

READY/RECOVER indicates that data on AD lines can be sampled or removed. If
RDYRCV is not asserted during a T

cycle, the T

cycle is extended to the next cycle

by inserting a wait state (T

0 = sample data
1 = don't sample data

The RDYRCV pin has another function during the recovery (T

) state. The processor

continues to insert additional recovery states until it samples the pin HIGH. This
function gives slow external devices more time to float their buffers before the
processor begins to drive address again.

0 = insert wait states
1 = recovery complete

LOCK/

ONCE

I/O

S(L)

R(H)

H(Z)

P(1)

BUS LOCK indicates that an atomic read-modify-write operation is in progress. The
LOCK output is asserted in the first clock of an atomic operation and deasserted in
the last data transfer of the sequence. The processor does not grant HOLDA while it
is asserting LOCK. This prevents external agents from accessing memory involved
in semaphore operations.

0 = Atomic read-modify-write in progress
1 = Atomic read-modify-write not in progress

ONCE MODE: The processor samples the ONCE input during reset. If it is asserted
LOW at the end of reset, the processor enters ONCE mode. In ONCE mode, the
processor stops all clocks and floats all output pins. The pin has a weak internal
pullup which is active during reset to ensure normal operation when the pin is left
unconnected.

0 = ONCE mode enabled
1 = ONCE mode not enabled

HOLD

S(L)

HOLD: A request from an external bus master to acquire the bus. When the
processor receives HOLD and grants bus control to another master, it asserts
HOLDA, floats the address/data and control lines and enters the T

state. When

HOLD is deasserted, the processor deasserts HOLDA and enters either the T

state, resuming control of the address/data and control lines.

0 = no hold request
1 = hold request

HOLDA

R(Q)

H(1)

P(Q)

HOLD ACKNOWLEDGE indicates to an external bus master that the processor has
relinquished control of the bus. The processor can grant HOLD requests and enter
the T

state during reset and while halted as well as during regular operation.

0 = hold not acknowledged
1 = hold acknowledged

BSTAT

R(0)

H(Q)

P(0)

BUS STATUS indicates that the processor may soon stall unless it has sufficient
access to the bus; see

i960

Jx Microprocessor Developer's Manual

(272483).

Arbitration logic can examine this signal to determine when an external bus master
should acquire/relinquish the bus.

0 = no potential stall
1 = potential stall

Table 3.

Pin Description -- External Bus Signals (Sheet 3 of 3)

NAME

TYPE

DESCRIPTION

80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

Table 4.

Pin Description -- Processor Control Signals, Test Signals and Power

NAME

TYPE

DESCRIPTION

CLKIN

CLOCK INPUT provides the processor's fundamental time base; both the processor
core and the external bus run at the CLKIN rate. All input and output timings are
specified relative to a rising CLKIN edge.

RESET

A(L)

RESET initializes the processor and clears its internal logic. During reset, the
processor places the address/data bus and control output pins in their idle (inactive)
states.

During reset, the input pins are ignored with the exception of LOCK/ONCE, STEST
and HOLD.

The RESET pin has an internal synchronizer. To ensure predictable processor
initialization during power up, RESET must be asserted a minimum of 10,000 CLKIN
cycles with V

and CLKIN stable. On a warm reset, RESET should be asserted for

a minimum of 15 cycles.

STEST

S(L)

SELF TEST enables or disables the processor's internal self-test feature at
initialization. STEST is examined at the end of reset. When STEST is asserted, the
processor performs its internal self-test and the external bus confidence test. When
STEST is deasserted, the processor performs only the external bus confidence test.

0 = self test disabled
1 = self test enabled

FAIL

R(0)

H(Q)

P(1)

FAIL indicates a failure of the processor's built-in self-test performed during
initialization. FAIL is asserted immediately upon reset and toggles during self-test to
indicate the status of individual tests:

When self-test passes, the processor deasserts FAIL and begins operation from
user code.

When self-test fails, the processor asserts FAIL and then stops executing.

0 = self test failed
1 = self test passed

TCK

TEST CLOCK is a CPU input which provides the clocking function for IEEE 1149.1
Boundary Scan Testing (JTAG). State information and data are clocked into the
processor on the rising edge; data is clocked out of the processor on the falling edge.

TDI

S(L)

TEST DATA INPUT is the serial input pin for JTAG. TDI is sampled on the rising
edge of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port.

TDO

R(Q)

HQ)

P(Q)

TEST DATA OUTPUT is the serial output pin for JTAG. TDO is driven on the falling
edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At
other times, TDO floats. TDO does not float during ONCE mode.

TRST

A(L)

TEST RESET asynchronously resets the Test Access Port (TAP) controller function
of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan
feature, connect a pulldown resistor between this pin and V

. If TAP is not used,

this pin must be connected to V

; however, no resistor is required. See Section 4.3,

"Connection Recommendations" on page 40.

TMS

S(L)

TEST MODE SELECT is sampled at the rising edge of TCK to select the operation of
the test logic for IEEE 1149.1 Boundary Scan testing.

POWER pins intended for external connection to a V

board plane.

VCCPLL

PLL POWER is a separate V

supply pin for the phase lock loop clock generator. It

is intended for external connection to the V

board plane. In noisy environments,

add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects
on timing relationships.

VCC5

5 V REFERENCE VOLTAGE input is the reference voltage for the 5 V-tolerant I/O
buffers. This signal should be connected to +5 V for use with inputs which exceed
3.3 V. If all inputs are from 3.3 V components, this pin should be connected to 3.3 V.

GROUND pins intended for external connection to a V

board plane.

NO CONNECT pins. Do not make any system connections to these pins.

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

Table 5.

Pin Description -- Interrupt Unit Signals

NAME

TYPE

DESCRIPTION

XINT7:0

A(E/L)

EXTERNAL INTERRUPT pins are used to request interrupt service. The XINT7:0
pins can be configured in three modes:

Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated inputs
can be programmed to be level (low) or edge (falling) sensitive.

Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt pins
are level sensitive in this mode.

Mixed Mode:

The XINT7:5 pins act as dedicated sources and the XINT4:0 pins act

as the five most significant bits of a vectored source. The least significant bits of the
vectored source are set to 010

internally.

Unused external interrupt pins should be connected to V

NMI

A(E)

NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.
NMI is the highest priority interrupt source and is falling edge-triggered. If NMI is
unused, it should be connected to V

80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

3.1.2

80960Jx 132-Lead PGA Pinout

Figure 3.

132-Lead Pin Grid Array Bottom View - Pins Facing Up

AD6

AD11

AD13

AD18

AD19

AD22

AD25

AD3

AD7

AD10

AD20

AD24

AD26

AD27

AD0

AD4

AD8

AD9

AD12

AD14

AD15

AD16

AD17

AD21

AD23

AD29

AD30

AD28

BE3

BE2

AD31

BE1

BE0

ALE

BSTAT

DT/R

AD1

CLKIN

VCCPLL

RDYRCV

RESET

AD5

AD2

TDI

XINT0

WIDTH/

ADS

XINT1

TMS

XINT2

STEST

TRST

HOLD

FAIL

VCC5

BLAST

LOCK/ HOLDA

TCK

XINT3

XINT5

XINT7

NMI

ALE

XINT6

TDO

WIDTH/

D/C

W/R

XINT4

DEN

HLTD1

HLTD0

ONCE

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

Figure 4.

132-Lead Pin Grid Array Top View - Pins Facing Down

AD6

AD11 AD13

AD18

AD19 AD22

AD25

AD3

AD7

AD10

AD20

AD24 AD26

AD27

AD0

AD4

AD8

AD9

AD12

AD14 AD15

AD16

AD17

AD21 AD23

AD29

AD30

AD28

BE3

BE2

AD31

BE1

BE0

ALE

BSTAT V

DT/R

AD1

CLKIN

VCCPLL

RDYRCV

RESET

AD5

AD2

TDI

XINT0

WIDTH/

ADS

XINT1

TMS

XINT2

STEST TRST

HOLD

FAIL

VCC5

BLAST

LOCK/

HOLDA

TCK XINT3

XINT5 XINT7

NMI

ALE

XINT6

TDO

WIDTH/

D/C

W/R

XINT4

DEN

HLTD1

HLTD0

ONCE

© 19xx

A80960Jx

XXXXXXXX SS

80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

Table 6.

132-Lead PGA Pinout -- In Signal Order

Signal

Pin

Signal

Pin

Signal

Pin

Signal

Pin

AD31

TDO

ADS

TMS

A14

AD0

M14

ALE

TRST

C12

D13

AD1

L13

ALE

AD2

K12

BE0

E13

AD3

N14

BE1

AD4

M13

BE2

F13

AD5

L12

BE3

AD6

P14

BLAST

D14

G13

AD7

N13

BSTAT

AD8

M12

CLKIN

H14

E14

H13

AD9

M11

D/C

AD10

N12

DEN

F14

J13

AD11

P13

DT/R

AD12

M10

FAIL

G14

K13

AD13

P12

HOLD

AD14

HOLDA

AD15

LOCK/ONCE

J14

AD16

AD17

K14

AD18

L14

N10

AD19

B14

N11

AD20

W/R

AD21

C14

WIDTH/HLTD0

AD22

G12

WIDTH/HLTD1

AD23

J12

XINT0

C11

AD24

P10

XINT1

C10

AD25

NMI

A10

P11

XINT2

A13

AD26

RDYRCV

F12

VCCPLL

H12

XINT3

B12

AD27

RESET

E12

VCC5

XINT4

B11

AD28

STEST

C13

XINT5

A12

AD29

TCK

B13

XINT6

B10

AD30

TDI

D12

XINT7

A11

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

Table 7.

132-Lead PGA Pinout -- In Pin Order

Pin

Signal

Pin

Signal

Pin

Signal

Pin

Signal

ADS

FAIL

M10

AD12

WIDTH/HLTD1

VCC5

M11

AD9

ALE

BE0

M12

AD8

HOLD

H12

VCCPLL

M13

AD4

C10

XINT1

H13

M14

AD0

C11

XINT0

H14

CLKIN

AD27

C12

TRST

AD26

C13

STEST

AD24

C14

BE1

AD20

A10

NMI

J12

A11

XINT7

J13

A12

XINT5

DT/R

J14

A13

XINT2

D12

TDI

A14

TMS

D13

W/R

D14

AD31

N10

D/C

K12

AD2

N11

WIDTH/HLTD0

K13

N12

AD10

TDO

DEN

K14

N13

AD7

E12

RESET

BE2

N14

AD3

E13

BE3

AD25

E14

AD28

AD22

L12

AD5

AD19

L13

AD1

AD18

B10

XINT6

BSTAT

L14

B11

XINT4

F12

RDYRCV

AD30

B12

XINT3

F13

AD29

B13

TCK

F14

B14

AD23

LOCK/ONCE

AD21

P10

HOLDA

ALE

AD17

P11

BLAST

G12

AD16

P12

AD13

G13

AD15

P13

AD11

G14

AD14

P14

AD6

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

3.1.3

80960Jx 132-Lead PQFP Pinout

Figure 5.

132-Lead PQFP - Top View

(I/O)

(C
or

VCCP

(C
L

)

RDYRCV

(C
or

)

RESE

ST
E

(I/O)

TD
I

(I/O)

AD2

(

I/O)

(I/O)

AD2

AD3

(

ore)

(C
or

(

I/O)

(I/O)

BE
3

BE
2

BE
1

BE
0

BS
T

LOC

/ONCE

(

I/O)

(I/O)

(

ore)

(C
or

AL
E

HOL

DEN

DT
/R

(

I/O)

(I/O)

(

ore)

(C
or

W/
R

ADS

D/C

BL
A

10
0

101

102

103

104

105

106

107

108

109

11
0

111

11
2

11
3

11
4

11
5

11
6

11
7

11
8

11
9

120

121

122

123

124

125

126

127

128

129

130

131

132

2
3

4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

23
24
25
26
27
28
29

30
31
32
33

99
98

96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78

77
76
75
74
73
72
71

70
69
68
67

TRST

TCK

TMS

HOLD

XINT0
XINT1
XINT2

XINT3

(I/O)

XINT4
XINT5
XINT6

XINT7

NMI

(Core)

NC
NC

VCC5

NC
NC

FAIL

ALE

TDO

(I/O)

WIDTH/HLTD1

(Core)

WIDTH/HLTD0

AD9

(I/O)

AD10

(I/O)

AD11

(I/O)

(Core)

AD12

AD13
AD14
AD15

(I/O)

AD16
AD17
AD18

AD19

(I/O)

AD22

AD25

AD21

AD20

AD24

AD26

AD23

(I/O)

(Core)

(I/O)

(Core)

(I/O)

(I/O

)

CL
K

I
N

(C
L

)

(

ore)

XXXXXXXX SS

© 19xx

i960

NG80960Jx

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

Table 8.

132-Lead PQFP Pinout -- In Signal Order

Signal

Pin

Signal

Pin

Signal

Pin

Signal

Pin

AD31

ALE

(Core)

124

AD30

ADS

(Core)

(I/O)

AD29

(Core)

(I/O)

AD28

(Core)

(I/O)

AD27

BE3

(Core)

113

(I/O)

AD26

BE2

(Core)

115

(I/O)

AD25

BE1

(Core)

123

(I/O)

AD24

BE0

(I/O)

AD23

WIDTH/HLTD1

(I/O)

AD22

WIDTH/HLTD0

(I/O)

AD21

D/C

(I/O)

AD20

W/R

(I/O)

AD19

DT/R

(I/O)

106

AD18

DEN

(I/O)

112

AD17

BLAST

(I/O)

131

AD16

RDYRCV

132

(I/O)

AD15

LOCK/ONCE

(I/O)

AD14

HOLD

(I/O)

AD13

HOLDA

(I/O)

105

AD12

BSTAT

(I/O)

111

AD11

CLKIN

117

(I/O)

129

121

AD10

RESET

125

VCCPLL

119

122

AD9

STEST

128

VCC5

126

AD8

100

FAIL

(CLK)

118

127

AD7

101

TCK

(Core)

XINT7

AD6

102

TDI

130

(Core)

XINT6

AD5

103

TDO

(Core)

XINT5

AD4

104

TRST

(Core)

XINT4

AD3

107

TMS

(Core)

XINT3

AD2

108

(CLK)

120

(Core)

XINT2

AD1

109

(Core)

XINT1

AD0

110

(Core)

114

XINT0

ALE

(Core)

116

NMI

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

Table 9.

132-Lead PQFP Pinout -- In Pin Order

Pin

Signal

Pin

Signal

Pin

Signal

Pin

Signal

TRST

BLAST

100

AD8

TCK

D/C

AD26

101

AD7

TMS

ADS

AD25

102

AD6

HOLD

W/R

AD24

103

AD5

XINT0

(Core)

(I/O)

104

AD4

XINT1

(Core)

(I/O)

105

(I/O)

XINT2

(I/O)

(Core)

106

(I/O)

XINT3

(I/O)

(Core)

107

AD3

(I/O)

DT/R

AD23

108

AD2

(I/O)

DEN

AD22

109

AD1

XINT4

HOLDA

AD21

110

AD0

XINT5

ALE

AD20

111

(I/O)

XINT6

(Core)

(I/O)

112

(I/O)

XINT7

(Core)

(I/O)

113

(Core)

NMI

(I/O)

AD19

114

(Core)

(I/O)

AD18

115

(Core)

LOCK/ONCE

AD17

116

(Core)

BSTAT

AD16

117

CLKIN

BE0

(I/O)

118

(CLK)

VCC5

BE1

(I/O)

119

VCCPLL

BE2

AD15

120

CC (CLK)

BE3

AD14

121

FAIL

(I/O)

AD13

122

ALE

(I/O)

AD12

123

(Core)

TDO

(Core)

124

(Core)

(I/O)

(Core)

125

RESET

(I/O)

AD31

(I/O)

126

WIDTH/HLTD1

AD30

(I/O)

127

(Core)

AD29

AD11

128

STEST

(Core)

AD28

AD10

129

(I/O)

WIDTH/HLTD0

(I/O)

130

TDI

(I/O)

131

(I/O)

AD27

AD9

132

RDYRCV

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

3.1.4

80960Jx 196-Ball MPBGA Pinout

Figure 6.

196-Ball Mini Plastic Ball Grid Array Bottom View - Balls Facing Up

AD8

AD13

AD15

AD18

AD22

AD28

AD4

AD7

AD9

AD10

AD12

AD14

AD17

AD20

AD23

AD29

AD27

AD30

AD2

AD6

AD11

AD16

AD19

AD21

AD24

AD25

AD26

AD31

BE3

BE1

BSTAT

BE0

LOCK/

ALE

DEN

HOLDA

AD1

AD0

VCCPLL

CLKIN

RESET

TDI

STEST

RDYRCV

AD5

XINT0

HOLD

ADS

XINT2

TCK

TRST

TMS

VCC5

ALE

DT/R

XINT3

XINT1

XINT5

XINT7

NMI

FAIL

WIDTH1

WIDTH0

BLAST

XINT4

TDO

D/C

W/R

XINT6

BE2

AD3

ONCE

80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

Figure 7.

196-Ball Mini Plastic Ball Grid Array Top View - Balls Facing Down

AD8

AD13

AD15

AD18

AD22

AD28

AD4

AD7

AD9

AD10

AD12

AD14

AD17

AD20

AD23

AD29

AD27

AD30

AD2

AD6

AD11

AD16

AD19

AD21

AD24

AD25

AD26

AD31

BE3

BE1

BSTAT

BE0

LOCK/

ALE

DEN

HOLDA

AD1

AD0

VCCPLL V

CLKIN

RESET

TDI

STEST

RDYRCV NC

AD5

XINT0

HOLD

ADS

XINT2

TCK

TRST

TMS

VCC5

ALE

DT/R

XINT3 XINT1

XINT5 XINT7

NMI

FAIL WIDTH1 WIDTH0 V

BLAST

XINT4

TDO

D/C

W/R

XINT6

BE2

AD3

ONCE

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

Table 10.

196-Ball MPBGA Pinout -- In Signal Order (Sheet 1 of 2)

Signal

Pin

Signal

Pin

Signal

Pin

Signal

Pin

BE0

BE1

AD0

D13

BE2

K13

AD1

D14

BE3

AD2

C14

BLAST

N10

AD3

D11

BSTAT

AD4

B14

CLKIN

G13

AD5

D12

DEN

AD6

C13

D/C

P14

AD7

B13

DT/R

NMI

P10

P13

AD8

A13

FAIL

RDYRCV

L14

VCCPLL

F14

AD9

B12

HOLD

N14

RESET

J14

AD10

B11

HOLDA

STEST

K14

AD11

C12

LOCK/ONCE

TCK

M14

AD12

B10

TDI

J12

AD13

A11

TDO

AD14

A14

TMS

M12

AD15

A10

TRST

M13

D10

AD16

VCC5

AD17

AD18

AD19

AD20

AD21

A12

AD22

E10

AD23

E11

AD24

C10

AD25

C11

AD26

G12

AD27

G14

E12

AD28

H12

E13

AD29

H14

E14

AD30

J13

F10

AD31

K12

F12

F11

ADS

L12

F13

ALE

L13

ALE

H13

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

Table 11.

196-Ball MPBGA Pinout -- In Pin Order (Sheet 1 of 2)

Pin

Signal

Pin

Signal

Pin

Signal

Pin

Signal

C11

BSTAT

AD28

C12

AD11

C13

AD6

C14

AD2

F10

F11

AD22

F12

F13

AD18

F14

VCCPLL

J10

J11

A10

AD15

J12

TDI

A11

AD13

J13

A12

J14

RESET

A13

AD8

ALE

A14

D10

LOCK/ONCE

D11

AD3

AD30

D12

AD5

AD27

D13

AD0

AD29

D14

AD1

G10

G11

AD23

G12

AD20

G13

CLKIN

AD17

G14

K10

AD14

BE1

K11

B10

AD12

BE2

K12

B11

AD10

BE3

K13

B12

AD9

K14

STEST

B13

AD7

HOLDA

B14

AD4

E10

DEN

E11

AD31

E12

E13

AD26

E14

H10

AD25

H11

AD24

H12

AD21

H13

AD19

H14

L10

AD16

L11

C10

BE0

L12

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

3.2

Package Thermal Specifications

The 80960Jx is specified for operation when T

(case temperature) is within the range of 0°C to

100°C for PGA, MPBGA and PQFP packages. An extended temperature device is also available in
a PQFP package with T

-40°C to 100°C. Case temperature may be measured in any environment

to determine whether the 80960Jx is within its specified operating range. The case temperature
should be measured at the center of the top surface, opposite the pins.

is the thermal resistance from case to ambient. Use the following equation to calculate T

, the

maximum ambient temperature to conform to a particular case temperature:

= T

- P (

)

Junction temperature (T

) is commonly used in reliability calculations. T

can be calculated from

(thermal resistance from junction to case) using the following equation:

= T

+ P (

)

Similarly, if T

is known, the corresponding case temperature (T

) can be calculated as follows:

= T

+ P (

)

Compute P by multiplying I

from Table 22 and V

. Values for

and

are given in

Table 12 for the PGA package, Table 13 for the MPBGA package, and Table 14 for the PQFP
package. For high speed operation, the processor's

may be significantly reduced by adding a

heatsink and/or by increasing airflow.

Tables 15, 16, and 17 show the maximum ambient temperature (T

) permitted without exceeding

for the PGA, MPBGA, and PQFP packages. The values are based on typical I

and V

+3.3 V, with a T

CASE

of +100°C.

L13

M10

XINT2

TDO

L14

RDYRCV

M11

XINT0

WIDTH0

DT/R

M12

TMS

XINT4

WIDTH1

M13

TRST

N10

FAIL

M14

TCK

N11

XINT6

W/R

N12

XINT1

D/C

N13

XINT3

P10

NMI

N14

HOLD

P11

XINT7

ALE

P12

XINT5

VCC5

ADS

P13

BLAST

P14

Table 11.

196-Ball MPBGA Pinout -- In Pin Order (Sheet 2 of 2)

Pin

Signal

Pin

Signal

Pin

Signal

Pin

Signal

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

Table 12.

132-Lead PGA Package Thermal Characteristics

Thermal Resistance -- °C/Watt

Parameter

Airflow -- ft./min (m/sec)

(0)

200

(1.01)

400

(2.03)

600

(3.04)

800

(4.06)

1000

(5.08)

(Junction-to-Case)

0.7

(Case-to-Ambient) (No Heatsink)

(Case-to-Ambient) (Omnidirectional Heatsink)

(Case-to-Ambient) (Unidirectional Heatsink)

NOTES:

1. This table applies to a PGA device plugged into a socket or soldered directly into a board.
2.

J-CAP

= 5.6°C/W (approximate) (no heatsink)

J-PIN

= 6.4°C/W (inner pins) (approximate) (no heatsink)

J-PIN

= 6.2°C/W (outer pins) (approximate) (no heatsink)

J-CAP

= 3°C/W (approximate) (with heatsink)

J-PIN

= 3.3°C/W (inner pins) (approximate) (with heatsink)

J-PIN

= 3.3°C/W (outer pins) (approximate) (with heatsink)

Table 13.

196-Ball MPBGA Package Thermal Characteristics

Thermal Resistance -- °C/Watt

Parameter

Airflow -- ft./min (m/sec)

(0)

200

(1.01)

400

(2.03)

600

(3.04)

800

(4.06)

1000

(5.08)

(Junction-to-Case)

TBD

(Case-to-Ambient) (No Heatsink)

TBD

(Case-to-Ambient) (Omnidirectional Heatsink)

TBD

(Case-to-Ambient) (Unidirectional Heatsink)

TBD

J-CAP

J-PIN

TBD

80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

Table 14.

132-Lead PQFP Package Thermal Characteristics

Thermal Resistance -- °C/Watt

Parameter

Airflow -- ft./min (m/sec)

(0)

(0.25)

100

(0.50)

200

(1.01)

400

(2.03)

600

(3.04)

800

(4.06)

(Junction-to-Case)

4.1

4.3

4.7

4.9

(Case-to-Ambient -No Heatsink)

NOTES:

1. This table applies to a PQFP device soldered directly into board.
2.

= 13°C/W (approx.)

= 13.5°C/W (approx.)

Table 15.

Maximum T

at Various Airflows in °C (80960JT)

Airflow-ft/min (m/sec)

CLKIN

(MHz)

(0)

200

(1.01)

400

(2.03)

600

(3.04)

800

(4.06)

1000

(5.07)

PQFP

Package

without Heatsink

33
25

62
71

73
79

76
82

81
86

85
88

88
91

PGA

Package

without Heatsink

33
25

58
68

68
75

76
82

80
84

81
86

83
87

with Omnidirectional

Heatsink

33
25

75
81

85
88

90
92

92
94

93
95

with Unidirectional

Heatsink

33
25

73
79

86
90

90
92

92
94

93
95

MPBGA

Package

without Heatsink

33
25

TBD
TBD

NOTES:

1. 0.248" high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing).
2. 0.250" high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

Table 16.

Maximum T

at Various Airflows in °C (80960JD)

Airflow-ft/min (m/sec)

CLKIN

(MHz)

(0)

200

(1.01)

400

(2.03)

600

(3.04)

800

(4.06)

1000

(5.07)

PQFP

Package

without Heatsink

33
25
20

16.67

61
70
75
79

73
79
82
86

76
82
85
87

81
86
88
90

85
88
90
92

86
90
91
93

PGA

Package

without Heatsink

33
25
20

16.67

58
68
73
78

68
75
79
83

76
82
85
87

80
84
87
89

81
86
88
90

83
87
89
91

with Omnidirectional

Heatsink

33
25
20

16.67

75
81
84
87

85
88
90
92

90
92
93
95

92
94
95
96

93
95
96
96

with Unidirectional

Heatsink

33
25
20

16.67

73
79
82
86

86
90
91
93

90
92
93
95

92
94
95
96

93
95
96
96

93
96
96
96

MPBGA

Package

without Heatsink

25
20

16.67

TBD
TBD
TBD

NOTES:

Table 17.

Maximum T

at Various Airflows in °C (80960JA/JF)

Airflow-ft/min (m/sec)

CLKIN

(MHz)

(0)

200

(1.01)

400

(2.03)

600

(3.04)

800

(4.06)

1000

(5.07)

PQFP

Package

For NG80960JA/JF

without Heatsink

33
25
16

79
84
89

86
89
92

87
90
93

90
92
95

92
94
96

93
94
96

For TG80960JA-25

without Heatsink

PGA

Package

without Heatsink

33
25
16

78
83
88

83
87
91

87
90
93

89
92
94

90
92
95

91
93
95

with Omnidirectional

Heatsink

33
25
16

87
90
93

92
94
96

95
96
97

96
97
98

with Unidirectional

Heatsink

33
25
16

86
89
92

93
94
96

95
96
97

96
97
98

MPBGA

Package

without Heatsink

33
25
16

TBD
TBD
TBD

NOTES:

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

4.0

Electrical Specifications

4.1

Absolute Maximum Ratings

Warning:

Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended
and extended exposure beyond the "Operating Conditions" may affect device reliability.

Note:

This document contains information on products in the sampling and initial production phases of
development. It is valid for the devices indicated in the revision history. The specifications within
this data sheet are subject to change without notice. Verify with your local Intel sales office that
you have the latest data sheet before finalizing a design.

4.2

Operating Conditions

Table 19 indicates the operating conditions for the 80960Jx.

Table 18.

Absolute Maximum Ratings

Parameter

Maximum Rating

Storage Temperature

C to +150

Case Temperature Under Bias

C to +110

Supply Voltage wrt. V

0.5 V to + 4.6 V

Voltage on VCC5 wrt. V

0.5 V to + 6.5 V

Voltage on Other Pins wrt. V

0.5 V to V

+ 0.5 V

Table 19.

80960Jx Operating Conditions

Symbol

Parameter

Min

Max

Units

Notes

Supply Voltage

3.15

3.45

VCC5

Input Protection Bias

3.15

5.5

(1)

CLKIN

Input Clock Frequency

80960JT-100
80960JT-75
80960JD-66
80960JD-50
80960JD-40
80960JD-33
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16

15
15
12
12
12
12
12
12
12

33.3

25
20

16.67

33.3

25
16

MHz

Operating Case Temperature

PGA, MPBGA, and PQFP
Extended temp PQFP (TG80960JA-25)

-40

100
100

°C

NOTE:

1. See Section 4.4, "VCC5 Pin Requirements (VDIFF)" on page 40.

80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

4.3

Connection Recommendations

For clean on-chip power distribution, V

and V

pins separately feed the device's functional units.

Power and ground connections must be made to all 80960Jx power and ground pins. On the circuit board,
every V

pin should connect to a power plane and every V

pin should connect to a ground plane. Place

liberal decoupling capacitance near the 80960Jx, since the processor can cause transient power surges.

Pay special attention to the Test Reset (TRST) pin. It is essential that the JTAG Boundary Scan Test Access
Port (TAP) controller initializes to a known state whether it will be used or not. If the JTAG Boundary Scan
function will be used, connect a pulldown resistor between the TRST pin and V

. If the JTAG Boundary

Scan function will not be used (even for board-level testing), connect the TRST pin to V

Do not connect the TDI, TDO, and TCK pins if the TAP Controller will not be used.

Note:

Pins identified as NC must not be connected in the system.

4.4

VCC5 Pin Requirements (VDIFF)

In 3.3 V only systems where the 80960Jx input pins are driven from 3.3 V logic, connect the VCC5

pin directly to the 3.3 V V

plane.

In mixed voltage systems where the processor is powered by 3.3 V and interfaces with 5 V
components, VCC5 must be connected to 5 V. This allows proper 5 V tolerant buffer operation,
and prevents damage to the input pins. The voltage differential between the 80960Jx VCC5 pin and
its 3.3 V V

pins must not exceed 2.25 V. If this requirement is not met, current flow through the

pin may exceed the value at which the processor is damaged. Instances when the voltage can
exceed 2.25 V is during power up or power down, where one source reaches its level faster than the
other, briefly causing an excess voltage differential. Another instance is during steady-state
operation, where the differential voltage of the regulator (provided a regulator is used) cannot be
maintained within 2.25 V. Two methods are possible to prevent this from happening:

Use a regulator that is designed to prevent the voltage differential from exceeding 2.25 V, or,

As shown in Figure 8, place a 100

resistor in series with the VCC5 pin to limit the current

through VCC5.

If the regulator cannot prevent the 2.25 V differential, the addition of the resistor is a simple and
reliable method for limiting current. The resistor can also prevent damage in the case of a power
failure, where the 5 V supply remains on and the 3.3 V supply goes to zero.

Figure 8.

VCC5 Current-Limiting Resistor

+5 V (±0.25 V)

VCC5 Pin

100

(±5%, 0.5 W)

Table 20.

VDIFF Parameters

Symbol

Parameter

Min

Max

Units

Notes

VDIFF

VCC5-V

Difference

2.25

VCC5 input should not exceed V

by more than 2.25 V

during power-up and power-down, or during
steady-state operation.

80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

4.6

DC Specifications

Table 21.

80960Jx DC Characteristics

Symbol

Parameter

Min

Typ

Max

Units

Notes

Input Low Voltage

-0.3

0.8

Input High Voltage

2.0

VCC5 + 0.3

Output Low Voltage

0.4

0.2

= 3 mA

= 100 µA

Output High Voltage

2.4

- 0.2

= -1 mA

= -200 µA

OLP

Output Ground Bounce

<0.8

(1,2)

Input Capacitance
PGA
PQFP
MPBGA

15
15
15

CLKIN

= f

MIN

(2)

OUT

I/O or Output Capacitance
PGA
PQFP
MPBGA

15
15
15

CLKIN

= f

MIN

(2)

CLK

CLKIN Capacitance
PGA
PQFP
MPBGA

15
15
15

CLKIN

= f

MIN

(2)

NOTES:

1. Typical is measured with V

= 3.3 V and temperature = 25 °C.

2. Not tested.

Table 22.

80960Jx I

Characteristics (Sheet 1 of 2)

Symbol

Parameter

Typ

Max

Units

Notes

LI1

Input Leakage Current for each pin
except TCK, TDI, TRST and TMS

± 1

µA

LI2

Input Leakage Current for TCK, TDI,
TRST and TMS

-140

-250

µA

= 0.45V (1)

Output Leakage Current

± 1

µA

0.4

OUT

Internal Pull-UP Resistance for
ONCE, TMS, TDI and TRST

Active

(Power Supply)

80960JT-100
80960JT-75
80960JD-66
80960JD-50
80960JD-40
80960JD-33
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16

600
450
580
447
367
310
320
260
194

(2,3)
(2,3)
(2,3)
(2,3)
(2,3)
(2,3)
(2,3)
(2,3)
(2,3)

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

Active

(Thermal)

80960JT-100
80960JT-75
80960JD-66
80960JD-50
80960JD-40
80960JD-33
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16

500
380
510
390
320
260
271
215
152

(2,4)
(2,4)
(2,4)
(2,4)
(2,4)
(2,4)
(2,4)
(2,4)
(2,4)

Test

(Power modes)

Reset mode

80960JT-100
80960JT-75
80960JD-66
80960JD-50
80960JD-40
80960JD-33
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16

Halt mode

80960JT-100
80960JT-75
80960JD-66
80960JD-50
80960JD-40
80960JD-33
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16

ONCE mode

450
400
475
425
345
300
250
200
150

50
40
50
40
34
34
31
26
21

(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)

(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)

(5)

CC5

Current on the

VCC5 Pin

80960JT-100
80960JT-75
80960JD-66
80960JD-50
80960JD-40
80960JD-33
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16

200

µA

(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)

NOTES:

1. These pins have internal pullup devices. Typical leakage current is not tested.
2. Measured with device operating and outputs loaded to the test condition in Figure 10 "AC Test Load" on

page 47.

3. I

Active (Power Supply) value is provided for selecting your system's power supply. It is measured using

one of the worst case instruction mixes with V

= 3.45 V. This parameter is characterized but not tested.

4. I

Active (Thermal) value is provided for your system's thermal management. Typical I

is measured with

=3.3 V and temperature = 25°C. This parameter is characterized but not tested.

5. I

Test (Power modes) refers to the I

values that are tested when the 80960JD is in Reset mode, Halt

mode or ONCE mode with V

= 3.45 V.

6. I

CC5

is tested at V

= 3.3 V, VCC5 = 5.25 V.

Table 22.

80960Jx I

Characteristics (Sheet 2 of 2)

Symbol

Parameter

Typ

Max

Units

Notes

80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

4.7

AC Specifications

The 80960Jx AC timings are based upon device characterization.

Table 23.

80960Jx AC Characteristics (Sheet 1 of 3)

Symbol

Parameter

Min

Max

Unit

Notes

INPUT CLOCK TIMINGS

CLKIN Frequency

80960JT-100
80960JT-75
80960JD-66
80960JD-50
80960JD-40
80960JD-33
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16

15
15
12
12
12
12
12
12
12

33.3

25
20

16.67

33.3

25
16

MHz

CLKIN Period

80960JT-100
80960JT-75
80960JD-66
80960JD-50
80960JD-40
80960JD-33
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16

30
40
30
40
50
60
30
40

62.5

66.7
66.7
83.3
83.3
83.3
83.3
83.3
83.3
83.3

CLKIN Period Stability

250

(1, 2)

CLKIN High Time

Measured at 1.5 V

(1)

CLKIN Low Time

Measured at 1.5 V

(1)

CLKIN Rise Time

0.8 V to 2.0 V (1)

CLKIN Fall Time

2.0 V to 0.8 V (1)

SYNCHRONOUS OUTPUT TIMINGS

OV1

Output Valid Delay, Except ALE/ALE
Inactive and DT/R for 3.3 V input signals

Same as above, but for 5.5 V input signals

2.5

13.5

16.5

(3)

OV2

Output Valid Delay, DT/R

80960JT
80960JD
80960JA/JF

0.5T

+ 7

0.5T

+ 7

0.5T

+ 4

0.5T

+ 9

0.5T

+ 9

0.5T

+ 18

Output Float Delay

2.5

13.5

(4)

NOTE:

See Table 24 on page 47 for note definitions for this table.

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

SYNCHRONOUS INPUT TIMINGS

IS1

Input Setup to CLKIN -- AD31:0, NMI,
XINT7:0

80960JT
80960JD
80960JA/JF

6
6
9

(5)

IH1

Input Hold from CLKIN -- AD31:0, NMI,
XINT7:0

80960JT
80960JD
80960JA/JF

1.5
1.5
1.0

(5)

IS2

Input Setup to CLKIN -- RDYRCV and
HOLD

80960JT
80960JD
80960JA/JF

6.5
6.5

10.0

(6)

IH2

Input Hold from CLKIN -- RDYRCV and
HOLD

(6)

IS3

Input Setup to CLKIN -- RESET

80960JT
80960JD
80960JA/JF

7
7
8

(7)

IH3

Input Hold from CLKIN -- RESET

80960JT
80960JD
80960JA/JF

2
2
1

(7)

IS4

Input Setup to RESET -- ONCE, STEST

80960JT
80960JD
80960JA/JF

7
7
8

(8)

IH4

Input Hold from RESET -- ONCE, STEST

80960JT
80960JD
80960JA/JF

2
2
1

(8)

RELATIVE OUTPUT TIMINGS

Address Valid to ALE/ALE Inactive

For 3.3 V Data Input Signals
For 5.0 V Data Input Signals

0.5T

- 5

0.5T

- 8

(9)

LXL

ALE/ALE Width

0.5T

- 7

Equal Loading (9)

LXA

Address Hold from ALE/ALE Inactive

DXD

DT/R Valid to DEN Active

BOUNDARY SCAN TEST SIGNAL TIMINGS

BSF

TCK Frequency

0.5T

MHz

BSCH

TCK High Time

Measured at 1.5 V

(1)

BSCL

TCK Low Time

Measured at 1.5 V

(1)

BSCR

TCK Rise Time

0.8 V to 2.0 V (1)

BSCF

TCK Fall Time

2.0 V to 0.8 V (1)

Table 23.

80960Jx AC Characteristics (Sheet 2 of 3)

Symbol

Parameter

Min

Max

Unit

Notes

NOTE:

See Table 24 on page 47 for note definitions for this table.

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

4.7.1

AC Test Conditions and Derating Curves

The AC Specifications in Section 4.7, "AC Specifications" are tested with the 50 pF load indicated
in Figure 10. Figure 11 shows how timings and output rise and fall times vary with load
capacitance.

Table 24.

Note Definitions for Table 23, 80960Jx AC Characteristics (pg. 44)

NOTES:

1. Not tested.

2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter

frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN
frequency.

3. Inactive ALE/ALE refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE

timings, refer to Relative Output Timings in this table.

4. A float condition occurs when the output current becomes less than I

. Float delay is not tested, but is

designed to be no longer than the valid delay.

5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI

and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition
at a particular clock edge. For asynchronous operation, NMI and XINT7:0 must be asserted for a
minimum of two CLKIN periods to guarantee recognition.

6. RDYRCV and HOLD are synchronous inputs. Setup and hold times must be met for proper processor

operation.

7. RESET may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a

particular clock edge.

8. ONCE and STEST must be stable at the rising edge of RESET for proper operation.

9. Guaranteed by design. May not be 100% tested.

10.Relative to falling edge of TCK.

11.Worst-case T

condition occurs on I/O pins when pins transition from a floating high input to driving a

low output state. The Address/Data Bus pins encounter this condition between the last access of a read,
and the address cycle of a following write. 5 V signals take 3 ns longer to discharge than 3.3 V signals at
50 pF loads.

Figure 10.

AC Test Load

Output Pin

= 50 pF for all signals

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

Figure 40.

Cold Reset Waveform

KIN

, A

SET

LOC

EST

I
L

~
~

r
s

Act

i
vit

~
~

lid

~
~

(Ou

t
pu

NCE

, A

,D/C

~
~

(
N

ote

~
~

l
e

t
e

~
~

l
i
d

put

t
e 3

)

~
~

BE3

:
0

, DE

AST

~
~

lid Outp

ut (Not

)

~
~

KIN p

r
i
o

,
fo

r
PL

sta

iliza

t
io

CC a

I
N st

RESET

Hig

,
m

i
n

i
m

~
~

i
l
t
-
i
n se

l
f
-te

t (

ote

(
I
np

ut)

~
~

.
T

pro

esso

r a

sser

t
s F

r
i
ng

i
l
t
-i

n s

l
f
-
t
es

t
.
If

l
f
-
t

t
pa

,
t

i
n

eas

sert

ed.

e p

r
oce

ssor

sert

s F

ring

e bu

s co

nfid

ence

st. If

the

s co

nfide

tes

t
pa

sses,

asse

rte

the

oce

ssor

beg

i
n

s u

ram

exe

i
o

.
If

the

pro

ess

fai

l
s

i
l
t
-
i
n

l
f
-te

t, i

t

i
n

i
t
i
a

t
e

s o

dum

l
oad

s ac

cess.

e l

r
ess

ndi

tes

the

i
n

t o

f
s

l
f-te

st fa

ilure

.
S

i
nce

e b

s i

i
d

l
e

hol

que

sts a

r
e

hon

dur

i
ng

rese

t a

bui

l
t
-
i
n se

l
f
-t

est.

~
~

:
0

.
W

sel

ed,

i
l
t
-
i
n

sel

f
t

st r

i
r
e

pro

i
m

t
el

I
N

: 39

3,0

for

960

, 2

07,

000

r 8

096

0JD

,

and

for

809

/JF

~
~

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

Figure 42.

Entering the ONCE State

KIN

, A

,
W/

RESET

LOC

, WIDT

H/HL

:
0

I
L

~
~

ONC

, A

:
2

D/C

~
~

BE3

:
0

, DE

,
BL

AST

~
~

HOL

~
~

npu

,
0

I
N

,
f

r P

N st

t
o

RESET

i
gh,

~
~

~ ~

~
~

(
N

e 1)

.
ONCE

y b

t
e

r
e

r
io

r

t
o

i
sin

f
RESET

: O

NCE

t i

not

l
a

tch

unt

i
l

the

ES:

CLK

I
N m

y n

allowe

d to

floa

~
~

EST

~
~

e O

npu

t m

y b

d af

ter

the

oce

ssor

ter

~
~

t
a

i
liza

t
io

It m

i
v

r
co

nti

to r

80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

5.1

Basic Bus States

The bus has five basic bus states: idle (Ti), address (Ta), wait/data (Tw/Td), recovery (Tr), and hold
(Th). During system operation, the processor continuously enters and exits different bus states.

The bus occupies the idle (Ti) state when no address/data transactions are in progress and when RESET is
asserted. When the processor needs to initiate a bus access, it enters the Ta state to transmit the address.

Following a Ta state, the bus enters the Tw/Td state to transmit or receive data on the address/data
lines. Assertion of the RDYRCV input signal indicates completion of each transfer. When data is
not ready, the processor can wait as long as necessary for the memory or I/O device to respond.

After the data transfer, the bus exits the Tw/Td state and enters the recovery (Tr) state. In the case of a
burst transaction, the bus exits the Td state and re-enters the Td/Tw state to transfer the next data word.
The processor asserts the BLAST signal during the last Tw/Td states of an access. Once all data words
transfer in a burst access (up to four), the bus enters the Tr state to allow devices on the bus to recover.

The processor remains in the Tr state until RDYRCV is deasserted. When the recovery state
completes, the bus enters the Ti state if no new accesses are required. If an access is pending, the
bus enters the Ta state to transmit the new address.

Figure 43.

Bus States with Arbitration

Ti -- IDLE STATE
Ta -- ADDRESS STATE
Tw / Td -- WAIT/DATA STATE
Tr -- RECOVERY STATE
Th -- HOLD STATE
To -- ONCE STATE

READY -- RDYRCV ASSERTED

NOT READY -- RDYRCV NOT ASSERTED

BURST -- BLAST NOT ASSERTED

NO BURST -- BLAST ASSERTED

RECOVERED -- RDYRCV NOT ASSERTED

NOT RECOVERED -- RDYRCV ASSERTED

REQUEST PENDING -- NEW TRANSACTION

NO REQUEST -- NO NEW TRANSACTION

HOLD -- HOLD REQUEST ASSERTED

NO HOLD -- HOLD REQUEST NOT ASSERTED

LOCKED -- ATOMIC EXECUTION (ATADD, ATMOD) IN PROGRESS

NOT LOCKED -- NO ATOMIC EXECUTION IN PROGRESS

RESET -- RESET ASSERTED

ONCE -- ONCE ASSERTED

Tw/Td

HOLD AND

NOT LOCKED

HOLD

RECOVERED AND

NO REQUEST AND

(NO HOLD OR

LOCKED)

RECOVERED AND

REQUEST

PENDING AND (NO

HOLD OR LOCKED)

NO REQUEST

AND NO HOLD

RESET

NOT

RECOVERED

RECOVERED AND

HOLD AND NOT

LOCKED

READY AND NO BURST

(READY AND BURST)

OR NOT READY

REQUEST PENDING

AND (NO HOLD OR

LOCKED)

NO REQUEST

AND (NO HOLD

OR LOCKED)

ONCE & RESET

DEASSERTION

REQUEST

PENDING AND

NO HOLD

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

5.2

Boundary-Scan Register

The Boundary-Scan register contains a cell for each pin as well as cells for control of I/O and HIGHZ pins.

Table 25 shows the bit order of the 80960Jx processor Boundary-Scan register. All table cells that
contain "CTL" select the direction of bidirectional pins or HIGHZ output pins. If a "1" is loaded
into the control cell, the associated pin(s) are HIGHZ or selected as input.

Table 25.

Boundary-Scan Register Bit Order

Bit

Signal

Input/

Output

Bit

Signal

Input/

Output

Bit

Signal

Input/

Output

RDYRCV (TDI)

DEN

AD17

I/O

HOLD

HOLDA

AD16

I/O

XINT0

ALE

AD15

I/O

XINT1

LOCK/ONCE

cell

Enable cell

AD14

I/O

XINT2

LOCK/ONCE

I/O

AD13

I/O

XINT3

BSTAT

AD12

I/O

XINT4

BE0

AD cells

Enable

cell

XINT5

BE1

AD11

I/O

XINT6

BE2

AD10

I/O

XINT7

BE3

AD9

I/O

NMI

AD31

I/O

AD8

I/O

FAIL

AD30

I/O

AD7

I/O

ALE

AD29

I/O

AD6

I/O

WIDTH/HLTD1

AD28

I/O

AD5

I/O

WIDTH/HLTD0

AD27

I/O

AD4

I/O

AD26

I/O

AD3

I/O

AD25

I/O

AD2

I/O

CONTROL1

Enable cell

AD24

I/O

AD1

I/O

CONTROL2

Enable cell

AD23

I/O

AD0

I/O

BLAST

AD22

I/O

CLKIN

D/C

AD21

I/O

RESET

ADS

AD20

I/O

STEST

(TDO)

W/R

AD19

I/O

DT/R

AD18

I/O

NOTE:

1. Enable cells are active low.

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

Table 29.

Summary of

-Word Load and Store Accesses (

= 1, 2, 3, 4)

Address Offset

from Natural

Boundary in Bytes

Accesses on 8-Bit Bus

(WIDTH1:0=00)

Accesses on 16 Bit Bus

(WIDTH1:0=01)

Accesses on 32 Bit

Bus (WIDTH1:0=10)

+0 (aligned)
(

=1, 2, 3, 4)

burst(s) of 4 bytes

case

=1:

burst of 2 short words

case

=2:

burst of 4 short words

case

=3:

burst of 4 short words
burst of 2 short words

case

=4:

2 bursts of 4 short words

burst of

word(s)

+1 (

=1, 2, 3, 4)

+5 (

= 2, 3, 4)

+9 (

= 3, 4)

+13 (

= 3, 4)

byte access

burst of 2 bytes

-1 burst(s) of 4 bytes

byte access

short-word access

-1 burst(s) of 2 short

words

byte access

short-word access

-1 word

access(es)

byte access

+2 (

=1, 2, 3, 4)

+6 (

= 2, 3, 4)

+10 (

= 3, 4)

+14 (

= 3, 4)

burst of 2 bytes

-1 burst(s) of 4 bytes

burst of 2 bytes

short-word access

-1 burst(s) of 2 short

words

short-word access

-1 word

access(es)

short-word access

+3 (

=1, 2, 3, 4)

+7 (

= 2, 3, 4)

+11 (

= 3, 4)

+15 (

= 3, 4)

byte access

-1 burst(s) of 4 bytes

burst of 2 bytes

byte access

-1 burst(s) of 2 short

words

short-word access

byte access

-1 word

access(es)

short-word access

byte access

+4 (

= 2, 3, 4)

+8 (

= 3, 4)

+12 (

= 3, 4)

burst(s) of 4 bytes

burst(s) of 2 short words

word access(es)

80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

6.0

Device Identification

80960Jx processors may be identified electrically, according to device type and stepping (see
Figure 46, and Table 31 through Table 36). Table 30 identifies the device type and stepping for all
5V, 80960Jx processors. Figure 46, and Table 31 through Table 36 identify all 3.3V-5V-tolerant
80960Jx processors. The device ID was enhanced to differentiate between 3.3V and 5V supply
voltages, and between non-clock-doubled and clock-doubled cores when stepping from the A2
stepping to the C0 stepping. The 32-bit identifier is accessible in three ways:

Upon reset, the identifier is placed into the g0 register.

The identifier may be accessed from supervisor mode at any time by reading the DEVICEID
register at address FF008710H.

The IEEE Standard 1149.1 Test Access Port may select the DEVICE ID register through the
IDCODE instruction.

The device and stepping letter is also printed on the top side of the product package.

Table 30.

80960Jx Device Type and Stepping Reference

Device and

Stepping

Version

Number

Part Number

Manufacturer

Complete ID

(Hex)

80960JT A0, A1

0000

0000 1000 0010 1011

0000 0001 001

0082B013

80960JD C0

0011

0000 1000 0011 0000

0000 0001 001

30830013

80960JF C0

0011

0000 1000 0010 0000

0000 0001 001

30820013

80960JA C0

0011

0000 1000 0010 0001

0000 0001 001

30821013

Figure 46.

80960JT

Device Identification Register

Manufacturer ID

Part Number

Version

Model

Gen

Product
Type

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

Table 31.

Fields of 80960JT Device ID

Field

Value

Definition

Version

See Table 32

Indicates major stepping changes.

0 = 3.3 V device

Indicates that a device is 3.3 V.

Product Type

000 100
(Indicates i960 CPU)

Designates type of product.

Generation Type

0001 = J-series

Indicates the generation (or series) the product belongs
to.

Model

D DPCC

D = Clock Multiplier

(01) Clock-Tripled

(P) Product Derivative

(0) Jx

C = Cache Size

(11) 16K I-cache, 4K D-cache

Indicates member within a series and specific model
information.

Manufacturer ID

000 0000 1001
(Indicates Intel)

Manufacturer ID assigned by IEEE.

Table 32.

80960JT Device ID Model Types

Device

Version

Product

Gen.

Model

Manufacturer ID

`1'

80960JT A0, A1

0000

000100

0001

01011

00000001001

Figure 47.

80960JD Device Identification Register

Manufacturer ID

Part Number

Version

Model

Gen

Product
Type

80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

Table 33.

Fields of 80960JD Device ID

Field

Value

Definition

Version

See Table 30

Indicates major stepping changes.

0 = 3.3 V device

1 = 5V device

Indicates that a device is 3.3 V.

Product Type

00 0100
(Indicates i960 CPU)

Designates type of product.

Generation Type

0001 = J-series

Indicates the generation (or series) the product belongs to.

Model

D000C

D = Clock Doubled

(0) Not Clock-Doubled

(1) Clock Doubled

C = Cache Size

(0) 4K I-cache, 2K
D-cache

(1) 2K I-cache, 1K
D-cache

Indicates member within a series and specific model information.

Manufacturer ID

000 0000 1001
(Indicates Intel)

Manufacturer ID assigned by IEEE.

Table 34.

80960JD Device ID Model Types

Device

Version

Product

Gen.

Model

Manufacturer ID

`1'

80960JD C0

0011

000100

0001

10000

00000001001

Figure 48.

80960JA/JF Device Identification Register

Manufacturer ID

Part Number

Version

Model

Gen

Product
Type

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

7.0

Revision History

This data sheet supersedes revisions 273109-001, 272971-002, and 276146-001. Table 37 indicates
significant changes since the previous revisions.

Table 35.

Fields of 80960JA/JF Device ID

Field

Value

Definition

Version

See Table 36

Indicates major stepping changes.

0 = 3.3 V device

1 = 5V device

Indicates that a device is 3.3 V.

Product Type

00 0100
(Indicates i960 CPU)

Designates type of product.

Generation Type

0001 = J-series

Indicates the generation (or series) to which the
product belongs.

Model

0000C

C = Cache Size

0 = 4K I-cache, 2K D-cache

1 = 2K I-cache, 1K D-cache

Indicates member within a series and specific
model information.

Manufacturer ID

000 0000 1001
(Indicates Intel)

Manufacturer ID assigned by IEEE.

Table 36.

80960JA/JF Device ID Model Types

Device

Version

Product

Gen.

Model

Manufacturer ID

`1'

80960JA C0

0011

000100

0001

00001

00000001001

80960JF C0

0011

000100

0001

00000

00000001001

Table 37.

Data Sheet Revision History

Figure 1 "80960Jx Microprocessor Package
Options" on page 7

Added MPBGA package diagram

Section 3.1.4, "80960Jx 196-Ball MPBGA
Pinout" on page 29

Added new Figures 6 and 7, Tables 10, 11 and 13

Figure 12 "T

vs. AD Bus Load Capacitance" on

page 48

Added with following note

Throughout document

Merged 80960JA/JF/JD/JT 3.3 volt Processor data sheets

Document Outline

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Document Outline

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