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November 1995

INTEL CORPORATION 1995

Order Number 290429-005

28F008SA

8-MBIT (1-MBIT x 8) FlashFile

MEMORY

Extended Temperature Specifications Included

High-Density Symmetrically-Blocked
Architecture

Sixteen 64-Kbyte Blocks

Extended Cycling Capability

100 000 Block Erase Cycles
1 6 Million Block Erase
Cycles per Chip

Automated Byte Write and Block Erase

Command User Interface
Status Register

System Performance Enhancements

RY BY

Status Output

Erase Suspend Capability

Deep Power-Down Mode

0 20 mA I

Typical

Very High-Performance Read

85 ns Maximum Access Time

SRAM-Compatible Write Interface

Hardware Data Protection Feature

Erase Write Lockout during Power
Transitions

Industry Standard Packaging

40-Lead TSOP 44-Lead PSOP

ETOX III Nonvolatile Flash Technology

12V Byte Write Block Erase

Intel's 28F008SA 8-Mbit FlashFile

Memory is the highest density nonvolatile read write solution for sol-

id-state storage The 28F008SA's extended cycling symmetrically blocked architecture fast access time
write automation and low power consumption provide a more reliable lower power lighter weight and higher
performance alternative to traditional rotating disk technology The 28F008SA brings new capabilities to porta-
ble computing Application and operating system software stored in resident flash memory arrays provide
instant-on rapid execute-in-place and protection from obsolescence through in-system software updates
Resident software also extends system battery life and increases reliability by reducing disk drive accesses

For high density data acquisition applications the 28F008SA offers a more cost-effective and reliable alterna-
tive to SRAM and battery Traditional high density embedded applications such as telecommunications can
take advantage of the 28F008SA's nonvolatility blocking and minimal system code requirements for flexible
firmware and modular software designs

The 28F008SA is offered in 40-lead TSOP (standard and reverse) and 44-lead PSOP packages Pin assign-
ments simplify board layout when integrating multiple devices in a flash memory array or subsystem This
device uses an integrated Command User Interface and state machine for simplified block erasure and byte
write The 28F008SA memory map consists of 16 separately erasable 64-Kbyte blocks

Intel's 28F008SA employs advanced CMOS circuitry for systems requiring low power consumption and noise
immunity Its 85 ns access time provides superior performance when compared with magnetic storage media
A deep powerdown mode lowers power consumption to 1 mW typical thru V

crucial in portable computing

handheld instrumentation and other low-power applications The RP

power control input also provides

absolute data protection during system powerup down

Manufactured on Intel's 0 8 micron ETOX process the 28F008SA provides the highest levels of quality
reliability and cost-effectiveness

28F008SA

PRODUCT OVERVIEW

The

28F008SA

high-performance

8-Mbit

(8 388 608 bit) memory organized as 1 Mbyte
(1 048 576 bytes) of 8 bits each Sixteen 64-Kbyte
(65 536 byte) blocks are included on the 28F008SA
A memory map is shown in Figure 6 of this specifica-
tion A block erase operation erases one of the six-
teen blocks of memory in typically 1 6 seconds in-
dependent of the remaining blocks Each block can
be independently erased and written 100 000 cy-
cles Erase Suspend

mode allows system software

to suspend block erase to read data or execute
code from any other block of the 28F008SA

The 28F008SA is available in the 40-lead TSOP
(Thin Small Outline Package 1 2 mm thick) and 44-
lead PSOP

(Plastic Small Outline) packages Pin-

outs are shown in Figures 2 and 4 of this specifica-
tion

The Command User Interface serves as the inter-
face between the microprocessor or microcontroller
and the internal operation of the 28F008SA

Byte Write and Block Erase Automation

allow

byte write and block erase operations to be execut-
ed using a two-write command sequence to the
Command User Interface The internal Write State
Machine

(WSM) automatically executes the algo-

rithms and timings necessary for byte write and
block

erase

operations

including

verifications

thereby unburdening the microprocessor or micro-
controller Writing of memory data is performed in
byte increments typically within 9 ms an 80% im-
provement over current flash memory products I

byte write and block erase currents

are 10 mA

typical 30 mA maximum V

byte write and

block erase voltage

is 11 4V to 12 6V

The Status Register indicates the status of the
WSM and when the WSM successfully completes
the desired byte write or block erase operation

The RY BY

output gives an additional indicator of

WSM activity providing capability for both hardware
signal of status (versus software polling) and status
masking (interrupt masking for background erase
for example) Status polling using RY BY

mini-

mizes both CPU overhead and system power con-
sumption When low RY BY

indicates that the

WSM is performing a block erase or byte write oper-
ation RY BY

high indicates that the WSM is ready

for new commands block erase is suspended or the
device is in deep powerdown mode

Maximum access time is 85 ns (t

ACC

)

over the com-

mercial temperature range (0 C to a70 C) and over
V

supply voltage range (4 5V to 5 5V and 4 75V to

5 25V) I

active current

(CMOS Read) is 20 mA

typical 35 mA maximum at 8 MHz

When the CE

and RP

pins are at V

the I

CMOS Standby

mode is enabled

A Deep Powerdown mode is enabled when the
RP

pin is at GND minimizing power consumption

and providing write protection I

current

in deep

powerdown is 0 20 mA typical Reset time of 400 ns
is required from RP

switching high until outputs are

valid to read attempts Equivalently the device has a
wake time of 1 ms from RP

high until writes to the

Command User Interface are recognized by the
28F008SA With RP

at GND the WSM is reset

and the Status Register is cleared

28F008SA

Table 1 Pin Description

Symbol

Type

Name and Function

� A

INPUT

ADDRESS INPUTS

for memory addresses Addresses are internally

latched during a write cycle

� DQ

INPUT OUTPUT

DATA INPUT OUTPUTS

Inputs data and commands during Command

User Interface write cycles outputs data during memory array Status
Register and Identifier read cycles The data pins are active high and
float to tri-state off when the chip is deselected or the outputs are
disabled Data is internally latched during a write cycle

INPUT

CHIP ENABLE

Activates the device's control logic input buffers

decoders and sense amplifiers CE

is active low CE

high deselects

the memory device and reduces power consumption to standby levels

INPUT

RESET DEEP POWERDOWN

Puts the device in deep powerdown

mode RP

is active low RP

high gates normal operation RP

also

locks out block erase or byte write operations when active low providing
data protection during power transitions RP

active resets internal

automation Exit from Deep Powerdown sets device to read-array mode

INPUT

OUTPUT ENABLE

Gates the device's outputs through the data buffers

during a read cycle OE

is active low

INPUT

WRITE ENABLE

Controls writes to the Command User Interface and

array blocks WE

is active low Addresses and data are latched on the

rising edge of the WE

pulse

RY BY

OUTPUT

READY BUSY

Indicates the status of the internal Write State

Machine When low it indicates that the WSM is performing a block
erase or byte write operation RY BY

high indicates that the WSM is

ready for new commands block erase is suspended or the device is in
deep powerdown mode RY BY

is always active and does NOT float

to tri-state off when the chip is deselected or data outputs are disabled

BLOCK ERASE BYTE WRITE POWER SUPPLY

for erasing blocks of

the array or writing bytes of each block

NOTE

With V

PPLMAX

memory contents cannot be altered

DEVICE POWER SUPPLY (5V

10% 5V

5%)

GND

GROUND

Электронный компонент: E28F008SA-85