Document Outline
- TITLE PAGE
- CONTENTS
- 1.0 INTRODUCTION
- 1.1 Enhanced Features
- 1.2 Product Overview
- 2.0 DEVICE PINOUT
- 3.0 MEMORY MAPS
- 3.1 Extended Status Registers Memory Map
- 4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
- 4.1 Bus Operations for Word-Wide Mode (BYTE# = V IH )
- 4.2 Bus Operations for Byte-Wide Mode (BYTE# = V IL )
- 4.3 28F008SACompatible Mode Command Bus Definitions
- 4.4 28F016SVPerformance Enhancement Command Bus Definitions
- 4.5 Compatible Status Register
- 4.6 Global Status Register
- 4.7 Block Status Register
- 4.8 Device Configuration Code
- 5.0 ELECTRICAL SPECIFICATIONS
- 5.1 Absolute Maximum Ratings
- 5.2 Capacitance
- 5.3 DC Characteristics
- 5.4 DC Characteristics
- 5.5 Timing Nomenclature
- 5.6 AC CharacteristicsRead Only Operations
- 5.7 Power-Up and Reset Timings
- 5.8 AC Characteristics for WE#Controlled Command Write Operations
- 5.9 AC Characteristics for CE#Controlled Command Write Operations
- 5.10 AC Characteristics for WE#Controlled Page Buffer Write Operations
- 5.11 AC Characteristics for CE#Controlled Page Buffer Write Operations
- 5.12 Erase and Word/Byte Program Performance
- 6.0 MECHANICAL SPECIFICATIONS
- APPENDIX A:Device Nomenclature and Ordering Information
- APPENDIX B: Additional Information
- FIGURES
- Figure 1. 28F016SV Block Diagram
- Figure 2. 28F016SV 56-Lead TSOP Pinout Configuration
- Figure 3. 56-Lead SSOP Pinout Configuration
- Figure 4. 28F016SV Memory Maps (Byte-Wide and Word-Wide Modes)
- Figure 5. Extended Status Register Memory Map (Byte-Wide Mode)
- Figure 6. Extended Status Register Memory Map (Word-Wide Mode)
- Figure 7. Transient Input/Output Reference Waveform for
- Figure 8. Transient Input/Output Reference Waveform for V CC = 3.3V 0.3V
- Figure 9. Transient Equivalent Testing Load Circuit
- Figure 10. Transient Equivalent Testing Load Circuit
- Figure 11. High Speed Transient Equivalent Testing Load Circuit
- Figure 12. Read Timing Waveforms
- Figure 13. BYTE# Timing Waveforms
- Figure 14. V CC Power-Up and RP# Reset Waveforms
- Figure 15. AC Waveforms for Command Write Operations
- Figure 16. Alternate AC Waveforms for Command Write Operations
- Figure 17. WE#Controlled Page Buffer Write Timing Waveforms
- Figure 18. CE#Controlled Page Buffer Write Timing Waveforms
- Figure 19. Mechanical Specifications of the 28F016SV 56-Lead TSOP Type I Package
- Figure 20. Mechanical Specifications of the 28F016SV 56-Lead SSOP Type I Package
E
7/11/97 11:03 AM 29052807.DOC
July 1997
Order Number: 290528-007
n
SmartVoltage Technology
User-Selectable 3.3V or 5V V
CC
User-Selectable 5V or 12V V
PP
n
65 ns Access Time
n
1 Million Erase Cycles per Block
n
30.8 MB/sec Burst Write Transfer Rate
n
0.48 MB/sec Sustainable Write Transfer
Rate
n
Configurable x8 or x16 Operation
n
56-Lead TSOP and SSOP Type I
Packages
n
Backwards-Compatible with 28F016SA,
28F008SA Command Set
n
Revolutionary Architecture
Multiple Command Execution
Program during Erase
Command Super-Set of the Intel
28F008SA
Page Buffer Program
n
2 A Typical Deep Power-Down
n
32 Independently Lockable Blocks
n
State-of-the-Art 0.6 m ETOXTM IV Flash
Technology
Intel's 28F016SV 16-Mbit FlashFileTM memory is a revolutionary architecture which is the ideal choice for
designing embedded direct-execute code and mass storage data/file flash memory systems. With innovative
capabilities, low-power operation, user-selectable V
PP
voltage and high read/program performance, the
28F016SV enables the design of truly mobile, high-performance personal computing and communications
products.
The 28F016SV is the highest density, highest performance nonvolatile read/program solution for solid-state
storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F008SA 8-Mbit and
28F016SA 16-Mbit FlashFile memories), extended cycling, flexible V
CC
and V
PP
voltage (SmartVoltage
technology), fast program and read performance and selective block locking, provide a highly-flexible memory
component suitable for Resident Flash Arrays, high-density memory cards and PCMCIA-ATA flash drives.
The 28F016SV's dual read voltage enables the design of memory cards which can be read/written in 3.3V
and 5V systems interchangeably. Its x8/x16 architecture allows optimization of the memory-to-processor
interface. The flexible block locking option enables bundling of executable application software in a Resident
Flash Array or memory card. The 28F016SV is manufactured on Intel's 0.6 m ETOX IV process technology.
28F016SV
16-MBIT (1 MBIT x 16, 2 MBIT x 8)
FlashFileTM MEMORY
Includes Commercial and Extended Temperature Specifications
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F016SV may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
or visit Intel's Website at http:\\www.intel.com
COPYRIGHT INTEL CORPORATION, 1997
CG-041493
*
Third-party brands and names are the property of their respective owners.
E
28F016SV FlashFileTM MEMORY
3
CONTENTS
PAGE
PAGE
1.0 INTRODUCTION .............................................7
1.1 Enhanced Features......................................7
1.2 Product Overview.........................................7
2.0 DEVICE PINOUT.............................................9
2.1 Lead Descriptions ...................................... 11
3.0 MEMORY MAPS ........................................... 15
3.1 Extended Status Registers Memory Map ... 16
4.0 BUS OPERATIONS, COMMANDS AND
STATUS REGISTER DEFINITIONS ................ 17
4.1 Bus Operations for Word-Wide Mode
(BYTE# = V
IH
) .............................................. 17
4.2 Bus Operations for Byte-Wide Mode
(BYTE# = V
IL
)............................................... 17
4.3 28F008SA--Compatible Mode Command
Bus Definitions ............................................. 18
4.4 28F016SV--Performance Enhancement
Command Bus Definitions ............................ 19
4.5 Compatible Status Register........................ 21
4.6 Global Status Register ............................... 22
4.7 Block Status Register................................. 23
4.8 Device Configuration Code......................... 24
5.0 ELECTRICAL SPECIFICATIONS..................25
5.1 Absolute Maximum Ratings ........................25
5.2 Capacitance ...............................................26
5.3 DC Characteristics (V
CC
= 3.3V 0.3V) .....29
5.4 DC Characteristics (V
CC
= 5V 0.5V)
5V 0.25V) ..................................................33
5.5 Timing Nomenclature .................................37
5.6 AC Characteristics--Read Only Operations38
5.7 Power-Up and Reset Timings.....................43
5.8 AC Characteristics for WE#--Controlled
Command Write Operations .........................44
5.9 AC Characteristics for CE#--Controlled
Command Write Operations) ........................49
5.10 AC Characteristics for WE#--Controlled
Page Buffer Program Operations..................54
5.11 AC Characteristics for CE#--Controlled
Page Buffer Program Operations..................56
5.12 Erase and Word/Byte Program
Performance.................................................58
6.0 MECHANICAL SPECIFICATIONS.................60
APPENDIX A: Device Nomenclature and
Ordering Information .....................................61
APPENDIX B: Ordering Information .................63
28F016SV FlashFileTM MEMORY
E
4
REVISION HISTORY
Number
Description
-001
Original Version
-002
Added 28F016SV-065/-070 at 5V V
CC
and 28F016SV-075 at 3.3V V
CC
.
Improved burst write transfer rate to 30.8 MB/sec.
Added 56-lead SSOP Type I packaging information.
Changed V
PPLK
from 2V to 1.5V.
Increased I
CCR
at 5V V
CC
and 3.3V V
CC
:
I
CCR1
from 30 mA (typ)/35 mA (max) to 40 mA (typ)/50 mA (max) @ V
CC
= 3.3V
I
CCR2
from 15 mA (typ)/20 mA (max) to 20 mA (typ)/30 mA (max) @ V
CC
= 3.3V
I
CCR1
from 50 mA (typ)/60 mA (max) to 75 mA (typ)/95 mA (max) @ V
CC
= 5V
I
CCR2
from 30 mA (typ)/35 mA (max) to 45 mA (typ)/55 mA (max) @ V
CC
= 5V
Moved AC Characteristics for Extended Register Reads into separate table.
Increased V
PP
MAX from 13V to 14V.
Added Erase Suspend Command Latency times to Section 5.12
Modified Device Nomenclature Section to include SSOP package option and Ordering
Information
-003
Changed definition of "NC." Removed "No internal connection to die" from description.
Added "
xx
" to Upper Byte of Command (Data) Definition in Sections 4.3 and 4.4.
Added Note to Sleep Command (Section 4.4) denoting that the chip must be de-selected
in order for the power consumption in sleep mode to reach deep power-down
levels.
Modified parameters "V" and "I" of Section 5.1 to apply to "NC" pins.
Increased I
PPR
(V
PP
Read Current) for V
PP
> V
CC
to 200 A at V
CC
= 3.3V and V
CC
= 5V
Changed V
CC
= 5V DC Characteristics (Section 5.5) marked with Note 1 to indicate
that these currents are specified for a CMOS rise/fall time (10% to 90%) of <5 ns
and a TTL rise/fall time of <10 ns.
Corrected the graphical representation of t
WHGL
and t
EHGL
in Figures 15 and 16.
Increased Typical "Page Buffer Byte/Word Program Times" from 6.0 s to 8.0 s (Byte)
and 12.1 s to 16.0 s (Word) @ V
CC
= 3.3V/5V and V
PP
= 5V:
Increased Typ. "Byte/Word Program Times" (t
WHRH1A
/t
WHRH1B
) for V
PP
= 5V (Section
5.12)
t
WHRH1A
from 16.5 s to 29.0 s and t
WHRH1B
from 24.0 s to 35.0 s at V
CC
=3.3V
t
WHRH1A
from 11.0 s to 20.0 s and t
WHRH1B
from 16.0 s to 25.0 s at V
CC
= 5V
Increased Typical "Block Program Times" (t
WHRH2
/t
WHRH3
)for V
PP
=5V (Section 5.12):
t
WHRH2
from 1.1 sec to 1.9 sec and t
WHRH3
from 0.8 sec to 1.2 sec at V
CC
= 3.3V
t
WHRH2
from 0.8 sec to 1.4 sec and t
WHRH3
from 0.6 sec to 0.85 sec at V
CC
= 5V
Changed "Time from Erase Suspend Command to WSM Ready" spec name to "Erase
Suspend Latency Time to Read;" modified typical values and added Min/Max
values at V
CC
=3.3/5V and V
PP
=5V/12V (Section 5.12)
Added "Erase Suspend Latency Time to Program" Specifications to Section 5.12
Minor cosmetic changes throughout document
E
28F016SV FlashFileTM MEMORY
5
REVISION HISTORY
(Continued)
Number
Description
-004
Added 3/5# pin to Block Diagram (Figure 1), Pinout Configurations (Figures 2 and 3),
Product Overview (Section 1.1) and Lead Descriptions (Section 2.1)
Added 3/5# pin to Test Conditions of I
CCS
Specifications
Added 3/5# pin (Y) to Timing Nomenclature (Section 5.5)
Increased t
PHQV
Specifications at 5V V
CC
to 400 ns for E28F016SV 065 devices
and 480 ns for E28F106SV 070 devices.
Modified Power-Up and Reset Timings (Section 5.9) to include 3/5# pin: Removed t
5VPH
and t
3VPH
specifications; Added t
PLYL
, t
PLYH
, t
YLPH
, and t
YHPH
specifications
Added t
PHEL3
and t
PHEL5
specifications to Power-Up and Reset Timings (Section 5.9)
Corrected TSOP Mechanical Specification A
1
from 0.50 mm to 0.050 mm (Section 6.0)
Corrected SSOP Mechanical Spec. B (max) from 0.20 mm to 0.40 mm (Section 6.0)
Minor cosmetic changes throughout document.
-005
Updated DC Specifications: I
CCD
, I
PPES
Updated AC Specifications: Page Buffer Reads: (t
AVAV
, t
AVQV
, t
ELQV
, and t
FLQV
/t
FHQV
)
Page Buffer WE#-Controlled Command Writes (t
ELWL
)
CE#-Controlled Command Write Parameters (t
AVAV
, t
ELEH
, t
EHEL
)
Combined Commercial and Extended Temperature information into single datasheet.
-006
Updated AC Specifications: Page Buffer Reads: (t
AVAV
, t
AVQV
, t
ELQV
, and t
FLQV
/t
FHQV
)
-007
Updated Disclaimer
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