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November 1995
COPYRIGHT
INTEL CORPORATION 1995
Order Number 290448-005
2-MBIT (128K x 16 256K x 8)
BOOT BLOCK
FLASH MEMORY FAMILY
28F200BX-T B 28F002BX-T B
Y
x8 x16 Input Output Architecture
28F200BX-T 28F200BX-B
For High Performance and High
Integration 16-bit and 32-bit CPUs
Y
x8-only Input Output Architecture
28F002BX-T 28F002BX-B
For Space Constrained 8-bit
Applications
Y
Upgradeable to Intel's SmartVoltage
Products
Y
Optimized High-Density Blocked
Architecture
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
One 96-KB Main Block
One 128 KB Main Block
Top or Bottom Boot Locations
Y
Extended Cycling Capability
100 000 Block Erase Cycles
Y
Automated Word Byte Write and
Block Erase
Command User Interface
Status Registers
Erase Suspend Capability
Y
SRAM-Compatible Write Interface
Y
Automatic Power Savings Feature
1 mA Typical I
CC
Active Current in
Static Operation
Y
Hardware Data Protection Feature
Erase Write Lockout during Power
Transitions
Y
Very High-Performance Read
60 80 120 ns Maximum Access Time
30 40 40 ns Maximum Output Enable
Time
Y
Low Power Consumption
20 mA Typical Active Read Current
Y
Reset Deep Power-Down Input
0 2 mA I
CC
Typical
Acts as Reset for Boot Operations
Y
Extended Temperature Operation
b
40 C to
a
85 C
Y
Write Protection for Boot Block
Y
Industry Standard Surface Mount
Packaging
28F200BX JEDEC ROM Compatible
44-Lead PSOP
56-Lead TSOP
28F002BX 40-Lead TSOP
Y
12V Word Byte Write and Block Erase
V
PP
e
12V
g
5% Standard
V
PP
e
12V
g
10% Option
Y
ETOX
TM
III Flash Technology
5V Read
Y
Independent Software Vendor Support
28F200BX-T B 28F002BX-T B
Intel's 2-Mbit Flash Memory Family is an extension of the Boot Block Architecture which includes block-selec-
tive erasure automated write and erase operations and standard microprocessor interface The 2-Mbit Flash
Memory Family enhances the Boot Block Architecture by adding more density and blocks x8 x16 input out-
put control very high speed low power an industry-standard ROM compatible pinout and surface mount
packaging The 2-Mbit flash family allows for an easy upgrade to Intel's 4-Mbit Boot Block Flash Memory
Family
The Intel 28F200BX-T B are 16-bit wide flash memory offerings These high-density flash memories provide
user selectable bus operation for either 8-bit or 16-bit applications The 28F200BX-T and 28F200BX-B are
2 097 152-bit nonvolatile memories organized as either 262 144 bytes or 131 072 words of information They
are offered in 44-Lead plastic SOP and 56-Lead TSOP packages The x8 x16 pinout conforms to the industry-
standard ROM EPROM pinout
The Intel 28F002BX-T B are 8-bit wide flash memories with 2 097 152 bits organized as 262 144 bytes of
information They are offered in a 40-lead TSOP package which is ideal for space-constrained portable
systems
These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified
word byte write and block erasure The 28F200BX-T 28F002BX-T provide block locations compatible with
Intel's MCS -186 family 80286 i386
TM
i486
TM
i860
TM
and 80960CA microprocessors The 28F200BX-B
28F002BX-B provide compatibility with Intel's 80960KX and 80960SX families as well as other embedded
microprocessors
The boot block includes a data protection feature to protect the boot code in critical applications With a
maximum access time of 60 ns these 2-Mbit flash devices are very high-performance memories which inter-
face at zero wait-state to a wide range of microprocessors and microcontrollers A deep power-down mode
lowers the total V
CC
power consumption to 1 mW typical This is critical in handheld battery-powered systems
For very low-power applications using a 3 3V supply refer to the Intel 28F200BX-TL BL 28F002BX-TL BL
2-Mbit Boot Block Flash Memory Family datasheet
Manufactured on Intel's 0 8 micron ETOX III process the 2-Mbit flash memory family provides world-class
quality reliability and cost-effectiveness at the 2-Mbit density level
2
28F200BX-T B 28F002BX-T B
1 0
PRODUCT FAMILY OVERVIEW
Throughout this datasheet the 28F200BX refers to
both the 28F200BX-T and 28F200BX-B devices and
28F002BX refers to both the 28F002BX-T and
28F002BX-B devices The 2-Mbit flash memory fam-
ily refers to both the 28F200BX and 28F002BX prod-
ucts This datasheet comprises the specifications for
four separate products in the 2-Mbit flash memory
family Section 1 provides an overview of the 2-Mbit
flash memory family including applications pinouts
and pin descriptions Sections 2 and 3 describe in
detail the specific memory organizations for the
28F200BX and 28F002BX products respectively
Section 4 combines a description of the family's
principles of operations Finally Section 5 describes
the family's operating specifications
PRODUCT FAMILY
x8 x16 Products
x8-Only Products
28F200BX-T
28F002BX-T
28F200BX-B
28F002BX-B
1 1 Designing for Upgrade to
SmartVoltage Products
Today's high volume boot block products are up-
gradable to Intel's SmartVoltage boot block prod-
ucts that provide program and erase operation at 5V
or 12V V
PP
and read operation at 3V or 5V V
CC
Intel's SmartVoltage boot block products provide the
following enhancements to the boot block products
described in this data sheet
1 DU pin is replaced by WP
to provide a means
to lock and unlock the boot block with logic sig-
nals
2 5V Program Erase operation uses proven pro-
gram and erase techniques with 5V
g
10% ap-
plied to VPP
3 Enhanced circuits optimize performance at 3 3V
V
CC
Refer to the 2 4 or 8 Mbit SmartVoltage Boot Block
Flash Memory Data Sheets for complete specifica-
tions
When you design with 12V V
PP
boot block products
you should provide the capability in your board de-
sign to upgrade to SmartVoltage products
Follow these guidelines to ensure compatibility
1 Connect DU (WP
on SmartVoltage products) to
a control signal or to V
CC
or GND
2 If adding a switch on V
PP
for write protection
switch to GND for complete write protection
3 Allow for connecting 5V to V
PP
and disconnect
12V from the V
PP
line if desired
1 2 Main Features
The 28F200BX 28F002BX boot block flash memory
family is a very high performance 2-Mbit (2 097 152
bit) memory family organized as either 128 KWords
(131 072 words) of 16 bits each or 256 Kbytes
(262 144 bytes) of 8 bits each
Five Separately Erasable Blocks
including a hard-
ware-lockable boot block
(16 384 Bytes) two pa-
rameter blocks
(8 192 Bytes each) and two main
blocks
(1 block of 98 304 Bytes and 1 block of
131 072 Bytes) are included on the 2-Mbit family An
erase operation erases one of the main blocks in
typically 2 4 seconds and the boot or parameter
blocks in typically 1 0 second Each block can be
independently erased and programmed 100 000
times
The Boot Block
is located at either the top
(28F200BX-T
28F002BX-T)
or
the
bottom
(28F200BX-B 28F002BX-B) of the address map in
order to accommodate different microprocessor pro-
tocols for boot code location The hardware locka-
ble boot block
provides the most secure code stor-
age The boot block is intended to store the kernel
code required for booting-up a system When the
RP
pin is between 11 4V and 12 6V the boot block
is unlocked and program and erase operations can
be performed When the RP
pin is at or below 6 5V
the boot block is locked and program and erase op-
erations to the boot block are ignored
The 28F200BX products are available in the ROM
EPROM compatible pinout and housed in the 44-
Lead PSOP (Plastic Small Outline) package and the
56-Lead TSOP (Thin Small Outline 1 2mm thick)
package as shown in Figures 3 and 4
The
28F002BX products are available in the 40-Lead
TSOP (1 2mm thick) package as shown in Figure 5
The Command User Interface (CUI) serves as the
interface between the microprocessor or microcon-
troller and the internal operation of the 28F200BX
and 28F002BX flash memory products
Program and Erase Automation
allows program
and erase operations to be executed using a two-
write command sequence to the CUI The internal
Write State Machine (WSM) automatically executes
the algorithms and timings necessary for program
and erase operations including verifications there-
by unburdening the microprocessor or microcontrol-
ler Writing of memory data is performed in word or
byte increments for the 28F200BX family and in byte
increments for the 28F002BX family typically within
9 ms which is a 100% improvement over current
flash memory products
3
28F200BX-T B 28F002BX-T B
The Status Register (SR) indicates the status of the
WSM and whether the WSM successfully completed
the desired program or erase operation
Maximum Access Time of 60 ns (t
ACC
)
is achieved
over the commercial temperature range (0 C to
70 C) 5% V
CC
supply voltage range (4 75V to
5 25V) and 30 pF output load Refer to Figure 19
t
ACC
vs Output Load Capacitance for larger output
loads Maximum Access Time of 80 ns (t
ACC
)
is
achieved over the commercial temperature range
10% V
CC
supply range (4 5V to 5 5V) and 100 pF
output load
I
PP
maximum Program current is 40 mA for x16
operation and 30 mA for x8 operation I
PP
Erase
current is 30 mA maximum V
PP
erase and pro-
gramming voltage is 11 4V to 12 6V (V
PP
e
12V
g
5%) under all operating conditions
As an op-
tion V
PP
can also vary between 10 8V to 13 2V (V
PP
e
12V
g
10%) with a guaranteed number of 100
block erase cycles
Typical I
CC
Active Current of 25 mA
is achieved
for the x16 products (28F200BX) typical I
CC
Active
Current of 20 mA
is achieved for the x8 products
(28F200BX 28F002BX) Refer to the I
CC
active cur-
rent derating curves in this datasheet
The 2-Mbit boot block flash family is also designed
with an Automatic Power Savings (APS) feature to
minimize system battery current drain and allow for
very low power designs Once the device is ac-
cessed to read array data APS mode will immedi-
ately put the memory in static mode of operation
where I
CC
active current is typically 1 mA until the
next read is initiated
When the CE
and RP
pins are at V
CC
and the
BYTE
pin (28F200BX-only) is at either V
CC
or
GND the CMOS Standby mode is enabled where
I
CC
is typically 50 mA
A Deep Power-Down Mode is enabled when the
RP
pin is at ground minimizing power consumption
and providing write protection during power-up con-
ditions I
CC
current
during deep power-down mode
is 0 20 mA typical An initial maximum access time
or Reset Time of 300 ns is required from RP
switching until outputs are valid Equivalently the
device has a maximum wake-up time of 215 ns until
writes to the Command User Interface are recog-
nized When RP
is at ground the WSM is reset the
Status Register is cleared and the entire device is
protected from being written to This feature pre-
vents data corruption and protects the code stored
in the device during system reset The system Reset
pin can be tied to RP
to reset the memory to nor-
mal read mode upon activation of the Reset pin
With on-chip program erase automation in the
2-Mbit family and the RP
functionality for data pro-
tection when the CPU is reset and even if a program
or erase command is issued the device will not rec-
ognize any operation until RP
returns to its normal
state
For the 28F200BX Byte-wide or Word-wide In-
put Output Control
is possible by controlling the
BYTE
pin When the BYTE
pin is at a logic low
the device is in the byte-wide mode (x8) and data is
read and written through DQ 0 7
During the byte-
wide mode DQ 8 14 are tri-stated and DQ15 Ab1
becomes the lowest order address pin When the
BYTE
pin is at a logic high the device is in the
word-wide mode (x16) and data is read and written
through DQ 0 15
1 3 Applications
The 2-Mbit boot block flash family combines high
density high performance cost-effective flash mem-
ories with blocking and hardware protection capabili-
ties Its flexibility and versatility will reduce costs
throughout the product life cycle Flash memory is
ideal for Just-In-Time production flow reducing sys-
tem inventory and costs and eliminating component
handling during the production phase During the
product life cycle when code updates or feature en-
hancements become necessary flash memory will
reduce the update costs by allowing either a user-
performed code change via floppy disk or a remote
code change via a serial link The 2-Mbit boot block
flash family provides full function blocked flash
memories suitable for a wide range of applications
These applications include Extended PC BIOS
Digital Cellular Phone
program and data storage
Telecommunication
boot firmware
and various
other embedded applications where both program
and data storage are required
Reprogrammable systems such as personal com-
puters are ideal applications for the 2-Mbit flash
products Portable and handheld personal computer
applications are becoming more complex with the
addition of power management software to take ad-
vantage of the latest microprocessor technology
the availability of ROM-based application software
pen tablet code for electronic hand writing and diag-
nostic code
Figure 1 shows an example of a
28F200BX-T application
This increase in software sophistication augments
the probability that a code update will be required
after the PC is shipped The 2-Mbit flash products
provide an inexpensive update solution for the note-
book and handheld personal computers while ex-
tending their product lifetime
Furthermore
the
2-Mbit flash products' power-down mode provides
added flexibility for these battery-operated portable
designs which require operation at very low power
levels
4
28F200BX-T B 28F002BX-T B
The 2-Mbit flash products also provide excellent de-
sign solutions for Digital Cellular Phone and Tele-
communication switching applications requiring high
performance high density storage capability cou-
pled with modular software designs and a small
form factor package (x8-only bus) The 2-Mbit's
blocking scheme allows for an easy segmentation of
the embedded code with 16 Kbytes of Hardware-
Protected Boot code 2 Main Blocks of program
code and 2 Parameter Blocks of 8 Kbytes each for
frequently updatable data storage and diagnostic
messages
(e g
phone
numbers
authorization
codes) Figure 2 is an example of such an applica-
tion with the 28F002BX-T
These are a few actual examples of the wide range
of applications for the 2-Mbit Boot Block flash mem-
ory family which enable system designers to achieve
the best possible product design Only your imagina-
tion limits the applicability of such a versatile product
family
290448 4
Figure 1 28F200BX Interface to Intel386
TM
EX Embedded Processor
290448 24
Figure 2 28F002BX Interface to INTEL 80C188EB 8-Bit Embedded Microprocessor
5
28F200BX-T B 28F002BX-T B
1 4 Pinouts
The 28F200BX 44-Lead PSOP pinout follows the in-
dustry standard ROM EPROM pinout as shown in
Figure 3 with an upgrade to the 28F400BX (4-Mbit
flash family) Furthermore the 28F200BX 56-Lead
TSOP pinout shown in Figure 4 provides density up-
grades to the 28F400BX and to future higher density
boot block memories
The 28F002BX 40-Lead TSOP pinout shown in Fig-
ure 5 is 100% compatible and provides a density
upgrade to the 28F004BX 4-Mbit Boot Block flash
memory
28F400BX
28F400BX
290448 25
Figure 3 PSOP Lead Configuration for x8 x16 28F200BX
6
28F200BX-T B 28F002BX-T B
28F400BX
28F400BX
290448 3
Figure 4 TSOP Lead Configuration for x8 x16 28F200BX
28F004BX
28F004BX
290448 20
Figure 5 TSOP Lead Configuration for x8 28F002BX
7
28F200BX-T B 28F002BX-T B
1 5 Pin Descriptions for the x8 x16 28F200BX
Symbol
Type
Name and Function
A
0
A
16
I
ADDRESS INPUTS
for memory addresses Addresses are internally latched
during a write cycle
A
9
I
ADDRESS INPUT
When A
9
is at 12V the signature mode is accessed During this
mode A
0
decodes between the manufacturer and device ID's When BYTE
is at
a logic low only the lower byte of the signatures are read DQ
15
A
b
1
is a don't
care in the signature mode when BYTE
is low
DQ
0
DQ
7
I O
DATA INPUTS OUTPUTS
Inputs array data on the second CE
and WE
cycle
during a program command Inputs commands to the Command User Interface
when CE
and WE
are active Data is internally latched during the write and
program cycles Outputs array Intelligent Identifier and Status Register data The
data pins float to tri-state when the chip is deselected or the outputs are disabled
DQ
8
DQ
15
I O
DATA INPUTS OUTPUTS
Inputs array data on the second CE
and WE
cycle
during a program command Data is internally latched during the write and program
cycles Outputs array data The data pins float to tri-state when the chip is
deselected or the outputs are disabled as in the byte-wide mode (BYTE
e
``0'')
In the byte-wide mode DQ
15
A
b
1
becomes the lowest order address for data
output on DQ
0
DQ
7
CE
I
CHIP ENABLE
Activates the device's control logic input buffers decoders and
sense amplifiers CE
is active low CE
high deselects the memory device and
reduces power consumption to standby levels If CE
and RP
are high but not
at a CMOS high level the standby current will increase due to current flow through
the CE
and RP
input stages
RP
I
RESET DEEP POWER-DOWN
Provides three-state control Puts the device in
deep power-down mode Locks the boot block from program erase
When RP
is at logic high level and equals 6 5V maximum the boot block is
locked and cannot be programmed or erased
When RP
e
11 4V minimum the boot block is unlocked and can be programmed
or erased
When RP
is at a logic low level the boot block is locked the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased therefore providing data protection during power
transitions When RP
transitions from logic low to logic high the flash memory
enters the read array mode
OE
I
OUTPUT ENABLE
Gates the device's outputs through the data buffers during a
read cycle OE
is active low
WE
I
WRITE ENABLE
Controls writes to the Command Register and array blocks
WE
is active low Addresses and data are latched on the rising edge of the WE
pulse
BYTE
I
BYTE
ENABLE
Controls whether the device operates in the byte-wide mode
(x8) or the word-wide mode (x16) BYTE
pin must be controlled at CMOS levels
to meet 100 mA CMOS current in the standby mode BYTE
e
``0'' enables the
byte-wide mode where data is read and programmed on DQ
0
DQ
7
and
DQ
15
A
b
1
becomes the lowest order address that decodes between the upper
and lower byte DQ
8
DQ
14
are tri-stated during the byte-wide mode
BYTE
e
``1'' enables the word-wide mode where data is read and programmed
on DQ
0
DQ
15
V
PP
PROGRAM ERASE POWER SUPPLY
For erasing memory array blocks or
programming data in each block
Note
V
PP
k
V
PPLMAX
memory contents cannot be altered
V
CC
DEVICE POWER SUPPLY (5V
g
10% 5V
g
5%)
GND
GROUND
For all internal circuitry
NC
NO CONNECT
Pin may be driven or left floating
DU
DON'T USE PIN
Pin should not be connected to anything
8
28F200BX-T B 28F002BX-T B
1 6 Pin Descriptions for x8 28F002BX
Symbol
Type
Name and Function
A
0
A
17
I
ADDRESS INPUTS
for memory addresses Addresses are internally latched during
a write cycle
A
9
I
ADDRESS INPUT
When A
9
is at 12V the signature mode is accessed During this
mode A
0
decodes between the manufacturer and device ID's
DQ
0
DQ
7
I O
DATA INPUTS OUTPUTS
Inputs array data on the second CE
and WE
cycle
during a program command Inputs commands to the command user interface
when CE
and WE
are active Data is internally latched during the write and
program cycles Outputs array Intelligent Identifier and status register data The
data pins float to tri-state when the chip is deselected or the outputs are disabled
CE
I
CHIP ENABLE
Activates the device's control logic input buffers decoders and
sense amplifiers CE
is active low CE
high deselects the memory device and
reduces power consumption to standby levels If CE
and RP
are high but not at
a CMOS high level the standby current will increase due to current flow through the
CE
and RP
input stages
RP
I
RESET DEEP POWERDOWN
Provides Three-State control Puts the device in
deep powerdown mode Locks the Boot Block from program erase
When RP
is at logic high level and equals 6 5V maximum the Boot Block is locked
and cannot be programmed or erased
When RP
e
11 4V minimum the Boot Block is unlocked and can be programmed
or erased
When RP
is at a logic low level the Boot Block is locked the deep powerdown
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased therefore providing data protection during power
transitions When RP
transitions from logic low to logic high the flash memory
enters the read-array mode
OE
I
OUTPUT ENABLE
Gates the device's outputs through the data buffers during a
read cycle OE
is active low
WE
I
WRITE ENABLE
Controls writes to the Command Register and array blocks WE
is active low Addresses and data are latched on the rising edge of the WE
pulse
V
PP
PROGRAM ERASE POWER SUPPLY
For erasing memory array blocks or
programming data in each block
Note
V
PP
k
V
PPLMAX
memory contents cannot be altered
V
CC
DEVICE POWER SUPPLY (5V
g
10% 5V
g
5%)
GND
GROUND
For all internal circuitry
NC
NO CONNECT
Pin may be driven or left floating
DU
DON'T USE PIN
Pin should not be connected to anything
9
28F200BX-T B 28F002BX-T B
2 0
28F200BX WORD BYTE-WIDE PRODUCTS DESCRIPTION
Figure 6 28F200BX Word Byte-Wide Block Diagram
290448
1
10
28F200BX-T B 28F002BX-T B
2 1 28F200BX Memory Organization
2 1 1 BLOCKING
The 28F200BX uses a blocked array architecture to
provide independent erasure of memory blocks A
block is erased independently of other blocks in the
array when an address is given within the block ad-
dress range and the Erase Setup and Erase Confirm
commands are written to the CUI The 28F200BX is
a random read write memory only erasure is per-
formed by block
2 1 1 1 Boot Block Operation and Data
Protection
The 16-Kbyte boot block provides a lock feature for
secure code storage The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of pow-
er failure or other disruption during code update
This lock feature ensures absolute data integrity by
preventing the boot block from being written or
erased when RP
is not at 12V The boot block can
be erased and written when RP
is held at 12V for
the duration of the erase or program operation This
allows customers to change the boot code when
necessary while providing security when needed
See the Block Memory Map section for address
locations of the boot block for the 28F200BX-T
and 28F200BX-B
2 1 1 2 Parameter Block Operation
The 28F200BX has 2 parameter blocks (8 Kbytes
each) The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information The pa-
rameter blocks can also be used to store additional
boot or main code The parameter blocks however
do not have the hardware write protection feature
that the boot block has The parameter blocks pro-
vide for more efficient memory utilization when deal-
ing with parameter changes versus regularly blocked
devices See the Block Memory Map section for ad-
dress locations of the parameter blocks for the
28F200BX-T and 28F200BX-B
2 1 1 3 Main Block Operation
Two main blocks of memory exist on the 28F200BX
(1 x 128 Kbyte block and 1 x 96-Kbyte block) See
the following section on Block Memory Map for the
address location of these blocks for the 28F200BX-T
and 28F200BX-B products
2 1 2 BLOCK MEMORY MAP
Two versions of the 28F200BX product exist to sup-
port two different memory maps of the array blocks
in order to accommodate different microprocessor
protocols for boot code location The 28F200BX-T
memory map is inverted from the 28F200BX-B
memory map
2 1 2 1 28F200BX-B Memory Map
The 28F200BX-B device has the 16-Kbyte boot
block located from 00000H to 01FFFH to accommo-
date those microprocessors that boot from the bot-
tom of the address map at 00000H
In the
28F200BX-B the first 8-Kbyte parameter block re-
sides in memory space from 02000H to 02FFFH
The second 8-Kbyte parameter block resides in
memory space from 03000H to 03FFFH
The
96-Kbyte main block resides in memory space from
04000H to 0FFFFH The 128-Kbyte main block re-
sides in memory space from 10000H to 1FFFFH
(word locations) See Figure 7
(Word Addresses)
1FFFFH
128-Kbyte MAIN BLOCK
0FFFFH
10000H
96-Kbyte MAIN BLOCK
03FFFH
04000H
8-Kbyte PARAMETER BLOCK
02FFFH
03000H
8-Kbyte PARAMETER BLOCK
01FFFH
02000H
16-Kbyte BOOT BLOCK
00000H
Figure 7 28F200BX-B Memory Map
11
28F200BX-T B 28F002BX-T B
2 1 2 2 28F200BX-T Memory Map
The 28F200BX-T device has the 16-Kbyte boot
block located from 1E000H to 1FFFFH to accommo-
date those microprocessors that boot from the top
of the address map In the 28F200BX-T the first
8-Kbyte parameter block resides in memory space
from 1D000H to 1DFFFH The second 8-Kbyte pa-
rameter block resides in memory space from
1C000H to 1CFFFH The 96-Kbyte main block re-
sides in memory space from 10000H to 1BFFFH
The 128-Kbyte main block resides in memory space
from 00000H to 0FFFFH as shown in Figure 8
(Word Addresses)
1FFFFH
16-Kbyte BOOT BLOCK
1DFFFH
1E000H
8-Kbyte PARAMETER BLOCK
1CFFFH
1D000H
8-Kbyte PARAMETER BLOCK
1BFFFH
1C000H
96-Kbyte MAIN BLOCK
0FFFFH
10000H
128-Kbyte MAIN BLOCK
00000H
Figure 8 28F200BX-T Memory Map
12
28F200BX-T B 28F002BX-T B
3 0
28F002BX BYTE-WIDE PRODUCTS DESCRIPTION
Figure 9 28F002BX Byte-Wide Block Diagram
290448
1
9
13
28F200BX-T B 28F002BX-T B
3 1 28F002BX Memory Organization
3 1 1 BLOCKING
The 28F002BX uses a blocked array architecture to
provide independent erasure of memory blocks A
block is erased independently of other blocks in the
array when an address is given within the block ad-
dress range and the Erase Setup and Erase Confirm
commands are written to the CUI The 28F002BX is
a random read write memory only erasure is per-
formed by block
3 1 1 1 Boot Block Operation and Data
Protection
The 16-Kbyte boot block provides a lock feature for
secure code storage The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of pow-
er failure or other disruption during code update
This lock feature ensures absolute data integrity by
preventing the boot block from being programmed
or erased when RP
is not at 12V The boot block
can be erased and programmed when RP
is held
at 12V for the duration of the erase or program oper-
ation This allows customers to change the boot
code when necessary while still providing security
when needed See the Block Memory Map section
for address locations of the boot block for the
28F002BX-T and 28F002BX-B
3 1 1 2 Parameter Block Operation
The 28F002BX has 2 parameter blocks (8 Kbytes
each) The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information The pa-
rameter blocks can also be used to store additional
boot or main code The parameter blocks however
do not have the hardware write protection feature
that the boot block has Parameter blocks provide
for more efficient memory utilization when dealing
with small parameter changes versus regularly
blocked devices See the Block Memory Map sec-
tion for address locations of the parameter blocks
for the 28F002BX-T and 28F002BX-B
3 1 1 3 Main Block Operation
Two main blocks of memory exist on the 28F002BX
(1 x 128-Kbyte block and 1 x 96-Kbyte block) See
the following section on Block Memory Map for
address
location
of
these
blocks
for
the
28F002BX-T and 28F002BX-B
3 1 2 BLOCK MEMORY MAP
Two versions of the 28F002BX product exist to sup-
port two different memory maps of the array blocks
in order to accommodate different microprocessor
protocols for boot code location The 28F002BX-T
memory map is inverted from the 28F002BX-B
memory map
3 1 2 1 28F002BX-B Memory Map
The 28F002BX-B device has the 16-Kbyte boot
block located from 00000H to 03FFFH to accommo-
date those microprocessors that boot from the bot-
tom of the address map at 00000H
In the
28F002BX-B the first 8-Kbyte parameter block re-
sides in memory from 04000H to 05FFFH The sec-
ond 8-Kbyte parameter block resides in memory
space from 06000H to 07FFFH The 96-Kbyte main
block resides in memory space from 08000H to
1FFFFH The 128-Kbyte main block resides in mem-
ory space from 20000H to 3FFFFH See Figure 10
3FFFFH
128-Kbyte MAIN BLOCK
1FFFFH
20000H
96-Kbyte MAIN BLOCK
07FFFH
08000H
8-Kbyte PARAMETER BLOCK
05FFFH
06000H
8-Kbyte PARAMETER BLOCK
03FFFH
04000H
16-Kbyte BOOT BLOCK
00000H
Figure 10 28F002BX-B Memory Map
14
28F200BX-T B 28F002BX-T B
3 1 2 2 28F002BX-T Memory Map
The 28F002BX-T device has the 16-Kbyte boot
block located from 3C000H to 3FFFFH to accom-
modate those microprocessors that boot from the
top of the address map In the 28F002BX-T the first
8-Kbyte parmeter block resides in memory space
from 3A000H to 3BFFFH The second 8-Kbyte pa-
rameter block resides in memory space from
38000H to 39FFFH The 96-Kbyte main block re-
sides in memory space from 20000H to 37FFFH
The 128-Kbyte main block resides in memory space
from 00000H to 1FFFFH
3FFFFH
16-Kbyte BOOT BLOCK
3BFFFH
3C000H
8-Kbyte PARAMETER BLOCK
39FFFH
3A000H
8-Kbyte PARAMETER BLOCK
37FFFH
38000H
96-Kbyte MAIN BLOCK
1FFFFH
20000H
128-Kbyte MAIN BLOCK
00000H
Figure 11 28F002BX-T Memory Map
4 0 PRODUCT FAMILY PRINCIPLES
OF OPERATION
Flash memory augments EPROM functionality with
in-circuit electrical write and erase The 2-Mbit flash
family utilizes a Command User Interface (CUI) and
internally generated and timed algorithms to simplify
write and erase operations
The CUI allows for 100% TTL-level control inputs
fixed power supplies during erasure and program-
ming and maximum EPROM compatibility
In the absence of high voltage on the V
PP
pin the
2-Mbit boot block flash family will only successfully
execute the following commands Read Array Read
Status Register Clear Status Register and Intelli-
gent Identifier mode The device provides standard
EPROM read standby and output disable opera-
tions Manufacturer Identification and Device Identi-
fication data can be accessed through the CUI or
through the standard EPROM A9 high voltage ac-
cess (V
ID
) for PROM programming equipment
The same EPROM read standby and output disable
functions are available when high voltage is applied
to the V
PP
pin In addition high voltage on V
PP
al-
lows write and erase of the device All functions as-
sociated with altering memory contents write and
erase Intelligent Identifier read and Read Status are
accessed via the CUI
The purpose of the Write State Machine (WSM) is to
completely automate the write and erasure of the
device The WSM will begin operation upon receipt
of a signal from the CUI and will report status back
through a Status Register The CUI will handle the
WE
interface to the data and address latches as
well as system software requests for status while the
WSM is in operation
4 1 28F200BX Bus Operations
Flash memory reads erases and writes in-system
via the local CPU All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles
15
28F200BX-T B 28F002BX-T B
Table 1 Bus Operations for WORD-WIDE Mode (BYTE
e
V
IH
)
Mode
Notes
RP
CE
OE
WE
A
9
A
0
V
PP
DQ
015
Read
1 2
V
IH
V
IL
V
IL
V
IH
X
X
X
D
OUT
Output Disable
V
IH
V
IL
V
IH
V
IH
X
X
X
High Z
Standby
V
IH
V
IH
X
X
X
X
X
High Z
Deep Power-Down
9
V
IL
X
X
X
X
X
X
High Z
Intelligent Identifier (Mfr)
3 4
V
IH
V
IL
V
IL
V
IH
V
ID
V
IL
X
0089H
Intelligent Identifier (Device)
3 4 5
V
IH
V
IL
V
IL
V
IH
V
ID
V
IH
X
2274H
2275H
Write
6 7 8
V
IH
V
IL
V
IH
V
IL
X
X
X
D
IN
Table 2 Bus Operations for BYTE-WIDE Mode (BYTE
e
V
IL
)
Mode
Notes
RP
CE
OE
WE
A
9
A
0
A
b
1
V
PP
DQ
07
DQ
814
Read
1 2 3
V
IH
V
IL
V
IL
V
IH
X
X
X
X
D
OUT
High Z
Output Disable
V
IH
V
IL
V
IH
V
IH
X
X
X
X
High Z
High Z
Standby
V
IH
V
IH
X
X
X
X
X
X
High Z
High Z
Deep Power-Down
9
V
IL
X
X
X
X
X
X
X
High Z
High Z
Intelligent Identifier (Mfr)
4
V
IH
V
IL
V
IL
V
IH
V
ID
V
IL
X
X
89H
High Z
Intelligent Identifier
4 5
V
IH
V
IL
V
IL
V
IH
V
ID
V
IH
X
X
74H
High Z
(Device)
75H
Write
6 7 8
V
IH
V
IL
V
IH
V
IL
X
X
X
X
D
IN
High Z
NOTES
1 Refer to DC Characteristics
2 X can be V
IL
or V
IH
for control pins and addresses V
PPL
or V
PPH
for V
PP
3 See DC characteristics for V
PPL
V
PPH
V
HH
V
ID
voltages
4 Manufacturer and Device codes may also be accessed via a CUI write sequence A
1
A
17
e
X
5 Device ID
e
2274H for 28F200BX-T and 2275H for 28F200BX-B
6 Refer to Table 4 for valid D
IN
during a write operation
7 Command writes for Block Erase or Word Byte Write are only executed when V
PP
e
V
PPH
8 To write or erase the boot block hold RP
at V
HH
9 RP
must be at GND
g
0 2V to meet the 1 2 mA maximum deep power-down current
16
28F200BX-T B 28F002BX-T B
4 2 28F002BX Bus Operations
Table 3 Bus Operations
Mode
Notes
RP
CE
OE
WE
A
9
A
0
V
PP
DQ
07
Read
1 2
V
IH
V
IL
V
IL
V
IH
X
X
X
D
OUT
Output Disable
V
IH
V
IL
V
IH
V
IH
X
X
X
High Z
Standby
V
IH
V
IH
X
X
X
X
X
High Z
Deep Power-Down
9
V
IL
X
X
X
X
X
X
High Z
Intelligent Identifier (Mfr)
3 4
V
IH
V
IL
V
IL
V
IH
V
ID
V
IL
X
89H
Intelligent Identifier (Device)
3 4 5
V
IH
V
IL
V
IL
V
IH
V
ID
V
IH
X
7CH
7DH
Write
6 7 8
V
IH
V
IL
V
IH
V
IL
X
X
X
D
IN
NOTES
1 Refer to DC Characteristics
2 X can be V
IL
or V
IH
for control pins and addresses V
PPL
or V
PPH
for V
PP
3 See DC characteristics for V
PPL
V
PPH
V
HH
V
ID
voltages
4 Manufacturer and Device codes may also be accessed via a CUI write sequence A
1
A
16
e
X
5 Device ID
e
7CH for 28F002BX-T and 7DH for 28F002BX-B
6 Refer to Table 4 for valid D
IN
during a write operation
7 Command writes for Block Erase or byte program are only executed when V
PP
e
V
PPH
8 Program or erase the Boot block by holding RP
at V
HH
9 RP
must be at GND
g
0 2V to meet the 1 2 mA maximum deep power-down current
4 3 Read Operations
The 2-Mbit boot block flash family has three user
read modes Array Intelligent Identifier and Status
Register Status Register read mode will be dis-
cussed in detail in the ``Write Operations'' section
During power-up conditions (V
CC
supply ramping) it
takes a maximum of 600 ns from when V
CC
is at
4 5V minimum to valid data on the outputs
4 3 1 READ ARRAY
If the memory is not in the Read Array mode it is
necessary to write the appropriate read mode com-
mand to the CUI The 2-Mbit boot block flash family
has three control functions all of which must be
logically active
to obtain data at the outputs
Chip-Enable CE
is the device selection control
Power-Down RP
is the device power control Out-
put-Enable OE
is the DATA INPUT OUTPUT
(DQ 0 15 or DQ 0 7 ) direction control and when
active is used to drive data from the selected memo-
ry on to the I O bus
4 3 1 1 Output Control
With OE
at logic-high level (V
IH
) the output from
the device is disabled and data input output pins
(DQ 0 15 or DQ 0 7 ) are tri-stated Data input is
then controlled by WE
4 3 1 2 Input Control
With WE
at logic-high level (V
IH
) input to the de-
vice is disabled Data Input Output pins (DQ- 0 15
or DQ 0 7 ) are controlled by OE
4 3 2 INTELLIGENT IDENTlFlERS
28F200BX Products
The manufacturer and device codes are read via the
CUI or by taking the A
9
pin to 12V Writing 90
H
to
the CUI places the device into Intelligent Identifier
read mode A read of location 00000
H
outputs the
manufacturer's identification code 0089H and loca-
tion 00001
H
outputs the device code 2274H for
28F200BX-T
2275H
for
28F200BX-B
When
BYTE
is at a logic low only the lower byte of the
above signatures is read and DQ
15
A
b
1
is a ``don't
care'' during Intelligent Identifier mode A read array
command must be written to the CUI to return to the
read array mode
17
28F200BX-T B 28F002BX-T B
28F002BX Products
The manufacturer and device codes are also read
via the CUI or by taking the A9 pin to 12V Writing
90
H
to the CUI places the device into Intelligent
Identifier read mode A read of location 00000
H
out-
puts the manufacturer's identification code 89H
and location 00001
H
outputs the device code 7CH
for 28F002BX-T 7DH for 28F002BX-B
4 4 Write Operations
Commands are written to the CUI using standard mi-
croprocessor write timings The CUl serves as the
interface between the microprocessor and the inter-
nal chip operation The CUI can decipher Read Ar-
ray Read Intelligent Identifier Read Status Register
Clear Status Register Erase and Program com-
mands In the event of a read command the CUI
simply points the read path at either the array the
intelligent identifier or the status register depending
on the specific read command given For a program
or erase cycle the CUI informs the write state ma-
chine that a write or erase has been requested Dur-
ing a program cycle the Write State Machine will
control the program sequences and the CUI will only
respond to status reads During an erase cycle the
CUI will respond to status reads and erase suspend
After the Write State Machine has completed its
task it will allow the CUI to respond to its full com-
mand set The CUI will stay in the current command
state until the microprocessor issues another com-
mand
The CUI will successfully initiate an erase or write
operation only when V
PP
is within its voltage range
Depending upon the application the system design-
er may choose to make the V
PP
power supply
switchable available only when memory updates
are desired The system designer can also choose
to ``hard-wire'' V
PP
to 12V The 2 Mbit boot block
flash family is designed to accommodate either de-
sign practice It is recommended that RP
be tied to
logical Reset for data protection during unstable
CPU reset function as described in the ``Product
Family Overview'' section
4 4 1 BOOT BLOCK WRITE OPERATIONS
In the case of Boot Block modifications (write and
erase) RP
is set to V
HH
e
12V typically in addi-
tion to V
PP
at high voltage However if RP
is not at
V
HH
when a program or erase operation of the boot
block is attempted the corresponding status register
bit (Bit 4 for Program and Bit 5 for Erase refer to
Table 5 for Status Register Definitions) is set to indi-
cate the failure to complete the operation
4 4 2 COMMAND USER INTERFACE (CUI)
The Command User Interface (CUI) serves as the
interface to the microprocessor The CUI points the
read write path to the appropriate circuit block as
described in the previous section After the WSM
has completed its task it will set the WSM Status bit
to a ``1'' which will also allow the CUI to respond to
its full command set Note that after the WSM has
returned control to the CUI the CUI will remain in its
current state
4 4 2 1 Command Set
Command
Device Mode
Codes
00
Invalid Reserved
10
Alternate Program Setup
20
Erase Setup
40
Program Setup
50
Clear Status Register
70
Read Status Register
90
Intelligent Identifier
B0
Erase Suspend
D0
Erase Resume Erase Confirm
FF
Read Array
4 4 2 2 Command Function Descriptions
Device operations are selected by writing specific
commands into the CUI Table 4 defines the 2-Mbit
boot block flash family commands
18
28F200BX-T B 28F002BX-T B
Table 4 Command Definitions
Command
Bus
Notes
First Bus Cycle
Second Bus Cycle
Cycles
Req'd
8
Operation Address Data Operation Address Data
Read Array Reset
1
1
Write
X
FFH
Intelligent Identifier
3
2 4
Write
X
90H
Read
IA
IID
Read Status Register
2
3
Write
X
70H
Read
X
SRD
Clear Status Register
1
Write
X
50H
Erase Setup Erase Confirm
2
5
Write
BA
20H
Write
BA
D0H
Word Byte Write Setup Write
2
6 7
Write
WA
40H
Write
WA
WD
Erase Suspend Erase Resume
2
Write
X
B0H
Write
X
D0H
Alternate Word Byte Write Setup Write
2
6 7
Write
WA
10H
Write
WA
WD
NOTES
1 Bus operations are defined in Tables 1 2 3
2 IA
e
Identifier Address 00H for manufacturer code 01H for device code
3 SRD
e
Data read from Status Register
4 IID
e
Intelligent Identifier Data
Following the Intelligent Identifier Command two read operations access manufacturer and device codes
5 BA
e
Address within the block being erased
6 WA
e
Address to be written
WD
e
Data to be written at location PA
7 Either 40H or 10H command is valid
8 When writing commands to the device the upper data bus DQ8 DQ15
e
X (28F200BX-only) which is either V
CC
or
V
SS
to avoid burning additional current
Invalid Reserved
These are unassigned commands It is not recom-
mended that the customer use any command other
than the valid commands specified above Intel re-
serves the right to redefine these codes for future
functions
Read Array (FFH)
This single write command points the read path at
the array If the host CPU performs a CE
OE
controlled read immediately following a two-write se-
quence that started the WSM then the device will
output status register contents If the Read Array
command is given after Erase Setup the device is
reset to read the array A two Read Array command
sequence (FFH) is required to reset to Read Array
after Program Setup
Inteligent Identifier (90H)
After this command is executed the CUI points the
output path to the Intelligent Identifier circuits Only
Intelligent Identifier values at addresses 0 and 1 can
be read (only address A0 is used in this mode all
other address inputs are ignored)
Read Status Register (70H)
This is one of the two commands that is executable
while the state machine is operating After this com-
mand is written a read of the device will output the
contents of the status register regardless of the ad-
dress presented to the device
The device automatically enters this mode after pro-
gram or erase has completed
Clear Status Register (50H)
The WSM can only set the Program Status and
Erase Status bits in the status register it can not
clear them Two reasons exist for operating the
status register in this fashion The first is a synchro-
nization The WSM does not know when the host
CPU has read the status register therefore it would
not know when to clear the status bits Secondly if
the CPU is programming a string of bytes it may be
more efficient to query the status register after pro-
gramming the string Thus if any errors exist while
programming the string the status register will return
the accumulated error status
19
28F200BX-T B 28F002BX-T B
Program Setup (40H or 10H)
This command simply sets the CUI into a state such
that the next write will load the address and data
registers Either 40H or 10H can be used for Pro-
gram Setup Both commands are included to ac-
commodate efforts to achieve an industry standard
command code set
Program
The second write after the program setup command
will latch addresses and data Also the CUI initiates
the WSM to begin execution of the program algo-
rithm While the WSM finishes the algorithm the de-
vice will output Status Register contents Note that
the WSM cannot be suspended during program-
ming
Erase Setup (20H)
Prepares the CUI for the Erase Confirm command
No other action is taken lf the next command is not
an Erase Confirm command then the CUI will set
both the Program Status and Erase Status bits of the
Status Register to a ``1'' place the device into the
Read Status Register state and wait for another
command
Erase Confirm (D0H)
If the previous command was an Erase Setup com-
mand then the CUI will enable the WSM to erase at
the same time closing the address and data latches
and respond only to the Read Status Register and
Erase Suspend commands While the WSM is exe-
cuting the device will output Status Register data
when OE
is toggled low Status Register data can
only be updated by toggling either OE
or CE
low
Erase Suspend (B0H)
This command only has meaning while the WSM is
executing an Erase operation and therefore will only
be responded to during an erase operation After
this command has been executed the CUl will set
an output that directs the WSM to suspend Erase
operations and then return to responding to only
Read Status Register or to the Erase Resume com-
mands Once the WSM has reached the Suspend
state it will set an output into the CUI which allows
the CUI to respond to the Read Array Read Status
Register and Erase Resume commands In this
mode the CUI will not respond to any other com-
mands The WSM will also set the WSM Status bit to
a ``1'' The WSM will continue to run idling in the
SUSPEND state regardless of the state of all input
control pins with the exclusion of RP
RP
will
immediately shut down the WSM and the remainder
of the chip During a suspend operation the data
and address latches will remain closed but the ad-
dress pads are able to drive the address into the
read path
Erase Resume (D0H)
This command will cause the CUI to clear the Sus-
pend state and set the WSM Status bit to a ``0'' but
only if an Erase Suspend command was previously
issued Erase Resume will not have any effect in all
other conditions
4 4 3 STATUS REGISTER
The 2-Mbit boot block flash family contains a status
register which may be read to determine when a pro-
gram or erase operation is complete and whether
that operation completed successfully The status
register may be read at any time by writing the Read
Status command to the CUI After writing this com-
mand all subsequent Read operations output data
from the status register until another command is
written to the CUI A Read Array command must be
written to the CUI to return to the Read Array mode
The status register bits are output on DQ 0 7
whether the device is in the byte-wide (x8) or word-
wide (x16) mode for the 28F200BX In the word-wide
mode the upper byte DQ 8 15 is set to 00H during
a Read Status command In the byte-wide mode
DQ 8 14 are tri-stated and DQ
15
A
b
1
retains the
low order address function
It should be noted that the contents of the status
register are latched on the falling edge of OE
or
CE
whichever occurs last in the read cycle This
prevents possible bus errors which might occur if the
contents of the status register change while reading
the status register CE
or OE
must be toggled
with each subsequent status read or the completion
of a program or erase operation will not be evident
The Status Register is the interface between the mi-
croprocessor and the Write State Machine (WSM)
When the WSM is active this register will indicate
the status of the WSM and will also hold the bits
indicating whether or not the WSM was successful in
performing the desired operation The WSM sets
status bits ``Three'' through ``Seven'' and clears bits
``Six'' and ``Seven'' but cannot clear status bits
``Three'' through ``Five'' These bits can only be
cleared by the controlling CPU through the use of
the Clear Status Register command
20
28F200BX-T B 28F002BX-T B
4 4 3 1 Status Register Bit Definition
Table 5 Status Register Definitions
WSMS
ESS
ES
PS
VPPS
R
R
R
7
6
5
4
3
2
1
0
NOTES
SR 7
e
WRITE STATE MACHINE STATUS
1
e
Ready
0
e
Busy
Write State Machine Status bit must first be checked to
determine byte word program or block erase completion
before the Program or Erase Status bits are checked for
success
SR 6
e
ERASE SUSPEND STATUS
1
e
Erase Suspended
0
e
Erase in Progress Completed
When Erase Suspend is issued WSM halts execution
and sets both WSMS and ESS bits to ``1'' ESS bit re-
mains set to ``1'' until an Erase Resume command is is-
sued
SR 5
e
ERASE STATUS
1
e
Error in Block Erasure
0
e
Successful Block Erase
When this bit is set to ``1'' WSM has applied the maxi-
mum number of erase pulses to the block and is still un-
able to successfully perform an erase verify
SR 4
e
PROGRAM STATUS
1
e
Error in Byte Word Program
0
e
Successful Byte Word Program
When this bit is set to ``1'' WSM has attempted but failed
to Program a byte or word
SR 3
e
V
PP
STATUS
1
e
V
PP
Low Detect Operation Abort
0
e
V
PP
OK
The V
PP
Status bit unlike an A D converter does not
provide continuous indication of V
PP
level The WSM in-
terrogates the V
PP
level only after the byte write or block
erase command sequences have been entered and in-
forms the system if V
PP
has not been switched on The
V
PP
Status bit is not guaranteed to report accurate feed-
back between V
PPL
and V
PPH
SR 2 SR 0
e
RESERVED FOR FUTURE ENHANCE-
MENTS
These bits are reserved for future use and should be
masked out when polling the Status Register
4 4 3 2 Clearing the Status Register
Certain bits in the status register are set by the write
state machine and can only be reset by the system
software These bits can indicate various failure con-
ditions By allowing the system software to control
the resetting of these bits several operations may
be performed (such as cumulatively programming
several bytes or erasing multiple blocks in se-
quence) The status register may then be read to
determine if an error occurred during that program-
ming or erasure series This adds flexibility to the
way the device may be programmed or erased To
clear the status register the Clear Status Register
command is written to the CUI Then any other
command may be issued to the CUI Note again that
before a read cycle can be initiated a Read Array
command must be written to the CUI to specify
whether the read data is to come from the array
status register or Intelligent Identifier
4 4 4 PROGRAM MODE
Program is executed by a two-write sequence The
Program Setup command is written to the CUI fol-
lowed by a second write which specifies the address
and data to be programmed The write state ma-
chine will execute a sequence of internally timed
events to
1 Program the desired bits of the addressed memo-
ry word (byte) and
2 Verify that the desired bits are sufficiently pro-
grammed
Programming of the memory results in specific bits
within a byte or word being changed to a ``0''
If the user attempts to program ``1''s there will be no
change of the memory cell content and no error oc-
curs
Similar to erasure
the status register indicates
whether programming is complete While the pro-
gram sequence is executing bit 7 of the status regis-
ter is a ``0'' The status register can be polled by
21
28F200BX-T B 28F002BX-T B
toggling either CE
or OE
to determine when the
program sequence is complete
Only the Read
Status Register command is valid while program-
ming is active
When programming is complete the status bits
which indicate whether the program operation was
successful should be checked If the programming
operation was unsuccessful Bit 4 of the status regis-
ter is set to a ``1'' to indicate a Program Failure lf Bit
3 is set then V
PP
was not within acceptable limits
and the WSM will not execute the programming se-
quence
The status register should be cleared before at-
tempting the next operation Any CUI instruction can
follow after programming is completed however it
must be recognized that reads from the memory
status register or Intelligent Identifier cannot be ac-
complished until the CUI is given the appropriate
command A Read Array command must first be giv-
en before memory contents can be read
Figure 12 shows a system software flowchart for de-
vice byte programming operation Figure 13 shows a
similar flowchart for device word programming oper-
ation (28F200BX-only)
4 4 5 ERASE MODE
Erasure of a single block is initiated by writing the
Erase Setup and Erase Confirm commands to the
CUI along with the addresses A 12 16
for the
28F200BX or A 12 17 for the 28F002BX identifying
the block to be erased These addresses are latched
internally when the Erase Confirm command is is-
sued Block erasure results in all bits within the block
being set to ``1''
The WSM will execute a sequence of internally
timed events to
1 Program all bits within the block
2 Verify that all bits within the block are sufficiently
programmed
3 Erase all bits within the block and
4 Verify that all bits within the block are sufficiently
erased
While the erase sequence is executing Bit 7 of the
status register is a ``0''
When the status register indicates that erasure is
complete the status bits which indicate whether the
erase operation was successful should be checked
If the erasure operation was unsuccessful Bit 5 of
the status register is set to a ``1'' to indicate an
Erase Failure If V
PP
was not within acceptable limits
after the Erase Confirm command is issued the
WSM will not execute an erase sequence instead
Bit 5 of the status register is set to a ``1'' to indicate
an Erase Failure and Bit 3 is set to a ``1'' to identify
that V
PP
supply voltage was not within acceptable
limits
The status register should be cleared before at-
tempting the next operation Any CUI instruction can
follow after erasure is completed however it must
be recognized that reads from the memory array
status register or Intelligent Identifier can not be ac-
complished until the CUI is given the appropriate
command A Read Array command must first be giv-
en before memory contents can be read
Figure 14 shows a system software flowchart for
Block Erase operation
4 4 5 1 Suspending and Resuming Erase
Since an erase operation typically requires 1 to 3
seconds to complete an Erase Suspend command
is provided This allows erase-sequence interruption
in order to read data from another block of the mem-
ory Once the erase sequence is started writing the
Erase Suspend command to the CUI requests that
the Write State Machine (WSM) pause the erase se-
quence at a predetermined point in the erase algo-
rithm The status register must be read to determine
when the erase operation has been suspended
At this point a Read Array command can be written
to the CUI in order to read data from blocks other
than that which is being suspended The only other
valid command at this time is the Erase Resume
command or Read Status Register operation
Figure 15 shows a system software flowchart detail-
ing the operation
During Erase Suspend mode the chip can go into a
pseudo-standby mode by taking CE
to V
IH
and the
active current is now a maximum of 10 mA If the
chip is enabled while in this mode by taking CE
to
V
IL
the Erase Resume command can be issued to
resume the erase operation
Upon completion of reads from any block other than
the block being erased the Erase Resume com-
mand must be issued When the Erase Resume
command is given the WSM will continue with the
erase sequence and complete erasing the block As
with the end of erase the status register must be
read cleared and the next instruction issued in or-
der to continue
4 4 6 EXTENDED CYCLING
Intel has designed extended cycling capability into
its ETOX III flash memory technology The 2-Mbit
boot block flash family is designed for 100 000 pro-
gram erase cycles on each of the five blocks The
combination of low electric fields clean oxide pro-
cessing and minimized oxide area per memory cell
subjected to the tunneling electric field results in
very high cycling capability
22
28F200BX-T B 28F002BX-T B
290448 6
Bus
Command
Comments
Operation
Write
Setup
Data
e
40H
Program
Address
e
Byte to be
programmed
Write
Program
Data to be programmed
Address
e
Byte to be
programmed
Read
Status Register Data
Toggle OE
or CE
to update
Status Register
Standby
Check SR 7
1
e
Ready 0
e
Busy
Repeat for subsequent bytes
Full status check can be done after each byte or after a
sequence of bytes
Write FFH after the last byte programming operation to
reset the device to Read Array Mode
Full Status Check Procedure
290448 7
Bus
Command
Comments
Operation
Standby
Check SR 3
1
e
V
PP
Low Detect
Standby
Check SR 4
1
e
Byte Program Error
SR 3 MUST be cleared if set during a program attempt
before further attempts are allowed by the Write State
Machine
SR 4 is only cleared by the Clear Status Register
Command in cases where multiple bytes are programmed
before full status is checked
If error is detected clear the Status Register before
attempting retry or other error recovery
Figure 12 Automated Byte Programming Flowchart
23
28F200BX-T B 28F002BX-T B
290448 8
Bus
Command
Comments
Operation
Write
Setup
Data
e
40H
Program
Address
e
Word to be
programmed
Write
Program
Data to be programmed
Address
e
Word to be
programmed
Read
Status Register Data
Toggle OE
or CE
to update
Status Register
Standby
Check SR 7
1
e
Ready 0
e
Busy
Repeat for subsequent words
Full status check can be done after each word or after a
sequence of words
Write FFH after the last word programming operation to
reset the device to Read Array Mode
Full Status Check Procedure
290448 9
Bus
Command
Comments
Operation
Standby
Check SR 3
1
e
V
PP
Low Detect
Standby
Check SR 4
1
e
Word Program Error
SR 3 MUST be cleared if set during a program attempt
before further attempts are allowed by the Write State
Machine
SR 4 is only cleared by the Clear Status Register
Command in cases where multiple words are programmed
before full status is checked
If error is detected clear the Status Register before
attempting retry or other error recovery
Figure 13 Automated Word Programming Flowchart
24
28F200BX-T B 28F002BX-T B
290448 10
Bus
Command
Comments
Operation
Write
Setup
Data
e
20H
Erase
Address
e
Within block to be
erased
Write
Erase
Data
e
D0H
Address
e
Within block to be
erased
Read
Status Register Data
Toggle OE
or CE
to update
Status Register
Standby
Check SR 7
1
e
Ready 0
e
Busy
Repeat for subsequent blocks
Full status check can be done after each block or after a
sequence of blocks
Write FFH after the last block erase operation to reset the
device to Read Array Mode
Full Status Check Procedure
290448 11
Bus
Command
Comments
Operation
Standby
Check SR 3
1
e
V
PP
Low Detect
Standby
Check SR 4 5
Both 1
e
Command Sequence
Error
Standby
Check SR 5
1
e
Block Erase Error
SR 3 MUST be cleared if set during an erase attempt
before further attempts are allowed by the Write State
Machine
SR 5 is only cleared by the Clear Status Register
Command in cases where multiple blocks are erased
before full status is checked
If error is detected clear the Status Register before
attempting retry or other error recovery
Figure 14 Automated Block Erase Flowchart
25
28F200BX-T B 28F002BX-T B
290448 12
Bus
Command
Comments
Operation
Write
Erase
Data
e
B0H
Suspend
Read
Status Register Data
Toggle OE
or CE
to
update Status Register
Standby
Check SR 7
1
e
Ready
Standby
Check SR 6
1
e
Suspended
Write
Read Array
Data
e
FFH
Read
Read array data from block
other than that being
erased
Write
Erase Resume
Data
e
D0H
Figure 15 Erase Suspend Resume Flowchart
4 5 Power Consumption
4 5 1 ACTIVE POWER
With CE
at a logic-low level and RP
at a logic-
high level the device is placed in the active mode
The device I
CC
current is a maximum of 60 mA at
10 MHz with TTL input signals
4 5 2 AUTOMATIC POWER SAVINGS
Automatic Power Savings (APS) is a low power fea-
ture during active mode of operation The 2-Mbit
family of products incorporate Power Reduction
Control (PRC) circuitry which basically allows the de-
vice to put itself into a low current state when it is
not being accessed After data is read from the
memory array PRC logic controls the device's pow-
er consumption by entering the APS mode where
maximum I
CC
current is 3 mA and typical I
CC
current
is 1 mA The device stays in this static state with
outputs valid until a new location is read
4 5 3 STANDBY POWER
With CE
at a logic-high level (V
IH
) and the CUI in
read mode the memory is placed in standby mode
where the maximum I
CC
standby current is 100 mA
with CMOS input signals The standby operation dis-
ables much of the device's circuitry and substantially
reduces device power consumption The outputs
(DQ 0 15 or DQ 0 7 ) are placed in a high-imped-
ance state independent of the status of the OE
signal When the 2-Mbit boot block flash family is
deselected during erase or program functions the
devices will continue to perform the erase or pro-
gram function and consume program or erase active
power until program or erase is completed
26
28F200BX-T B 28F002BX-T B
4 5 4 RESET DEEP POWER-DOWN
The 2-Mbit boot block flash family supports a typical
I
CC
of 0 2 mA in deep power-down mode One of the
target markets for these devices is in portable equip-
ment where the power consumption of the machine
is of prime importance The 2-Mbit boot block flash
family has a RP
pin which places the device in the
deep power-down mode When RP
is at a logic-
low (GND
g
0 2V) all circuits are turned off and the
device typically draws 0 2 mA of V
CC
current
During read modes the RP
pin going low dese-
lects the memory and places the output drivers in a
high impedance state Recovery from the deep pow-
er-down state requires a maximum of 300 ns to ac-
cess valid data (t
PHQV
)
During erase or program modes RP
low will abort
either erase or program operation The contents of
the memory are no longer valid as the data has been
corrupted by the RP
function As in the read mode
above all internal circuitry is turned off to achieve
the 0 2 mA current level
RP
transitions to V
IL
or turning power off to the
device will clear the status register
This use of RP
during system reset is important
with automated write erase devices When the sys-
tem comes out of reset it expects to read from the
flash memory Automated flash memories provide
status information when accessed during write
erase modes If a CPU reset occurs with no flash
memory reset proper CPU initialization would not
occur because the flash memory would be providing
the status information instead of array data Intel's
Flash Memories allow proper CPU initialization fol-
lowing a system reset through the use of the RP
input In this application RP
is controlled by the
same RESET
signal that resets the system CPU
4 6 Power-Up Operation
The 2-Mbit boot block flash family is designed to
offer protection against accidental block erasure or
programming during power transitions Upon power-
up the 2-Mbit boot block flash family is indifferent as
to which power supply V
PP
or V
CC
powers-up first
Power suppy sequencing is not required
The 2-Mbit boot block flash family ensures the CUI is
reset to the read mode on power-up
In addition on power-up the user must either drop
CE
low or present a new address to ensure valid
data at the outputs
A system designer must guard against spurious
writes for V
CC
voltages above V
LKO
when V
PP
is
active Since both WE
and CE
must be low for a
command write driving either signal to V
IH
will inhibit
writes to the device The CUI architecture provides
an added level of protection since alteration of mem-
ory contents can only occur after successful com-
pletion of the two-step command sequences Final-
ly the device is disabled until RP
is brought to V
IH
regardless of the state of its control inputs This fea-
ture provides yet another level of memory protec-
tion
4 7 Power Supply Decoupling
Flash memory's power switching characteristics re-
quire careful device decoupling methods System
designers are interested in 3 supply current issues
Standby current levels (I
CCS
)
Active current levels (I
CCR
)
Transient peaks produced by falling and rising
edges of CE
Transient current magnitudes depend on the device
outputs' capacitive and inductive loading Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks Each
flash device should have a 0 1 mF ceramic capacitor
connected between each V
CC
and GND and be-
tween its V
PP
and GND These high frequency low-
inherent inductance capacitors should be placed as
close as possible to the package leads
4 7 1 V
PP
TRACE ON PRINTED CIRCUIT
BOARDS
Writing to flash memories while they reside in the
target system requires special consideration of the
V
PP
power supply trace by the printed circuit board
designer The V
PP
pin supplies the flash memory
cell's current for programming and erasing One
should use similar trace widths and layout consider-
ations given to the V
CC
power supply trace Ade-
quate V
PP
supply traces and decoupling will de-
crease spikes and overshoots
4 7 2 V
CC
V
PP
AND RP
TRANSITIONS
The CUI latches commands as issued by system
software and is not altered by V
PP
or CE
tran-
sitions or WSM actions Its state upon power-up af-
ter exit from deep power-down mode or after V
CC
transitions below V
LKO
(Lockout voltage) is Read
Array mode
After any word byte write or block erase operation is
complete and even after V
PP
transitions down to
V
PPL
the CUI must be reset to Read Array mode via
the Read Array command when accesses to the
flash memory are desired
27
28F200BX-T B 28F002BX-T B
ABSOLUTE MAXIMUM RATINGS
Commercial Operating Temperature
During Read
0 C to 70 C
(1)
During Block Erase
and Word Byte Write
0 C to 70 C
Temperature Under Bias
b
10 C to a80 C
Extended Operating Temperature
During Read
b
40 C to a85 C
During Block Erase
and Word Byte Write
b
40 C to a85 C
Temperature Under Bias
b
40 C to a85 C
Storage Temperature
b
65 C to a125 C
Voltage on Any Pin
(except V
CC
V
PP
A
9
and RP )
with Respect to GND
b
2 0V to a7 0V
(2)
Voltage on Pin RP
or Pin A
9
with Respect to GND
b
2 0V to a13 5V
(2 3)
V
PP
Program Voltage with Respect
to GND during Block Erase
and Word Byte Write
b
2 0V to a14 0V
(2 3)
V
CC
Supply Voltage
with Respect to GND
b
2 0V to a7 0V
(2)
Output Short Circuit Current
100 mA
(4)
NOTICE This is a production data sheet The specifi-
cations are subject to change without notice
WARNING Stressing the device beyond the ``Absolute
Maximum Ratings'' may cause permanent damage
These are stress ratings only Operation beyond the
``Operating Conditions'' is not recommended and ex-
tended exposure beyond the ``Operating Conditions''
may affect device reliability
OPERATING CONDITIONS
Symbol
Parameter
Notes
Min
Max
Units
T
A
Operating Temperature
0
70
C
V
CC
V
CC
Supply Voltage (10%)
5
4 50
5 50
V
V
CC
V
CC
Supply Voltage (5%)
6
4 75
5 25
V
NOTES
1 Operating temperature is for commercial product defined by this specification
2 Minimum DC voltage is
b
0 5V on input output pins During transitions this level may undershoot to
b
2 0V for periods
k
20 ns Maximum DC voltage on input output pins is V
CC
a
0 5V which during transitions may overshoot to V
CC
a
2 0V for periods
k
20 ns
3 Maximum DC voltage on V
PP
may overshoot to
a
14 0V for periods
k
20 ns Maximum DC voltage on RP
or A
9
may
overshoot to 13 5V for periods
k
20 ns
4 Output shorted for no more than one second No more than one output shorted at a time
5 10% V
CC
specifications reference the 28F200BX-60 28F002BX-60 in their standard test configuration and the
28F200BX-80 28F002BX-80
6 5% V
CC
specifications reference the 28F200BX-60 28F002BX-60 in their high speed test configuration
DC CHARACTERISTICS
Symbol
Parameter
Notes
Min
Typ
Max
Unit
Test Condition
I
LI
Input Load Current
1
g
1 0
m
A
V
CC
e
V
CC
Max
V
IN
e
V
CC
or GND
I
LO
Output Leakage Current
1
g
10
m
A
V
CC
e
V
CC
Max
V
OUT
e
V
CC
or GND
28
28F200BX-T B 28F002BX-T B
DC CHARACTERISTICS
(Continued)
Symbol
Parameter
Notes Min Typ
Max
Unit
Test Condition
I
CCS
V
CC
Standby Current
1 3
1 5
mA V
CC
e
V
CC
Max
CE
e
RP
e
V
IH
100
m
A V
CC
e
V
CC
Max
CE
e
RP
e
V
CC
g
0 2V
28F200BX
BYTE
e
V
CC
g
0 2V or GND
I
CCD
V
CC
Deep Power-Down Current
1
0 20
1 2
m
A RP
e
GND
g
0 2V
I
CCR
V
CC
Read Current for
1 5
20
55
mA V
CC
e
V
CC
Max CE
e
GND
6 10
28F200BX Word-Wide and
f
(max)
e
10 MHz f
(typ)
e
5 MHz
Byte-Wide Mode and
I
OUT
e
0 mA CMOS Inputs
28F002BX Byte-Wide Mode
20
60
mA V
CC
e
V
CC
Max CE
e
GND
f
(max)
e
10 MHz f
(typ)
e
5 MHz
I
OUT
e
0 mA TTL Inputs
I
CCW
V
CC
Word Byte Write Current
1 4
65
mA Word Write in Progress
I
CCE
V
CC
Block Erase Current
1 4
30
mA Block Erase in Progress
I
CCES
V
CC
Erase Suspend Current
1 2
5
10
mA CE
e
V
IH
Block Erase Suspended
I
PPS
V
PP
Standby Current
1
g
15
m
A V
PP
s
V
CC
I
PPD
V
PP
Deep Power-Down Current
1
5 0
m
A RP
e
GND
g
0 2V RP
I
PPR
V
PP
Read Current
1
200
m
A V
PP
l
V
CC
I
PPW
V
PP
Word Write Current
1 4
40
mA V
PP
e
V
PPH
Word Write in Progress
I
PPW
V
PP
Byte Write Current
1 4
30
mA V
PP
e
V
PPH
Byte Write in Progress
I
PPE
V
PP
Block Erase Current
1 4
30
mA V
PP
e
V
PPH
Block Erase in Progress
I
PPES
V
PP
Erase Suspend Current
1
200
m
A V
PP
e
V
PPH
Block Erase Suspended
I
RP
RP
Boot Block Unlock Current 1 4
500
m
A RP
e
V
HH
I
ID
A
9
Intelligent Identifier Current
1 4
500
m
A A
9
e
V
ID
V
ID
A
9
Intelligent Identifier Voltage
11 5
13 0
V
V
IL
Input Low Voltage
b
0 5
0 8
V
V
IH
Input High Voltage
2 0
V
CC
a
0 5
V
V
OL
Output Low Voltage
0 45
V
V
CC
e
V
CC
Min
I
OL
e
5 8 mA
29
28F200BX-T B 28F002BX-T B
DC CHARACTERISTICS
(Continued)
Symbol
Parameter
Notes
Min
Typ Max Unit
Test Condition
V
OH1
Output High Voltage (TTL)
2 4
V
V
CC
e
V
CC
Min
I
OH
e b
2 5 mA
V
OH2
Output High Voltage (CMOS)
0 85 V
CC
V
V
CC
e
V
CC
Min
I
OH
e b
2 5 mA
V
CC
b
0 4
V
CC
e
V
CC
Min
I
OH
e b
100 mA
V
PPL
V
PP
during Normal Operations
3
0 0
6 5
V
V
PPH
V
PP
during Erase Write Operations
7
11 4
12 0 12 6
V
V
PPH
V
PP
during Erase Write Operations
8
10 8
12 0 13 2
V
V
LKO
V
CC
Erase Write Lock Voltage
2 0
V
V
HH
RP
Unlock Voltage
11 5
13 0
V
Boot Block Write Erase
NOTES
1 All currents are in RMS unless otherwise noted Typical values at V
CC
e
5 0V V
PP
e
12 0V T
e
25 C These currents
are valid for all product versions (packages and speeds)
2 I
CCES
is specified with the device deselected If the device is read while in Erase Suspend Mode current draw is the sum
of I
CCES
and I
CCR
3 Block Erases and Word Byte Writes are inhibited when V
PP
e
V
PPL
and not guaranteed in the range between V
PPH
and
V
PPL
4 Sampled not 100% tested
5 Automatic Power Savings (APS) reduces I
CCR
to less than 1 mA typical in static operation
6 CMOS Inputs are either V
CC
g
0 2V or GND
g
0 2V TTL Inputs are either V
IL
or V
IH
7 V
PP
e
12 0V
g
5% for applications requiring 100 000 block erase cycles
8 V
PP
e
12 0V
g
10% for applications requiring wider V
PP
tolerances at 100 block erase cycles
9 For the 28F002BX address pin A
10
follows the C
OUT
capacitance numbers
10 I
CCR
typical is 25 mA for X16 active read current
EXTENDED TEMPERATURE OPERATING CONDITIONS
Symbol
Parameter
Notes
Min
Max
Units
T
A
Operating Temperature
b
40
a
85
C
V
CC
V
CC
Supply Voltage (10%)
5
4 50
5 50
V
30
28F200BX-T B 28F002BX-T B
DC CHARACTERISTICS EXTENDED TEMPERATURE OPERATION
Symbol
Parameter
Notes Min Typ
Max Unit
Test Condition
I
LI
Input Load Current
1
g
1 0
m
A
V
CC
e
V
CC
Max
V
IN
e
V
CC
or GND
I
LO
Output Leakage Current
1
g
10
m
A
V
CC
e
V
CC
Max
V
OUT
e
V
CC
or GND
I
CCS
V
CC
Standby Current
1 3
1 5
mA V
CC
e
V
CC
Max
CE
e
RP
e
V
IH
100
m
A
V
CC
e
V
CC
Max
CE
e
RP
e
V
CC
g
0 2V
28F200BX
BYTE
e
V
CC
g
0 2V or GND
I
CCD
V
CC
Deep Power-Down Current
1
0 20
20
m
A
RP
e
GND
g
0 2V
I
CCR
V
CC
Read Current for
1 5
60
mA V
CC
e
V
CC
Max CE
e
GND
28F200BX Word-Wide and
6
f e 10 MHz I
OUT
e
0 mA
Byte-Wide Mode and
CMOS Inputs
28F002BX Byte-Wide Mode
65
mA V
CC
e
V
CC
Max CE
e
V
IL
f e 10 MHz I
OUT
e
0 mA
TTL Inputs
I
CCW
V
CC
Word Byte Write Current
1
70
mA Word Write in Progress
I
CCE
V
CC
Block Erase Current
1
40
mA Block Erase in Progress
I
CCES
V
CC
Erase Suspend Current
1 2
5
10
mA Block Erase Suspended
CE
e
V
IH
I
PPS
V
PP
Standby Current
1
g
15
m
A
V
PP
s
V
CC
I
PPD
V
PP
Deep Power-Down Current
1
5 0
m
A
RP
e
GND
g
0 2V
I
PPR
V
PP
Read Current
1
200
m
A
V
PP
l
V
CC
I
PPW
V
PP
Word Write Current
1 4
40
mA V
PP
e
V
PPH
Word Write in Progress
I
PPW
V
PP
Byte Write Current
1 4
30
mA V
PP
e
V
PPH
Byte Write in Progress
I
PPE
V
PP
Block Erase Current
1 4
30
mA V
PP
e
V
PPH
Block Erase in Progress
I
PPES
V
PP
Erase Suspend Current
1
200
m
A
V
PP
e
V
PPH
Block Erase Suspended
I
RP
RP
Boot Block Unlock Current
1 4
500
m
A
RP
e
V
HH
I
ID
A
9
Intelligent Identifier Current
1
500
m
A
A
9
e
V
ID
V
ID
A
9
Intelligent Identifier Voltage
11 5
13 0
V
31
28F200BX-T B 28F002BX-T B
DC CHARACTERISTICS EXTENDED TEMPERATURE OPERATION
(Continued)
Symbol
Parameter
Notes
Min
Typ
Max
Unit
Test Condition
V
IL
Input Low Voltage
b
0 5
0 8
V
V
IH
Input High Voltage
2 0
V
CC
a
0 5
V
V
OL
Output Low Voltage
0 45
V
V
CC
e
V
CC
Min
I
OL
e
5 8 mA
V
OH1
Output High Voltage (TTL)
2 4
V
V
CC
e
V
CC
Min
I
OH
e b
2 5 mA
V
OH2
Output High Voltage (CMOS)
0 85 V
CC
V
V
CC
e
V
CC
Min
I
OH
e b
2 5 mA
V
CC
b
0 4
V
CC
e
V
CC
Min
I
OH
e b
100 mA
V
PPL
V
PP
during Normal Operations
3
0 0
6 5
V
V
PPH
V
PP
during Erase Write Operations
7
11 4
12 0
12 6
V
V
PPH
V
PP
during Erase Write Operations
8
10 8
12 0
13 2
V
V
LKO
V
CC
Erase Write Lock Voltage
2 0
V
V
HH
RP
Unlock Voltage
11 5
13 0
V
Boot Block Write Erase
NOTES
1 All currents are in RMS unless otherwise noted Typical values at V
CC
e
5 0V V
PP
e
12 0V T
e
25 C These currents
are valid for all product versions (packages and speeds)
2 I
CCES
is specified with the device deselected If the device is read while in Erase Suspend Mode current draw is the sum
of I
CCES
and I
CCR
3 Block Erases and Word Byte Writes are inhibited when V
PP
e
V
PPL
and not guaranteed in the range between V
PPH
and
V
PPL
4 Sampled not 100% tested
5 Automatic Power Savings (APS) reduces I
CCR
to less than 1 mA typical in static operation
6 CMOS Inputs are either V
CC
g
0 2V or GND
g
0 2V TTL Inputs are either V
IL
or V
IH
7 V
PP
e
12 0V
g
5% for applications requiring 100 000 block erase cycles
8 V
PP
e
12 0V
g
10% for applications requiring wider V
PP
tolerances at 100 block erase cycles
9 For the 28F002BX address pin A
10
follows the C
OUT
capacitance numbers
10 I
CCR
typical is 25 mA for X16 active read current
32
28F200BX-T B 28F002BX-T B
CAPACITANCE
(1 2)
T
A
e
25 C f e 1 MHz
Symbol
Parameter
Typ
Max
Unit
Condition
C
IN
Input Capacitance
6
8
pF
V
IN
e
0V
C
OUT
Output Capacitance
10
12
pF
V
OUT
e
0V
NOTES
1 Sampled not 100% tested
2 For the 28F002BX address pin A
10
follows the C
OUT
capacitance numbers
STANDARD TEST CONFIGURATION
(1)
STANDARD AC INPUT OUTPUT REFERENCE WAVEFORM
290448 14
AC test inputs are driven at V
OH
(2 4 V
TTL
) for a Logic ``1'' and V
OL
(0 45 V
TTL
) for a logic ``0'' Input timing begins at V
IH
(2 0 V
TTL
) and V
IL
(0 8 V
TTL
) Output timing ends at V
IH
and V
IL
Input rise and fall times (10%
to 90%)
k
10 ns
STANDARD AC TESTING
LOAD CIRCUIT
290448 13
C
L
e
100 pF
C
L
Includes Jig Capacitance
R
L
e
3 3 KX
HIGH SPEED TEST CONFIGURATION
(2)
HIGH SPEED AC INPUT OUTPUT REFERENCE WAVEFORM
290448 22
AC test inputs are driven at 3 0V for a Logic ``1'' and 0 0V for a logic ``0''
Input timing begins and output timing ends at 1 5V Input rise and fall times
(10% to 90%)
k
10 ns
NOTES
1 Testing characteristics for 28F200BX-60 28F002BX-60 in standard test config-
uration and 28F200BX-80 28F002BX-80
2 Testing characteristics for 28F200BX-60 28F002BX-60 in high speed test con-
figuration
HIGH SPEED AC TESTING
LOAD CIRCUIT
290448 21
C
L
e
30 pF
C
L
Includes Jig Capacitance
R
L
e
3 3 KX
33
28F200BX-T B 28F002BX-T B
AC CHARACTERISTICS
Read Only Operations
(1)
Versions
V
CC
g
5%
V
CC
g
10%
Unit
28F200BX-60
(4)
28F200BX-60
(5)
28F200BX-80
(5)
28F200BX-120
(5)
28F002BX-60
(4)
28F002BX-60
(5)
28F002BX-80
(5)
28F002BX-120
(5)
Symbol
Parameter
Notes
Min
Max
Min
Max
Min
Max
Min
Max
t
AVAV
t
RC
Read Cycle Time
60
70
80
120
ns
t
AVQV
t
ACC
Address to
60
70
80
120
ns
Output Delay
t
ELQV
t
CE
CE
to Output Delay
2
60
70
80
120
ns
t
PHQV
t
PWH
RP
High to
300
300
300
300
ns
Output Delay
t
GLQV
t
OE
OE
to Output Delay
2
30
35
40
40
ns
t
ELQX
t
LZ
CE
to Output Low Z
3
0
0
0
0
ns
t
EHQZ
t
HZ
CE
High to Output
3
20
25
30
30
ns
High Z
t
GLQX
t
OLZ
OE
to Output Low Z
3
0
0
0
0
ns
t
GHQZ
t
DF
OE
High to Output
3
20
25
30
30
ns
High Z
t
OH
Output Hold from
3
0
0
0
0
ns
Addresses
CE
or OE
Change
Whichever is First
t
IR
Input Rise Time
10
10
10
10
ns
t
IF
Input Fall Time
10
10
10
10
ns
t
ELFL
CE
to BYTE
3
5
5
5
5
ns
t
ELFH
Switching
Low or High
t
FHQV
BYTE
Switching
3 6
60
70
80
120
ns
High to
Valid Output Delay
t
FLQZ
BYTE
Switching
3
20
25
30
30
ns
Low to
Output High Z
NOTES
1 See AC Input Output Reference Waveform for timing measurements
2 OE
may be delayed up to t
CE
t
OE
after the falling edge of CE
without impact on t
CE
3 Sampled not 100% tested
4 See High Speed Test Configuration
5 See Standard Test Configuration
6 t
FLQV
BYTE
switching low to valid output delay will be equal to t
AVQV
measured from the time DQ
15
A-
1
becomes
valid
34
28F200BX-T B 28F002BX-T B
EXTENDED TEMPERATURE OPERATIONS
AC CHARACTERISTICS
Read Only Operations
(1)
Versions
T28F200BX-80
(4)
Unit
T28F002BX-80
(4)
Symbol
Parameter
Notes
Min
Max
t
AVAV
t
RC
Read Cycle Time
80
ns
t
AVQV
t
ACC
Address to
80
ns
Output Delay
t
ELQV
t
CE
CE
to Output Delay
2
80
ns
t
PHQV
t
PWH
RP
High to
300
ns
Output Delay
t
GLQV
t
OE
OE
to Output Delay
2
40
ns
t
ELQX
t
LZ
CE
to Output Low Z
3
0
ns
t
EHQZ
t
HZ
CE
High to Output
3
30
ns
High Z
t
GLQX
t
OLZ
OE
to Output Low Z
3
0
ns
t
GHQZ
t
DF
OE
High to Output
3
30
ns
High Z
t
OH
Output Hold from
3
0
ns
Addresses
CE
or OE
Change
Whichever is First
t
IR
Input Rise Time
10
ns
t
IF
Input Fall Time
10
ns
t
ELFL
CE
to BYTE
3
5
ns
t
ELFH
Switching
Low or High
t
FHQV
BYTE
Switching
3 5
80
ns
High to
Valid Output Delay
t
FLQZ
BYTE
Switching
3
30
ns
Low to
Output High Z
NOTES
1 See AC Input Output Reference Waveform for timing measurements
2 OE
may be delayed up to t
CE
t
OE
after the falling edge of CE
without impact on t
CE
3 Sampled not 100% tested
4 See Standard Test Configuration
5 t
FLQV
BYTE
switching low to valid output delay will be equal to t
AVQV
measured from the time DQ
5
A-
1
becomes
valid
35
28F200BX-T B 28F002BX-T B
Figure 16 AC Waveforms for Read Operations
290448
1
5
36
28F200BX-T B 28F002BX-T B
290448 26
Figure 17 I
CC
(RMS) vs Frequency
(V
CC
e
5 5V) for x16 Operation
290448 27
Figure 18 I
CC
(RMS) vs Frequency
(V
CC
e
5 5V) for x8 Operation
290448 28
Figure 19 T
ACC
vs Output Load
Capacitance (V
CC
e
4 5V T e 70 C)
37
28F200BX-T B 28F002BX-T B
Figure 20 BYTE
Timing for Both Read and Write Operations for 28F200BX
290448
2
9
38
28F200BX-T B 28F002BX-T B
AC CHARACTERISTICS FOR WE -CONTROLLED WRITE OPERATIONS
(1)
Versions
V
CC
g
5%
V
CC
g
10%
Unit
28F200BX-60
(9)
28F200BX-60
(10)
28F200BX-80
(10)
28F200BX-120
(10)
28F002BX-60
(9)
28F002BX-60
(10)
28F002BX-80
(10)
28F002BX-120
(10)
Symbol
Parameter
Notes
Min
Max
Min
Max
Min
Max
Min
Max
t
AVAV
t
WC
Write Cycle Time
60
70
80
120
ns
t
PHWL
t
PS
RP
High
215
215
215
215
ns
Recovery to
WE
Going Low
t
ELWL
t
CS
CE
Setup to
0
0
0
0
ns
WE
Going Low
t
PHHWH
t
PHS
RP
V
HH
6 8
100
100
100
100
ns
Setup to
WE
Going High
t
VPWH
t
VPS
V
PP
Setup to
5 8
100
100
100
100
ns
WE
Going High
t
AVWH
t
AS
Address Setup to
3
50
50
50
50
ns
WE
Going High
t
DVWH
t
DS
Data Setup to
4
50
50
50
50
ns
WE
Going High
t
WLWH
t
WP
WE
Pulse Width
50
50
60
60
ns
t
WHDX
t
DH
Data Hold from
4
0
0
0
0
ns
WE
High
t
WHAX
t
AH
Address Hold
3
10
10
10
10
ns
from WE
High
t
WHEH
t
CH
CE
Hold from
10
10
10
10
ns
WE
High
t
WHWL
t
WPH
WE
Pulse
10
20
20
20
ns
Width High
t
WHQV1
Duration of
2 5
6
6
6
6
m
s
Word Byte Write
Operation
t
WHQV2
Duration of Erase 2 5 6
0 3
0 3
0 3
0 3
s
Operation (Boot)
t
WHQV3
Duration of Erase
2 5
0 3
0 3
0 3
0 3
s
Operation
(Parameter)
t
WHQV4
Duration of Erase 2 5 6
0 6
0 6
0 6
0 6
s
Operation (Main)
t
QVVL
t
VPH
V
PP
Hold from
5 8
0
0
0
0
ns
Valid SRD
39
28F200BX-T B 28F002BX-T B
AC CHARACTERISTICS FOR WE -CONTROLLED WRITE OPERATIONS
(1)
(Continued)
Versions
V
CC
g
5%
V
CC
g
10%
Unit
28F200BX-60
(9)
28F200BX-60
(10)
28F200BX-80
(10)
28F200BX-120
(10)
28F002BX-60
(9)
28F002BX-60
(10)
28F002BX-80
(10)
28F002BX-120
(10)
Symbol
Parameter
Notes
Min
Max
Min
Max
Min
Max
Min
Max
t
QVPH
t
PHH
RP
V
HH
Hold
6 8
0
0
0
0
ns
from Valid SRD
t
PHBR
Boot-Block
7 8
100
100
100
100
ns
Relock Delay
t
IR
Input Rise Time
10
10
10
10
ns
t
IF
Input Fall Time
10
10
10
10
ns
NOTES
1 Read timing characteristics during write and erase operations are the same as during read-only operations Refer to AC
characteristics during Read Mode
2 The on-chip WSM completely automates program erase operations program erase algorithms are now controlled inter-
nally which includes verify and margining operations
3 Refer to command definition table for valid A
IN
4 Refer to command definition table for valid D
IN
5 Program Erase durations are measured to valid SRD data (successful operation SR 7
e
1)
6 For Boot Block Program Erase RP
should be held at V
HH
until operation completes successfully
7 Time t
PHBR
is required for successful relocking of the Boot Block
8 Sampled but not 100% tested
9 See High Speed Test Configuration
10 See Standard Test Configuration
BLOCK ERASE AND WORD BYTE WRITE PERFORMANCE V
PP
e
12 0V
g
5%
Parameter
Notes
28F200BX-60
28F200BX-80
28F200BX-120
Unit
28F002BX-60
28F002BX-80
28F002BX-120
Min
Typ
(1)
Max
Min
Typ
(1)
Max
Min
Typ
(1)
Max
Boot Parameter
2
1 0
7
1 0
7
1 0
7
s
Block Erase Time
Main Block
2
2 4
14
2 4
14
2 4
14
s
Erase Time
Main Block Byte
2
1 2
4 2
1 2
4 2
1 2
4 2
s
Program Time
Main Block Word
2
0 6
2 1
0 6
2 1
0 6
2 1
s
Program Time
NOTES
1 25 C
2 Excludes System-Level Overhead
BLOCK ERASE AND WORD BYTE WRITE PERFORMANCE V
PP
e
12 0V
g
10%
Parameter
Notes
28F200BX-60
28F200BX-80
28F200BX-120
Unit
28F002BX-60
28F002BX-80
28F002BX-120
Min
Typ
(1)
Max
Min
Typ
(1)
Max
Min
Typ
(1)
Max
Boot Parameter
2
5 8
40
5 8
40
5 8
40
s
Block Erase Time
Main Block
2
14
60
14
60
14
60
s
Erase Time
Main Block Byte
2
6 0
20
6 0
20
6 0
20
s
Program Time
Main Block Word
2
3 0
10
3 0
10
3 0
10
s
Program Time
NOTES
1 25 C
2 Excludes System-Level Overhead
40
28F200BX-T B 28F002BX-T B
EXTENDED TEMPERATURE OPERATION
AC CHARACTERISTICS FOR WE -CONTROLLED WRITE OPERATIONS
(1)
Versions
(4)
T28F200BX-80
(9)
Unit
T28F002BX-80
(9)
Symbol
Parameter
Notes
Min
Max
t
AVAV
t
WC
Write Cycle Time
80
ns
t
PHWL
t
PS
RP
High Recovery to
220
ns
WE
Going Low
t
ELWL
t
CS
CE
Setup to WE
Going Low
0
ns
t
PHHWH
t
PHS
RP
V
HH
Setup to WE
Going High
6 8
100
ns
t
VPWH
t
VPS
V
PP
Setup to WE
Going High
5 8
100
ns
t
AVWH
t
AS
Address Setup to WE
Going High
3
60
ns
t
DVWH
t
DS
Data Setup to WE
Going High
4
60
ns
t
WLWH
t
WP
WE
Pulse Width
60
ns
t
WHDX
t
DH
Data Hold from WE
High
4
0
ns
t
WHAX
t
AH
Address Hold from WE
High
3
10
ns
t
WHEH
t
CH
CE
Hold from WE
High
10
ns
t
WHWL
t
WPH
WE
Pulse Width High
20
ns
t
WHQV1
Duration of Word Byte
2 5
7
m
s
Write Operation
t
WHQV2
Duration of Erase Operation (Boot)
2 5 6
0 4
s
t
WHQV3
Duration of Erase
2 5
0 4
s
Operation (Parameter)
t
WHQV4
Duration of Erase Operation (Main)
2 5 6
0 7
s
t
QVVL
t
VPH
V
PP
Hold from Valid SRD
5 8
0
ns
t
QVPH
t
PHH
RP
V
HH
Hold from Valid SRD
6 8
0
ns
t
PHBR
Boot-Block Relock Delay
7 8
100
ns
t
IR
Input Rise Time
10
ns
t
IF
Input Fall Time
10
ns
NOTES
1 Read timing characteristics during write and erase operations are the same as during read-only operations Refer to AC
characteristics during Read Mode
2 The on-chip WSM completely automates program erase operations program erase algorithms are now controlled inter-
nally which includes verify and margining operations
3 Refer to command definition table for valid A
IN
4 Refer to command definition table for valid D
IN
5 Program Erase durations are measured to valid SRD data (successful operation SR 7
e
1)
6 For Boot Block Program Erase RP
should be held at V
HH
until operation completes successfully
7 Time t
PHBR
is required for successful relocking of the Boot Block
8 Sampled but not 100% tested
9 See Standard Test Configuration
41
28F200BX-T B 28F002BX-T B
EXTENDED TEMPERATURE OPERATION
BLOCK ERASE AND WORD BYTE WRITE PERFORMANCE V
PP
e
12 0V
g
5%
Parameter
Notes
T28F200BX-80
Unit
T28F002BX-80
Min
Typ
(1)
Max
Boot Parameter
2
1 5
10 5
s
Block Erase Time
Main Block
2
3 0
18
s
Erase Time
Main Block Byte
2
1 4
5 0
s
Program Time
Main Block Word
2
0 7
2 5
s
Program Time
NOTES
1 25 C 12 0V V
PP
2 Excludes System-Level Overhead
42
28F200BX-T B 28F002BX-T B
Figure 21 AC Waveforms for Write and Erase Operations (WE -Controlled Writes)
290448
1
6
43
28F200BX-T B 28F002BX-T B
AC CHARACTERISTICS FOR CE -CONTROLLED WRITE OPERATIONS
(1 9)
Versions
V
CC
g
5%
V
CC
g
10%
Unit
28F200BX-60
(10)
28F200BX-60
(11)
28F200BX-80
(11)
28F200BX-120
(11)
28F002BX-60
(10)
28F002BX-60
(11)
28F002BX-80
(11)
28F002BX-120
(11)
Symbol
Parameter
Notes
Min
Max
Min
Max
Min
Max
Min
Max
t
AVAV
t
WC
Write Cycle Time
60
70
80
120
ns
t
PHEL
t
PS
RP
High Recovery
215
215
215
215
ns
to CE
Going Low
t
WLEL
t
WS
WE
Setup to CE
0
0
0
0
ns
Going Low
t
PHHEH
t
PHS
RP
V
HH
Setup to
6 8
100
100
100
100
ns
CE
Going High
t
VPEH
t
VPS
V
PP
Setup to CE
5 8
100
100
100
100
ns
Going High
t
AVEH
t
AS
Address Setup to
3
50
50
50
50
ns
CE
Going High
t
DVEH
t
DS
Data Setup to CE
4
60
60
60
60
ns
Going High
t
ELEH
t
CP
CE
Pulse Width
50
50
60
60
ns
t
EHDX
t
DH
Data Hold from
4
0
0
0
0
ns
CE
High
t
EHAX
t
AH
Address Hold
3
10
10
10
10
ns
from CE
High
t
EHWH
t
WH
WE
Hold from
10
10
10
10
ns
CE
High
t
EHEL
t
CPH
CE
Pulse
10
20
20
20
ns
Width High
t
EHQV1
Duration of
2 5
6
6
6
6
m
s
Word Byte
Programming
Operation
t
EHQV2
Duration of Erase
2 5 6
0 3
0 3
0 3
0 3
s
Operation (Boot)
t
EHQV3
Duration of Erase
2 5
0 3
0 3
0 3
0 3
s
Operation
(Parameter)
t
EHQV4
Duration of Erase
2 5
0 6
0 6
0 6
0 6
s
Operation (Main)
t
QVVL
t
VPH
V
PP
Hold from
5 8
0
0
0
0
ns
Valid SRD
t
QVPH
t
PHH
RP
V
HH
Hold
6 8
0
0
0
0
ns
from Valid SRD
t
PHBR
Boot-Block Relock
7
100
100
100
100
ns
Delay
t
IR
Input Rise Time
10
10
10
10
ns
t
IF
Input Fall Time
10
10
10
10
ns
NOTES
1 Chip-Enable Controlled Writes Write operations are driven by the valid combination of CE
and WE
in systems where
CE
defines the write pulse-width (within a longer WE
timing waveform) all set-up hold and inactive WE
time should
be measured relative to the CE
waveform
2 3 4 5 6 7 8 Refer to AC Characteristics notes for WE -Controlled Write Operations
9 Read timing characteristics during write and erase operations are the same as during read-only operations Refer to AC
Characteristics during Read Mode
10 See High Speed Test Configuration
11 See Standard Test Configuration
44
28F200BX-T B 28F002BX-T B
EXTENDED TEMPERATURE OPERATION
AC CHARACTERISTICS FOR CE -CONTROLLED WRITE OPERATIONS
(1 9)
Versions
T28F200BX-80
(10)
Unit
T28F002BX-80
(10)
Symbol
Parameter
Notes
Min
Max
t
AVAV
t
WC
Write Cycle Time
80
ns
t
PHEL
t
PS
RP
High Recovery
220
ns
to CE
Going Low
t
WLEL
t
WS
WE
Setup to CE
0
ns
Going Low
t
PHHEH
t
PHS
RP
V
HH
Setup to
6 8
100
ns
CE
Going High
t
VPEH
t
VPS
V
PP
Setup to CE
5 8
100
ns
Going High
t
AVEH
t
AS
Address Setup to
3
60
ns
CE
Going High
t
DVEH
t
DS
Data Setup to CE
4
60
ns
Going High
t
ELEH
t
CP
CE
Pulse Width
60
ns
t
EHDX
t
DH
Data Hold from
4
0
ns
CE
High
t
EHAX
t
AH
Address Hold
3
10
ns
from CE
High
t
EHWH
t
WH
WE
Hold from CE
High
10
ns
t
EHEL
t
CPH
CE
Pulse
20
ns
Width High
t
EHQV1
Duration of Word Byte
2 5
7
m
s
Programming
Operation
t
EHQV2
Duration of Erase
2 5 6
0 4
s
Operation (Boot)
t
EHQV3
Duration of Erase
2 5
0 4
s
Operation (Parameter)
t
EHQV4
Duration of Erase
2 5
0 7
s
Operation (Main)
t
QVVL
t
VPH
V
PP
Hold from
5 8
0
ns
Valid SRD
t
QVPH
t
PHH
RP
V
HH
Hold
6 8
0
ns
from Valid SRD
t
PHBR
Boot-Block Relock Delay
7
100
ns
t
IR
Input Rise Time
10
ns
t
IF
Input Fall Time
10
ns
NOTES
1 Ship-Enable Controlled Writes Write operations are driven by the valid combination of CE
and WE
in systems where
CE
defines the write pulse-width (within a longer WE
timing waveform) all set-up hold and inactive WE
time should
be measured relative to the CE
waveform
2 3 4 5 6 7 8 Refer to AC Characteristics for WE -Controlled Write Operations
9 Read timing characteristics during write and erase operations are the same as during read-only operations Refer to AC
Characteristics during Read Mode
10 See Standard Test Configuration
45
28F200BX-T B 28F002BX-T B
Figure 22 Alternate AC Waveforms for Write and Erase Operations (CE -Controlled Writes)
290448
1
7
46
28F200BX-T B 28F002BX-T B
ORDERING INFORMATION
290448 18
Valid Combinations
E28F200BX-T60
PA28F200BX-T60
E28F200BX-B60
PA28F200BX-B60
E28F200BX-T80
PA28F200BX-T80
TE28F200BX-T80
TB28F200BX-T80
E28F200BX-B80
PA28F200BX-B80
TE28F200BX-B80
TB28F200BX-B80
E28F200BX-T120
PA28F200BX-T120
E28F200BX-B120
PA28F200BX-B120
290448 23
Valid Combinations
E28F002BX-T60
E28F002BX-B60
E28F002BX-T80
TE28F002BX-T80
E28F002BX-B80
TE28F002BX-B80
E28F002BX-T120
E28F002BX-B120
ADDITIONAL INFORMATION
References
Order
Document
Number
290449
28F002 200BL-T B 2-Mbit Low Power Boot Block Flash Memory Datasheet
290450
28F004 400BL-T B 4-Mbit Low Power Boot Block Flash Memory Datasheet
290451
28F004 400BX-T B 4-Mbit Boot Block Flash Memory Datasheet
290531
2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
290530
4-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
290539
8-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
292098
AP-363 ``Extended Flash BIOS Concepts for Portable Computers''
292148
AP-604 ``Using Intel's Boot Block Flash Memory Parameter Blocks to Replace EEPROM''
292161
AP-608 ``Implementing a Plug
Play BIOS Using Intel's Boot Block Flash Memory''
292178
AP-623 ``Multi-Site Layout Planning Using Intel's Boot Block Flash Memory''
292130
AB-57 ``Boot Block Architecture for Safe Firmware Updates''
292154
AB-60 ``2 4 8-Mbit SmartVoltage Boot Block Flash Memory Family''
47
28F200BX-T B 28F002BX-T B
Revision History
Number
Description
-002
Removed b70 speed bin
Integrated b70 characteristics into b60 speed bin
Added Extended Temperature characteristics
Modified BYTE
Timing Diagram
Improved t
PHQV
RP
High to Output Delay and t
PHEL
RP
High Recovery to CE
going low
specifications
-003
PWD changed to RP
for JEDEC standardization compatibility
Combined V
CC
Read current for 28F200BX Word-wide mode and Byte-wide mode and
28F002BX Byte-wide mode in DC Characteristics tables
Change I
PPS
current spec from
g
10 mA to
g
15 mA in DC Characteristics tables
Improved I
CCR
and I
CCW
in DC Characteristics Extended Temperature Operation table
Improved t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
FHQV
and t
FLQZ
specifications for
Extended Temperature Operations AC Characteristics
Read and Write Operations
-004
Added specifications for 120 ns access time product version 28F200BX-120 and
28F002BX-120
Included permanent change on write timing parameters for -80 ns product versions Write
pulse width (t
WP
and t
CP
) increases from 50 ns to 60 ns Write pulse width high (t
WPH
and
t
CPH
) decreases from 30 ns to 20 ns Total write cycle time (t
WC
) remains unchanged
Added I
CCR
test condition note for typical frequency value in DC characteristics table
Added I
OH
CMOS specification
Added 28F400BX interface to Intel386
TM
EX Embedded Processor block diagram
Added description of how to upgrade to SmartVoltage Boot Block products
-005
Added references to input rise fall times
48