MOBILE CELERON

PROCESSOR IN MICRO-PGA AND

BGA PACKAGES AT 466 MHZ, 433 MHZ, 400 MHZ,

366 MHZ, 300 MHZ, AND 266 MHZ DATASHEET

Available at 266 MHz, 266 MHz at low
voltage, 300 MHz, 333 MHz, 366 MHz, 400
MHz, 433 MHz, and 466 MHz

Supports Intel Architecture with Dynamic
Execution

Integrated primary 16-Kbyte instruction
cache and 16-Kbyte write back data cache

Integrated second level cache (128-Kbyte)

Micro-PGA and BGA packaging technology

-- Supports thin form factor notebook

designs

-- Exposed die enables more efficient heat

dissipation

Fully compatible with previous Intel
microprocessors

-- Binary compatible with all applications

-- Support for MMXTM technology

Power Management Features

-- Quick Start and Deep Sleep modes

provide extremely low power
dissipation

Low-Power GTL+ processor system bus
interface

Integrated math co-processor

Integrated thermal diode

The Intel

Mobile CeleronTM (Micro-PGA and BGA) processor provides exceptional value to both businesses

and consumers. The mobile Celeron processor with multimedia enhancements and improved Internet and
communications capabilities not only provides an excellent solution for business but also a great choice for
home computing.

The Mobile Celeron (Micro-PGA and BGA) processor may contain design defects or errors know as errata
that may cause the product to deviate from published specifications. Current characterized errata are
available upon request.

ORDER NUMBER: 245112-005

MOBILE CELERONTM PROCESSOR IN MICRO-PGA AND BGA PACKAGES AT
466 MHZ, 433 MHZ, 400 MHZ, 366 MHZ, 333 MHZ, 300 MHZ, AND 266 MHZ DATASHEET

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document or by the sale of Intel products. Except as provided in
Intel's terms and conditions of sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or
implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular
purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving or life sustaining applications.

Intel retains the right to make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from
future changes to them. Contact your local sales office or your distributor to obtain the latest specifications before placing your
product order.

Mobile CeleronTM (Micro-PGA and BGA) processors may contain design defects or errors known as errata, which may cause
the product to deviate from published specifications. Current characterized errata are available upon request.

Copies of documents that have an ordering number and are referenced in this document, or other Intel literature, may be
obtained by calling 1-800-548-4725 or by visiting Intel's website at

http://www.intel.com

C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the

C bus/protocol and was developed by Intel. Implementations of the I

C bus/protocol or the SMBus bus/protocol may require

licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation.

* Third party brands and names are the property of their respective owners.

MOBILE CELERONTM PROCESSOR IN MICRO-PGA AND BGA PACKAGES AT

466 MHZ, 433 MHZ, 400 MHZ, 366 MHZ, 333 MHZ, 300 MHZ, AND 266 MHZ DATASHEET

INTEL CORPORATION

iii

CONTENTS

PAGE

1. INTRODUCTION .............................................. 1

1.1

Overview .................................................... 2

1.2

Terminology ............................................... 2

1.3

References ................................................ 2

2. MOBILE CELERON PROCESSOR FEATURES3

2.1

New Features in the Mobile Celeron
Processor................................................... 3

2.1.1

Integrated L2 Cache ......................... 3

2.1.2

Signal Differences from the Mini-
Cartridge Processors ........................ 3

2.2

Power Management ................................... 4

2.2.1

Clock Control Architecture ................ 4

2.2.2

Normal State .................................... 4

2.2.3

Auto Halt State ................................. 4

2.2.4

Stop Grant State............................... 6

2.2.5

Quick Start State .............................. 6

2.2.6

Halt/Grant Snoop State..................... 7

2.2.7

Sleep State....................................... 7

2.2.8

Deep Sleep State ............................. 7

2.2.9

Operating System Implications of
Quick Start and Sleep States............ 8

2.3

Low Power GTL+ ....................................... 8

2.3.1

GTL+ Signals.................................... 8

2.4

Mobile Celeron Processor CPUID .............. 8

3. ELECTRICAL SPECIFICATIONS .................. 10

3.1

Processor System Signals ....................... 10

3.1.1

Power Sequencing Requirements... 11

3.1.2

Test Access Port (TAP) Connection 12

3.1.3

Catastrophic Thermal Protection .... 12

3.1.4

Unused Signals .............................. 12

3.1.5

Signal State in Low Power States ... 12

3.2

Power Supply Requirements .................... 13

3.2.1

Decoupling Recommendations ....... 13

3.2.2

Voltage Planes ............................... 13

3.3

System Bus Clock and Processor
Clocking ................................................... 14

3.4

Maximum Ratings .................................... 15

3.5

DC Specifications..................................... 15

3.6

AC Specifications ..................................... 20

3.6.1

System Bus, Clock, APIC, TAP,
CMOS, and Open-drain AC
Specifications ................................. 20

4. SYSTEM SIGNAL SIMULATIONS ................. 34

4.1

System Bus Clock (BCLK) Signal Quality
Specifications........................................... 34

4.2

Low Power GTL+ Signal Quality
Specifications........................................... 35

4.3

Non-Low Power GTL+ Signal Quality
Specifications........................................... 36

4.3.1

Overshoot and Undershoot
Guidelines....................................... 36

4.3.2

Ringback Specification.................... 38

4.3.3

Settling Limit Guideline ................... 38

5. MECHANICAL SPECIFICATIONS ................. 39

5.1

Dimensions of the Micro-PGA Package ... 39

5.2

Dimensions of the BGA Package ............ 42

5.3

Signal Listings .......................................... 44

6. THERMAL SPECIFICATIONS........................ 57

6.1

Thermal Diode.......................................... 58

6.2

Case Temperature ................................... 59

7. PROCESSOR INITIALIZATION AND

CONFIGURATION.......................................... 60

7.1

Description ............................................... 60

7.1.1

Quick Start Enable.......................... 60

7.1.2

System Bus Frequency................... 60

7.1.3

APIC Disable .................................. 60

7.2

Clock Frequencies and Ratios.................. 60

8. PROCESSOR INTERFACE............................ 61

8.1

Alphabetical Signal Reference ................. 61

8.2

Signal Summaries .................................... 68

MOBILE CELERONTM PROCESSOR IN MICRO-PGA AND BGA PACKAGES AT
466 MHZ, 433 MHZ, 400 MHZ, 366 MHZ, 333 MHZ, 300 MHZ, AND 266 MHZ DATASHEET

INTEL CORPORATION

LIST OF FIGURES

PAGE

Figure 1.1 Signal Groups of a Mobile Celeron

Processor-Based System ...................... 1

Figure 2.1 Clock Control States ............................. 5
Figure 3.1 Ramp Rate Requirement .................... 11
Figure 3.2 PLL LC Filter ...................................... 13
Figure 3.3 Generic Clock Waveform.................... 27
Figure 3.4 Valid Delay Timings ............................ 28
Figure 3.5 Setup and Hold Timings ..................... 28
Figure 3.6 Reset and Configuration Timings........ 29
Figure 3.7 Power-on Reset Timings .................... 30
Figure 3.8 Test Timings (Boundary Scan) ........... 31
Figure 3.9 Test Reset Timings............................. 31
Figure 3.10 Quick Start/Deep Sleep Timing......... 32
Figure 3.11 Stop Grant/Sleep/Deep Sleep Timing33
Figure 4.1 BCLK Generic Clock Waveform ......... 35
Figure 4.2 Low to High, Low Power GTL+ Receiver

Ringback Tolerance ............................. 36

Figure 4.3 Non-GTL+ Overshoot/Undershoot and

Ringback.............................................. 37

Figure 5.1 Micro-PGA Package-Top and Side

View..................................................... 40

Figure 5.2 Micro-PGA Package-Bottom View ...... 41
Figure 5.3 Surface-mount BGA Package - Top and

Side View............................................. 43

Figure 5.4 Surface-mount BGA Package - Bottom

View..................................................... 44

Figure 5.5 Pin/Ball Map - Top View ..................... 45
Figure 6.1 Technique for Measuring Case

Temperature ........................................ 59

Figure 8.1 PWRGOOD Relationship at Power-On66

MOBILE CELERONTM PROCESSOR IN MICRO-PGA AND BGA PACKAGES AT

466 MHZ, 433 MHZ, 400 MHZ, 366 MHZ, 333 MHZ, 300 MHZ, AND 266 MHZ DATASHEET

INTEL CORPORATION

LIST OF TABLES

PAGE

Table 2.1 New Mobile Celeron Processor Signals . 3
Table 2.2 Removed Mini-Cartridge Processor

Signals................................................... 3

Table 2.3 Clock State Characteristics.................... 6
Table 2.4 Mobile Celeron Processor CPUID.......... 9
Table 2.5 Mobile Celeron Processor CPUID Cache

and TLB Descriptors .............................. 9

Table 3.1 System Signal Groups ......................... 10
Table 3.2 Recommended Resistors for Open-drain

Signals................................................. 11

Table 3.3 LC Filter Specifications ........................ 13
Table 3.4 Core Frequency to System Bus Ratio

Configuration ....................................... 14

Table 3.5 Mobile Celeron Processor Absolute

Maximum Ratings ................................ 15

Table 3.6 Mobile Celeron Processor Power

Specifications ...................................... 16

Table 3.7 Mobile Celeron Processor Power

Specifications ...................................... 17

Table 3.8 Low Voltage Mobile Celeron Processor

Power Specifications ........................... 18

Table 3.9 Low Power GTL+ Signal Group DC

Specifications ...................................... 19

Table 3.10. Low Power GTL+ Bus DC

Specifications ..................................... 19

Table 3.11 Clock, APIC, TAP, CMOS and Open-

Drain Signal Group DC Specifications . 20

Table 3.12 System Bus Clock AC Specifications. 21
Table 3.13 Valid Mobile Celeron Processor

Frequencies ......................................... 22

Table 3.14 Low Power GTL+ Signal Groups AC

Specifications ...................................... 22

Table 3.15 CMOS and Open-Drain Signal Groups

AC Specifications................................. 23

Table 3.16 Reset Configuration AC Specifications24
Table 3.17 TAP Signal AC Specifications ............ 25
Table 3.18 Quick Start/Deep Sleep AC

Specifications....................................... 26

Table 3.19 Stop Grant/Sleep/Deep Sleep AC

Specifications....................................... 26

Table 4.1 BCLK Signal Quality Specifications...... 34
Table 4.2 Low Power GTL+ Signal Group Ringback

Specification ........................................ 35

Table 4.3 Signal Ringback Specifications for Non-

GTL+ Signals ....................................... 38

Table 5.1 Micro-PGA Package Mechanical

Specifications....................................... 39

Table 5.2 Surface-mount BGA Package

Specifications....................................... 42

Table 5.3 Signal Listing in Order by Pin/Ball

Number................................................ 46

Table 5.4 Signal Listing in Order by Signal Name 52
Table 5.5 Voltage and No-Connect Pin/Ball

Locations ............................................. 56

Table 6.1 Mobile CeleronTM Processor Power

Specifications....................................... 57

Table 6.2 Thermal Diode Interface....................... 58
Table 6.3. Thermal Diode Specifications ............. 58
Table 8.1 Input Signals ........................................ 68
Table 8.2 Output Signals ..................................... 69
Table 8.3 Input/Output Signals (Single Driver) ..... 69
Table 8.4 Input/Output Signals (Multiple Driver)... 70

Электронный компонент: MOBILECELERONUPGA/BGA

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