ChipFind - документация

Электронный компонент:

Скачать:  PDF   ZIP
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
ACS573MS
Radiation Hardened Octal
Three-State Transparent Latch
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR,
CDIP2-T20, LEAD FINISH C
TOP VIEW
20 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR,
CDFP4-F20, LEAD FINISH C
TOP VIEW
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE
D0
D1
D2
D3
D4
D6
D5
D7
GND
VCC
Q1
Q2
Q3
Q0
Q4
Q5
Q6
Q7
LE
2
3
4
5
6
7
8
1
20
19
18
17
16
15
14
13
9
10
12
11
OE
D0
D1
D2
D3
D4
D6
D5
D7
GND
VCC
Q1
Q2
Q3
Q0
Q4
Q5
Q6
Q7
LE
Features
Devices QML Qualified in Accordance with MIL-PRF-38535
Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96724 and Intersil's QM Plan
1.25 Micron Radiation Hardened SOS CMOS
Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/Bit/Day
(Typ)
SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
2
/mg
Dose Rate Upset . . . . . . . . . . . . . . . . >10
11
RAD (Si)/s, 20ns Pulse
Dose Rate Survivability . . . . . . . . . . . >10
12
RAD (Si)/s, 20ns Pulse
Latch-Up Free Under Any Conditions
Military Temperature Range . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Significant Power Reduction Compared to ALSTTL Logic
DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
Input Current
1
A at VOL, VOH
Fast Propagation Delay . . . . . . . . . . . . . . . . 17ns (Max), 12ns (Typ)
Description
The Intersil ACS573MS is a Radiation Hardened Octal Transparent
Latch with an active low output enable. The outputs are transparent to
the inputs when the latch enable (LE) is High. When the latch goes low
the data is latched. The output enable controls the three-state outputs.
When the output enable pins (OE) are high the output is in a high
impedance state. The latch operation is independent of the state of
output enable.
The ACS573MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic family.
The ACS573MS is supplied in a 20 lead Ceramic Flatpack (K suffix) or a
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
5962F9672401VRC
-55
o
C to +125
o
C
MIL-PRF-38535 Class V
20 Lead SBDIP
5962F9672401VXC
-55
o
C to +125
o
C
MIL-PRF-38535 Class V
20 Lead Ceramic Flatpack
ACS573D/Sample
25
o
C
Sample
20 Lead SBDIP
ACS573K/Sample
25
o
C
Sample
20 Lead Ceramic Flatpack
ACS573HMSR
25
o
C
Die
Die
January 1996
Spec Number
518893
File Number
4093
2
ACS573MS
Functional Diagram
TRUTH TABLE
OE
LE
DATA
OUTPUT
L
H
H
H
L
H
L
L
L
L
l
L
L
L
h
H
H
X
X
Z
NOTE: L = Low Logic Level, H = High Logic Level, X = Don't Care, Z = High Impedance, l = Low Voltage Level Prior to High-to-Low Latch
Enable Transition, h = High Voltage Level Prior to High-to-Low Latch Enable Transition.
VCC
Qn
p
LE
LE
Dn
p
n
LE
LE
OE
p
n
LE
LE
LE
OE
OE
OE
n
OE
VSS
1 OF 8 IDENTICAL CIRCUITS
COMMON CONTROLS
Spec Number
518893
3
ACS573MS
Die Characteristics
DIE DIMENSIONS:
102 mils x 102 mils
2,600mm x 2,600mm
METALLIZATION:
Type: AlSi
Metal 1 Thickness: 7.125k
1.125k
Metal 2 Thickness: 9k
1k
GLASSIVATION:
Type: SiO
2
Thickness: 8k
1k
WORST CASE CURRENT DENSITY:
<2.0 x 10
5
A/cm
2
BOND PAD SIZE:
> 4.3 mils x 4.3 mils
> 110
m x 110
m
Metallization Mask Layout
ACS573MS
(1)
OE
(2) D0
(20) VCC
(16) Q3
GND (10)
LE (11)
Q7 (12)
NC
D2 (4)
D6 (8)
(14) Q5
(15) Q4
D3 (5)
NC
D4 (6)
NC
D5 (7)
D7 (9)
Q6 (13)
(17) Q2
NC
(3) D1
(18) Q1
(19) Q0
Spec Number
518893
4
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
ACS573MS
Spec Number