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File Number
4763
ACS175MS
Radiation Hardened Quad D-Type Flip-
Flop with Reset
The Radiation Hardened ACS175MS is a Quad D-Type
Flip-Flop with Reset. Information at the D input is
transferred to the Q and Q outputs on the positive-going
transition of the clock. All four flip-flops are controlled by a
common clock (CP) and a common reset (MR). Resetting is
accomplished by a LOW level independent of the clock. All
inputs are buffered and the outputs are designed for
balanced propagation delay and transition times.
The ACS175MS is fabricated on a CMOS Silicon on
Sapphire (SOS) process, which provides an immunity to
Single Event Latch-up and the capability of highly reliable
performance in any radiation environment. These devices
offer significant power reduction and faster performance
when compared to ALSTTL types.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Detailed Electrical Specifications for the ACS175MS are
contained in SMD 5962-98635. A "hot-link" is provided
on our homepage for downloading.
http://www.intersil.com/spacedefense/spaceselect.htm
Features
QML Qualified Per MIL-PRF-38535 Requirements
1.25 Micron Radiation Hardened SOS CMOS
Radiation Environment
- Latch-Up Free Under Any Conditions
- Total Dose (Max.) . . . . . . . . . . . . . . . . . 3 x 10
5
RAD(Si)
- SEU Immunity . . . . . . . . . . . . . <1 x 10
-10
Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm
2
)
Input Logic Levels. . . . V
IL
= (0.3)(V
CC
), V
IH
= (0.7)(V
CC
)
Output Current
. . . . . . . . . . . . . . . . . . . . . . . . . .
12mA (Min)
Quiescent Supply Current . . . . . . . . . . . . . . . 10
A (Max)
Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 22ns (Max)
Applications
High Speed Control Circuits
Sensor Monitoring
Low Power Designs
Ordering Information
ORDERING NUMBER
INTERNAL MARKETING
NUMBER
TEMP. RANGE (
o
C)
PACKAGE
DESIGNATOR
5962F9863501VCC
ACS175DMSR-03
-55 to 125
16 Ld SBDIP
CDIP2-T16
ACS175D/SAMPLE-03
ACS175D/SAMPLE-03
25
16 Ld SBDIP
CDIP2-T16
5962F9863501VXC
ACS175KMSR-03
-55 to 125
16 Ld Flatpack
CDFP4-F16
ACS175K/SAMPLE-03
ACS175K/SAMPLE-03
25
16 Ld Flatpack
CDFP4-F16
5962F9863501V9A
ACS175HMSR-03
25
Die
NA
Pinouts
ACS175MS
(SBDIP)
TOP VIEW
ACS175MS
(FLATPACK)
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
MR
Q0
Q0
D0
D1
Q1
GND
Q1
V
CC
Q3
D3
D2
Q2
Q2
CP
Q3
MR
Q0
Q0
D0
D1
Q1
Q1
GND
2
3
4
5
6
7
8
1
16
15
14
13
12
11
10
9
V
CC
Q3
Q3
D3
D2
Q2
Q2
CP
Data Sheet
July 1999
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
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All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
Die Characteristics
DIE DIMENSIONS:
Size: 2390
m x 2390
m (94 mils x 94 mils)
Thickness: 525
m
25
m (20.6 mils
1 mil)
Bond Pad: 110
m x 110
m (4.3 x 4.3 mils)
METALLIZATION: AI
Metal 1 Thickness: 0.7
m
0.1
m
Metal 2 Thickness: 1.0
m
0.1
m
SUBSTRATE POTENTIAL
Unbiased Insulator
PASSIVATION:
Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30
m
0.15
m
SPECIAL INSTRUCTIONS
Bond V
CC
First
ADDITIONAL INFORMATION:
Worst Case Current Density: <2.0 x 10
5
A/cm
2
Transistor Count: 280
Metallization Mask Layout
ACS175MS
Q0
MR
V
CC
Q3
Q0 (3)
D0 (4)
D1 (5)
Q1 (6)
(14) Q3
(13) D3
(12) D2
(11) Q2
(7)
(8)
(9)
(10)
(2)
(1)
(16)
(15)
Q2
CP
GND
Q1
ACS175MS
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