1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
Satellite Applications FlowTM (SAF) is a trademark of Intersil Corporation.
HS-303RH-T
Radiation Hardened
CMOS Dual SPDT Analog Switch
Intersil's Satellite Applications Flow
TM
(SAF) devices are fully
tested and guaranteed to 100kRAD Total Dose. These QML
Class T devices are processed to a standard flow intended
to meet the cost and shorter lead-time needs of large
volume satellite manufacturers, while maintaining a high
level of reliability.
The HS-303RH-T analog switch is a monolithic device
fabricated using Radiation Hardened CMOS technology and
the Intersil dielectric isolation process for latch-up free
operation. Improved total dose hardness is obtained by
layout (thin oxide tabs extending to a channel stop) and
processing (hardened gate oxide). This switch offers low-
resistance switching performance for analog voltages up to
the supply rails. "ON" resistance is low and stays reasonably
constant over the full range of operating voltage and current.
"ON" resistance also stays reasonably constant when
exposed to radiation, being typically 30
pre-rad and 35
post 100kRAD(Si). Break-before-make switching is
controlled by 5V digital inputs.
Specifications
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the HS-303RH-T
are contained in SMD 5962-95813. A "hot-link" is provided
from our website for downloading.
www.intersil.com/spacedefense/newsafclasst.asp
Intersil's Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
www.intersil.com/quality/manuals.asp
Features
QML Class T, Per MIL-PRF-38535
Radiation Performance
- Gamma Dose (
) 1 x 10
5
RAD(Si)
No Latch-Up, Dielectrically Isolated Device Islands
Pin for Pin Compatible with Intersil HI-303 Series Analog
Switches
Analog Signal Range 15V
Low Leakage . . . . . . . . . . . . . . . . 100nA (Max, Post Rad)
Low r
ON
. . . . . . . . . . . . . . . . . . . . . . 60
(Max, Post Rad)
Low Operating Power . . . . . . . . . . 100
A (Max, Post Rad)
Pinouts
HS1-303RH-T (SBDIP), CDIP2-T14
TOP VIEW
HS9-303RH-T (FLATPACK) CDFP3-F14
TOP VIEW
Ordering Information
ORDERING
NUMBER
PART
NUMBER
TEMP.
RANGE
(
o
C)
5962R9581301TCC
HS1-303RH-T
-55 to 125
5962R9581304TXC
HS9-303RH-T
-55 to 125
NOTE:
Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
NC
GND
V+
V-
1
2
3
4
5
6
7
14
13
12
11
10
9
8
IN1
S3
D3
D1
S4
D4
D2
IN2
S2
S1
NC
GND
IN1
S3
D3
D1
S1
V+
V-
S4
D4
D2
IN2
S2
14
13
12
11
10
9
8
2
3
4
5
6
7
1
Data Sheet
July 1999
File Number
4602.1
2
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Functional Diagram
Die Characteristics
DIE DIMENSIONS:
(2130
m x 1930
m x 279
m
25.4
m)
84 x 76 x 11mils
1mil
METALLIZATION:
Type: Al
Thickness: 12.5k
2k
SUBSTRATE POTENTIAL:
Unbiased (DI)
BACKSIDE FINISH:
Gold
PASSIVATION:
Type: Silox (S
i
O
2
)
Thickness: 8k
1k
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm
2
TRANSISTOR COUNT:
76
PROCESS:
Metal Gate CMOS, Dielectric Isolation
Metallization Mask Layout
HS-303RH-T
N
P
IN
D
SBDIP TRUTH TABLE
LOGIC
SW1AND SW2
SW3 AND SW4
0
OFF
ON
1
ON
OFF
D3
D1
S1
IN1
NC
GND
V-
D4
D2
S2
IN2
S3
V+
S4
HS-303RH-T
PDF 
ZIP