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CD4011BT
CMOS Quad 2-Input NAND Gate
Intersil's Satellite Applications Flow
TM
(SAF) devices are fully
tested and guaranteed to 100kRAD total dose. These QML
Class T devices are processed to a standard flow intended
to meet the cost and shorter lead-time needs of large
volume satellite manufacturers, while maintaining a high
level of reliability.
The CD4011BT, Quad 2-Input NAND gate provides the
system designer with direct implementation of the NAND
function and supplements the existing family of CMOS
gates. All inputs and outputs are buffered.
Specifications
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the CD4011BT are
contained in SMD 5962-96621. A "hot-link" is provided from
our website for downloading.
www.intersil.com/quality/manuals.asp
Intersil's Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
www.intersil.com/quality/manuals.asp
Features
QML Class T, Per MIL-PRF-38535
Radiation Performance
- Gamma Dose (
) 1 x 10
5
RAD(Si)
- SEP Effective LET > 75 MEV/gm/cm
2
Propagation Delay Time = 60ns (typ.) at CL = 50pF,
V
DD
= 10V
Buffered Inputs and Outputs
Standardized Symmetrical Output Characteristics
100% Tested for Maximum Quiescent Current at 20V
5V, 10V and 15V Parametric Ratings
Pinouts
CD4011BT (SBDIP), CDIP2-T14
TOP VIEW
CD4011BT (FLATPACK), CDFP3-F14
TOP VIEW
Ordering Information
ORDERING
NUMBER
PART
NUMBER
TEMP.
RANGE
(
o
C)
5962R9662101TCC
CD4011BDTR
-55 to 125
5962R9662101TXC
CD4011BKTR
-55 to 125
NOTE:
Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
A
B
J = AB
K = CD
C
D
V
SS
V
DD
H
G
M = GH
L = EF
E
F
1
2
3
4
5
6
7
14
13
12
11
10
9
8
14
13
12
11
10
9
8
2
3
4
5
6
7
1
A
B
J = AB
K = CD
C
D
V
SS
V
DD
H
G
M = GH
L = EF
E
F
Data Sheet
July 1999
File Number
4620.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
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All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
Die Characteristics
DIE DIMENSIONS:
(1143
m x 1626
m x 533
m
25.4
m)
45 x 64 x 21mils
1mil
METALLIZATION:
Type: Al
Thickness: 12.5k
1.5k
SUBSTRATE POTENTIAL:
Leave Floating or Tie to V
DD
Bond Pad #14 (V
DD
) First
BACKSIDE FINISH:
Silicon
PASSIVATION:
Type: Phosphorus Doped Silox (S
i
O
2
)
Thickness: 13k
2.6k
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm
2
TRANSISTOR COUNT:
10
PROCESS:
Bulk CMOS
Metallization Mask Layout
CD4011BT
45mils
64mils
CD4011BT
PDF 
ZIP