1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
Satellite Applications FlowTM (SAF) is a trademark of Intersil Corporation.
CD4015BT
CMOS Dual 4-Stage Static Shift Register
With Serial Input/Parallel Output
Intersil's Satellite Applications Flow
TM
(SAF) devices are fully
tested and guaranteed to 100kRAD total dose. These QML
Class T devices are processed to a standard flow intended
to meet the cost and shorter lead-time needs of large
volume satellite manufacturers, while maintaining a high
level of reliability.
CD4015BT consists of two identical, independent, 4-stage
serial-input/parallel output registers. Each register has
independent CLOCK and RESET inputs as well as a single
serial DATA input. "Q" outputs are available from each of the
four stages on both registers. All register stages are D type,
master-slave flip-flops. The logic level present at the DATA
input is transferred into the first register stage and shifted
over one stage at each positive-going clock transition.
Resetting of all stages is accomplished by a high level on the
reset line. Register expansion to 8 stages using one
CD4015BT, or to more than 8 stages using additional
CD4015BT's is possible.
Specifications
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the CD4015BT are
contained in SMD 5962-96624. A "hot-link" is provided from
our website for downloading.
www.intersil.com/spacedefense/newsafclasst.asp
Intersil's Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
www.intersil.com/quality/manuals.asp
Features
QML Class T, Per MIL-PRF-38535
Radiation Performance
- Gamma Dose (
) 1 x 10
5
RAD(Si)
- SEP Effective LET > 75 MEV/gm/cm
2
Medium Speed Operation 12MHz (typ.) Clock Rate at V
DD
- V
SS
= 10V
Fully Static Operation
8 Master-Slave Flip-Flops Plus Input and Output Buffering
100% Tested For Quiescent Current at 20V
5V, 10V and 15V Parametric Ratings
Standardized Symmetrical Output Characteristics
Pinouts
CD4015BT (SBDIP), CDIP2-T16
TOP VIEW
CD4015BT (FLATPACK), CDFP4-F16
TOP VIEW
Ordering Information
ORDERING
NUMBER
PART
NUMBER
TEMP.
RANGE
(
o
C)
5962R9662401TEC
CD4015BDTR
-55 to 125
5962R9662401TXC
CD4015BKTR
-55 to 125
NOTE:
Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
CLOCK B
Q4B
Q3A
Q2A
Q1A
RESET A
V
SS
DATA A
V
DD
RESET B
Q1B
Q2B
Q3B
Q4A
CLOCK A
DATA B
CLOCK B
Q4B
Q3A
Q2A
Q1A
RESET A
DATA A
V
SS
2
3
4
5
6
7
8
1
16
15
14
13
12
11
10
9
V
DD
DATA B
RESET B
Q1B
Q2B
Q3B
Q4A
CLOCK A
Data Sheet
July 1999
File Number
4621.1
3
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Die Characteristics
DIE DIMENSIONS:
(2032
m x 2489
m x 533
m
25.4
m)
80 x 98 x 21mils
1mil
METALLIZATION:
Type: Al
Thickness: 12.5k
1.5k
SUBSTRATE POTENTIAL:
Leave Floating or Tie to V
DD;
Bond Pad #16 (V
DD
) First
BACKSIDE FINISH:
Silicon
PASSIVATION:
Type: Phosphorus Doped Silox (S
i
O
2
)
Thickness: 13k
2.6k
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm
2
TRANSISTOR COUNT:
60
PROCESS:
Bulk CMOS
Metallization Mask Layout
CD4015BT
13
3
14
15
12
11
10
2
1
16
4
5
6
7
8
9
98mils
80mils
CD4015BT
PDF 
ZIP