1
ACTS541T
Radiation Hardened Octal Three-State
Buffer/Line Driver
Intersil's Satellite Applications Flow
TM
(SAF) devices are fully
tested and guaranteed to 100kRAD total dose. These QML
Class T devices are processed to a standard flow intended
to meet the cost and shorter lead-time needs of large
volume satellite manufacturers, while maintaining a high
level of reliability.
The Intersil ACTS541T is a Radiation Hardened Octal
Buffer/Line Driver, with three-state outputs. The output
enable pins OE1, OE2 control the three-state outputs. If
either enable is high the output will be in a high impedance
state. For data output both enables must be low.
Specifications
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the ACTS541T are
contained in SMD 5962-96726. A "hot-link" is provided from
our website for downloading.
www.intersil.com/spacedefense/newsafclasst.asp
Intersil's Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
www.semi.intersil.com/quality/manuals.asp
Features
QML Class T, Per MIL-PRF-38535
Radiation Performance
- Gamma Dose (
) 1 x 10
5
RAD(Si)
- Latch-Up Free Under Any Conditions
- Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/Bit/Day (Typ)
- SEU LET Threshold . . . . . . . . . . . . .>100 MEV-cm
2
/mg
1.25 Micron Radiation Hardened SOS CMOS
Significant Power Reduction Compared to ALSTTL Logic
DC Operating Voltage Range . . . . . . . . . . . . 4.5V to 5.5V
Input Logic Levels
- V
IL
= 0.8V Max
- V
IH
= VCC/2 Min
Fast Propagation Delay . . . . . . . . 21ns (Max), 14ns (Typ)
Pinouts
ACTS541T (SBDIP), CDIP2-T20
TOP VIEW
ACTS541T (FLATPACK), CDFP4-F20
TOP VIEW
Ordering Information
ORDERING
NUMBER
PART
NUMBER
TEMP.
RANGE
(
o
C)
5962R9672602TRC
ACTS541DTR-02
-55 to 125
5962R9672602TXC
ACTS541KTR-02
-55 to 125
NOTE:
Minimum order quantity for -T is 150 units through
distribution, or 450 units direct
.
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE1
A0
A1
A2
A3
A4
A6
A5
A7
GND
V
CC
Y0
Y1
Y2
OE2
Y3
Y4
Y5
Y6
Y7
2
3
4
5
6
7
8
1
20
19
18
17
16
15
14
13
OE1
A0
A1
A2
A3
A4
A5
A6
9
10
12
11
A7
GND
V
CC
Y0
Y1
Y2
OE2
Y3
Y4
Y5
Y6
Y7
Data Sheet
July 1999
File Number
4612.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
3
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Die Characteristics
DIE DIMENSIONS:
(2600
m x 2600
m x 533
m
51
m)
102 x 102 x 21mils
2mil
METALLIZATION:
Type: Al Si Cu
Thickness: 10.0k
2k
SUBSTRATE POTENTIAL:
Unbiased (Silicon on Sapphire)
Bond Pad #20 (V
CC
) First
BACKSIDE FINISH:
Sapphire
PASSIVATION:
Type: Silox (S
i
O
2
)
Thickness: 8.0k
1.0k
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm
2
TRANSISTOR COUNT:
182
PROCESS:
CMOS SOS
Metallization Mask Layout
ACTS541T
(1)
OE1
(2) A0
(20) V
CC
(16) Y2
GND (10)
Y7 (11)
Y6 (12)
NC
A2 (4)
A6 (8)
(14) Y4
(15) Y3
A3 (5)
NC
A4 (6)
NC
A5 (7)
A7 (9)
Y5 (13)
(17) Y1
NC
(3) A1
(18) Y
O
(19)
OE2
ACTS541T
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