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Электронный компонент: 82C82

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4-274
March 1997
82C82
CMOS Octal Latching Bus Driver
Features
Full Eight-Bit Parallel Latching Buffer
Bipolar 8282 Compatible
Three-State Noninverting Outputs
Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max.
Gated Inputs:
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
Single 5V Power Supply
Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10
A
Operating Temperature Ranges
- C82C82 . . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to +70
o
C
- I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
- M82C82 . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Description
The Intersil 82C82 is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon
gate CMOS process (Scaled SAJI IV). The 82C82 provides
an eight-bit parallel latch/buffer in a 20 pin package. The
active high strobe (STB) input allows transparent transfer of
data and latches data on the negative transition of this sig-
nal. The active low output enable (OE) permits simple inter-
face to state-of-the-art microprocessor systems.
Ordering Information
PART NUMBER
TEMP. RANGE
PACKAGE
PKG. NO.
CP82C82
0
o
C to +70
o
C
20 Ld PDIP
E20.3
IP82C82
-40
o
C to +85
o
C
CS82C82
0
o
C to +70
o
C
20 Ld PLCC
N20.35
IS82C82
-40
o
C to +85
o
C
CD82C82
0
o
C to +70
o
C
20 Ld CERDIP
F20.3
ID82C82
-40
o
C to +85
o
C
MD82C82/B
-55
o
C to +125
o
C
8406701RA
SMD #
MR82C82/B
-55
o
C to +125
o
C 20 Pad CLCC
J20.A
84067012A
SMD #
Pinouts
82C82 (PDIP, CERDIP)
TOP VIEW
82C82 (PLCC, CLCC)
TOP VIEW
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
7
DI
6
OE
GND
V
CC
DO
1
DO
2
DO
3
DO
0
DO
4
DO
5
DO
6
DO
7
STB
19
3
2
20
1
15
16
17
18
14
9
10
11
12
13
4
5
6
7
8
DI
4
DI
5
DI
6
DI
7
DI
3
OE
GND
STB
DO
7
DO
6
DO
2
DO
3
DO
4
DO
5
DO
1
DI
2
DI
1
DI
0
V
CC
DO
0
TRUTH TABLE
STB
OE
DI
DO
X
H
X
Hi-Z
H
L
L
L
H
L
H
H
L
X
H
= Logic One
L
= Logic Zero
X
= Don't Care
= Latched to Value of Last
Data
Hi-Z = High Impedance
= Neg. Transition
PIN NAMES
PIN
DESCRIPTION
DI
0
-DI
7
Data Input Pins
DO
0
-DO
7
Data Output Pins
STB
Active High Strobe
OE
Active Low Output
Enable
File Number
2975.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
4-275
Functional Diagram
Gated Inputs
During normal system operation of a latch, signals on the bus
at the device inputs will become high impedance or make
transitions unrelated to the operation of the latch. These unre-
lated input transitions switch the input circuitry and typically
cause an increase in power dissipation in CMOS devices by
creating a low resistance path between V
CC
and GND when
the signal is at or near the input switching threshold. Addition-
ally, if the driving signal becomes high impedance ("float" con-
dition), it could create an indeterminate logic state at the input
and cause a disruption in device operation.
The Intersil 82C8X Series of bus drivers eliminates these con-
ditions by turning off data inputs when data is latched (STB =
logic zero for the 82C82/83H) and when the device is disabled
(OE =
logic one for 82C86H/87H). These gated inputs dis-
connect the input circuitry from the V
CC
and ground power
supply pins by turning off the upper P-channel and lower N-
channel (see Figures 1, 2). No new current flow from V
CC
to
GND occurs during input transitions and invalid logic states
from floating inputs are not transmitted. The next stage is held
to a valid logic level internal to the device.
DC input voltage levels can also cause an increase in ICC if
these input levels approach the minimum V
IH
or maximum
V
IL
conditions. This is due to the operation of the input cir-
cuitry in its linear operating region (partially conducting
state). The 82C8X series gated inputs mean that this condi-
tion will occur only during the time the device is in the trans
parent mode (STB = logic one). ICC remains below the max-
imum ICC standby specification of l0mA during the time
inputs are disabled, thereby, greatly reducing the average
power dissipation of the 82C8X series devices
Typical 82C82 System Example
In a typical 80C86/88 system, the 82C82 is used to latch
multiplexed addresses and the STB input is driven by ALE
(Address Latch Enable) (see Figure 3). The high pulse width
of ALE is approximately 100ns with a bus cycle time of
800ns (80C86/88 at 5MHz). The 82C82 inputs are active
only 12.5% of the bus cycle time. Average power dissipation
related to input transitioning is reduced by this factor also.
DI
O
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
DO
0
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
OE
STB
D Q
CLK
FIGURE 16. 82C82/83H
FIGURE 17. 82C86H/87H GATED INPUTS
P
P
P
N
N
N
STB
DATA IN
INTERNAL
DATA
V
CC
V
CC
P
P
N
N
OE
DATA IN
INTERNAL
DATA
V
CC
P
N
V
CC
82C82
4-276
Application Information
Decoupling Capacitors
The transient current required to charge and discharge the
300pF load capacitance specified in the 82C82 data sheet is
determined by:
Assuming that all outputs change state at the same time and
that dv/dt is constant;
where tR = 20ns, V
CC
= 5.0V, C
L
= 300pF on each of eight
outputs.
This current spike may cause a large negative voltage spike
on V
CC
, which could cause improper operation of the device.
To filter out this noise, it is recommended that a 0.1
F
ceramic disc decoupling capacitor be placed between V
CC
and GND at each device, with placement being as near to
the device as possible.
I
C
L
=
(dv/dt)
(EQ. 1)
I
C
L
=
(EQ. 2)
V
CC
x 80%
(
)
tR/tF
-----------------------------------
(EQ. 3)
I = 8 x 300 x 10
-12
(
)
x (5.0V x 0.8)/ 20 x 10
9
(
)
= 480mA
(EQ. 4)
FIGURE 18. SYSTEM EFFECTS OF GATED INPUTS
ADDRESS
ADDRESS
ALE
MULTIPLEXED
ICC
BUS
P
P
N
N
STB
DATA IN
INTERNAL
DATA
V
CC
P
N
V
CC
82C82
4-277
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.5V to V
CC
+0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
C82C82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to +70
o
C
I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
M82C82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Thermal Resistance (Typical)
JA
JC
CERDIP . . . . . . . . . . . . . . . . . . . . . . . .
75
o
C/W
18
o
C/W
CLCC. . . . . . . . . . . . . . . . . . . . . . . . . .
85
o
C/W
22
o
C/W
PDIP . . . . . . . . . . . . . . . . . . . . . . . . . .
75
N/A
PLCC . . . . . . . . . . . . . . . . . . . . . . . . . .
75
N/A
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65
o
C to +150
o
C
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150
o
C
Minimum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300
o
C
(PLCC Lead Tips Only)
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
V
CC
= 5.0V
10%;
T
A
= 0
o
C to +70
o
C (C82C82);
T
A
= -40
o
C to +85
o
C (I82C82);
T
A
= -55
o
C to +125
o
C (M82C82)
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
V
IH
Logical One Input Voltage
2.0
-
V
C82C82, I82C82 (Note 1)
2.2
-
V
M82C82 (Note 1)
V
IL
Logical Zero Input Voltage
-
0.8
V
V
OH
Logical One Output Voltage
2.9
-
V
I
OH
= -8mA, OE = GND
V
CC
-0.4V
-
V
I
OH
= -100
A, OE = GND
V
OL
Logical Zero Output Voltage
-
0.4
V
I
OL
= 8mA, OE = GND
II
Input Leakage Current
-1.0
1.0
A
V
IN
= GND or V
CC
, DIP Pins 1-9, 11
IO
Output Leakage Current
-10.0
10.0
A
V
O
= GND or V
CC
, OE
V
CC
-0.5V
DIP Pins 12-19
ICCSB
Standby Power Supply Cur-
rent
-
10
A
V
IN
= V
CC
or GND, V
CC
= 5.5V, Outputs Open
ICCOP
Operating Power Supply
Current
-
1
mA/MHz
T
A
= +25
o
C, V
CC
= 5V, Typical (See Note 2)
NOTES:
1. V
IH
is measured by applying a pulse of magnitude = V
IH
min to one data input at a time and checking the corresponding device output
for a valid logical "1" during valid input high time. Control pins (STB, OE) are tested separately with all device data input pins at V
CC
-0.4.
2. Typical ICCOP = 1mA/MHz of STB cycle time. (Example: 5MHz
P, ALE = 1.25MHz, ICCOP = 1.25mA).
Capacitance
T
A
= +25
o
C
SYMBOL
PARAMETER
TYPICAL
UNITS
TEST CONDITIONS
C
IN
Input Capacitance
13
pF
Freq = 1MHz, all measurements are
referenced to device GND
C
OUT
Output Capacitance
20
pF
82C82
4-278
Timing Waveforms
AC Electrical Specifications
V
CC
= 5.0V
10%;
T
A
= 0
o
C to +70
o
C (C82C82);
C
L
= 300pF (Note 1), Freq = 1MHz T
A
= -40
o
C to +85
o
C (I82C82);
T
A
= -55
o
C to +125
o
C (M82C82)
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
(1)
TIVOV
Propagation Delay Input to Output
-
35
ns
Notes 2, 3
(2)
TSHOV
Propagation Delay STB to Output
-
55
ns
Notes 2, 3
(3)
TEHOZ
Output Disable Time
-
35
ns
Notes 2, 3
(4)
TELOV
Output Enable Time
-
50
ns
Notes 2, 3
(5)
TIVSL
Input to STB Setup Time
0
-
ns
Notes 2, 3
(6)
TSLIX
Input to STB Hold Time
25
-
ns
Notes 2, 3
(7)
TSHSL
STB High Time
25
-
ns
Notes 2, 3
(8)
TR, TF
Input Rise/Fall Times
-
20
ns
Notes 2, 3
NOTES:
1. Output load capacitance is rated at 300pF for ceramic and plastic packages.
2. All AC parameters tested as per test circuits and definitions below. Input rise and fall times are driven at 1ns/V.
3. Input test signals must switch between V
IL
- 0.4V and V
IH
+0.4V.
TR, TF (8)
TIVSL (5)
TSLIX
(6)
2.0V
0.8V
VOH -0.1V
TELOV (4)
VOL +0.1V
2.4V
0.8V
TEHOZ (3)
TSHSL (7)
(1)
TIVOV
TSHOV (2)
INPUTS
STB
OUTPUTS
OE
Test Load Circuits
NOTE: Includes stray and jig capacitance.
OUTPUT
TEST
300pF
150
1.7V
POINT
(NOTE)
TIVOV, TSHOV, TELOV
OUTPUT
TEST
50pF
300
0.6V
POINT
(NOTE)
TEHOZ OUTPUT HIGH DISABLE
OUTPUT
TEST
50pF
300
3.3V
POINT
(NOTE)
TEHOZ OUTPUT LOW DISABLE
82C82