1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
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Copyright
Intersil Corporation 1999
ACTS244MS
Radiation Hardened Octal
Non-Inverting Three-State Buffer
Pinouts
20 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR CDIP2-T20,
LEAD FINISH C
TOP VIEW
20 PIN CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR CDFP4-F20,
LEAD FINISH C
TOP VIEW
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
AE
AI1
BO4
AI2
BO3
AI3
AI4
BO2
BO1
GND
VCC
AO1
BI4
AO2
BE
BI3
AO3
BI2
AO4
BI1
2
3
4
5
6
7
8
1
20
19
18
17
16
15
14
13
9
10
12
11
AE
AI1
BO4
AI2
BO3
AI3
AI4
BO2
BO1
GND
VCC
AO1
BI4
AO2
BE
BI3
AO3
BI2
AO4
BI1
Features
Devices QML Qualified in Accordance with MIL-PRF-38535
Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96718 and Intersil's QM Plan
1.25 Micron Radiation Hardened SOS CMOS
Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/Bit/Day
(Typ)
SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
2
/mg
Dose Rate Upset . . . . . . . . . . . . . . . . >10
11
RAD (Si)/s, 20ns Pulse
Dose Rate Survivability . . . . . . . . . . . >10
12
RAD (Si)/s, 20ns Pulse
Latch-Up Free Under Any Conditions
Military Temperature Range . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Significant Power Reduction Compared to ALSTTL Logic
DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
Input Current
1
A at VOL, VOH
Fast Propagation Delay . . . . . . . . . . . . . . . 14.5ns (Max), 10ns (Typ)
Description
The Intersil ACTS244MS is a Radiation Hardened Octal Non-Inverting
Three-State Buffer having two active low enable inputs.
The ACTS244MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACTS244MS is supplied in a 20 lead Ceramic Flatpack (K suffix) or
a Dual-In-Line Ceramic Package (D suffix).
January 1996
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
5962F9671801VRC
-55
o
C to +125
o
C
MIL-PRF-38535 Class V
20 Lead SBDIP
5962F9671801VXC
-55
o
C to +125
o
C
MIL-PRF-38535 Class V
20 Lead Ceramic Flatpack
ACTS244D/Sample
25
o
C
Sample
20 Lead SBDIP
ACTS244K/Sample
25
o
C
Sample
20 Lead Ceramic Flatpack
ACTS244HMSR
25
o
C
Die
Die
Spec Number
518784
File Number
3187.1
3
ACTS244MS
Die Characteristics
DIE DIMENSIONS:
100 x 100 (mils)
2.54 x 2.54 (mm)
METALLIZATION:
Type: AlSi
Metal 1 Thickness: 7.125k
1.125k
Metal 2 Thickness: 9k
1k
GLASSIVATION:
Type: SiO
2
Thickness: 8k
1k
WORST CASE CURRENT DENSITY:
< 2.0 x 10
5
A/cm
2
BOND PAD SIZE:
110 x 110 (
m)
4.4 x 4.4 (mils)
Metallization Mask Layout
ACTS244MS
BO4 (3)
AI2 (4)
BO3 (5)
AI3 (6)
BO2 (7)
AI4 (8)
VCC
BO1 (9)
AO4 (12)
(13) BI2
(14) AO3
(15) BI3
(16) AO2
(17) BI4
(18) AO1
(20)
VCC
(20)
AE
(1)
AI1
(2)
BE
(19)
(11)
BI1
(10)
GND
(10)
GND
Spec Number
518784
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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