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Электронный компонент: CA3126M1

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8-33
May 1999
CA3126
TV Chroma Processor
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
Harris Corporation 1999
File Number
860.5
Features
Phase Locked Subcarrier Regeneration Utilizes
Sample-and-Hold Techniques
Automatic Chrominance Control (ACC)/Killer Detector
Employs Sample-and-Hold Techniques
Supplementary ACC with an Overload Detector to
Prevent Oversaturation of this Picture Tube
Sinusoidal Subcarrier Output
Keyed Chroma Output
Emitter Follower Buffered Outputs for Low Output
Impedance
Linear DC Saturation Control
Applications
TV/CATV Receiver Circuits
NTSC Color Decoder/Processor
Computer Graphics Subcarrier Regenerator
Timing Reference for Frame Grabbers
DSP Clock Timing Reference Source
Description
The Harris CA3126 is a monolithic silicon integrated circuit
designed for TV chroma processing and is ideally suited for
NTSC color graphic applications that require subcarrier
regeneration of the color burst signal.
Pinouts
Part Number Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
CA3126E
-40 to 85
16 Ld PDIP
E16.3
CA3126M1
-40 to 85
20 Ld SOIC
M20.3
CA3126
(PDIP)
TOP VIEW
CA3126
(SOIC)
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
CHROMA IN
AFPC FILTER +
AFPC FILTER -
RF BYPASS
GROUND
VCO OUT
CARRIER OUT
VCO IN
CHROMA GAIN CONT.
ZENER REF
OVERLOAD DET.
V+
ACC+
ACC-
HORIZ. KEY IN
CHROMA OUT
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
CHROMA IN
AFPC FILTER +
NC
AFPC FILTER -
RF BYPASS
GROUND
VCO IN
VCO OUT
NC
NC
CHROMA GAIN CONT.
NC
ZENER REF
OVERLOAD DET.
CHROMA OUT
V+
ACC +
ACC -
HORIZ. KEY IN
CARRIER OUT
[ /Title
(CA31
26)
/Sub-
ject
(TV
Chrom
a Pro-
cessor)
/Autho
r ()
/Key-
words
(Har-
ris
Semi-
con-
ductor,
TV
chroma
pro-
cessor,
subcar-
rier
regen-
era-
tion,
ntsc,
acc,
over-
load
detec-
tor,
keyed
chroma
out-
put,
color
proces-
sor,
indus-
trial
OBSOLETE PR
ODUCT
NO RECOMMENDED REPLA
CEMENT
Call Central Applications 1-800-442-7747
or email: centapp@harris.com
8-34
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage (V+ to GND) (Note 1). . . . . . . . . . . . . . . . . 13.2V
DC Current:
Into V+ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38mA
Into Zener Reference Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
DC Voltage (Horizontal Key In)
Negative Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V
Positive Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
Maximum Junction Temperature (Plastic Packages) . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. This rating does not apply when using the internal zener reference in conjunction with an external pass transistor.
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
T
A
= 25
o
C, Chroma Gain Control at maximum position for all tests except as noted. Electrical
specifications referenced to test circuit.
PARAMETER
TERMINAL,
MEASUREMENT
AND SYMBOL
SWITCH POS.
V
CHROMA
INPUT TP
1
UNITS
S
1
S
2
MIN
TYP
MAX
DC ELECTRICAL SPECIFICATIONS
Voltage Regulator
V
12
2
2
0
10.1
11.2
12.1
V
Supply Current
I
12
2
2
0
16
25
38
mA
SWITCHING ELECTRICAL SPECIFICATIONS (Note 3)
Pull-In Range (Note 4)
V
8
(Note 6)
2
0.5V
P-P
250
-
-
Hz
Oscillator Output
V
8
2
2
0
0.6
1.0
-
V
P-P
100% Chroma Output
V
15
1
2
0.5V
P-P
1.4
2.7
-
V
P-P
Overload Detector
V
15
1
1
0.5V
P-P
0.4
-
0.7
V
P-P
Minimum Chroma Output
(Note 5)
V
15
1
2
0.5V
P-P
-
-
20
mV
P-P
200% Chroma Output
V
15
1
2
1V
P-P
70
100
140
% of
100%
Reading
20% Chroma Output
V
15
1
2
0.1V
P-P
40
-
105
Kill Level
V
TP1
1
2
Vary
5
-
60
mV
P-P
NOTES:
3. Except for pull-in range testing, tune oscillator trimmer capacitor for free running frequency of 3.579545MHz
10Hz.
4. Set Switch 1 to Position 2, detune oscillator
250Hz, set Switch 1 to Position 1, and check for oscillator pull-in.
5. Set Chroma Gain Control to minimum position (CCW).
CA3126
8-35
Test Circuit
2N2102
16
15
14
13
270
+24V
10k
0.05
F
12
11
10
9
CA3126
I
1
2
S
2
2k
0.01
F
0.02
F
0.02
F
3.9k
47k
1
F
CCW
10k
CW
V
REG
1
F
OSCILLOSCOPE
1
2
3
4
5
6
7
8
0.1
F
2
k
0.01
F
0.01
F
0.01
F
680
0.01
F
10pF
NPO
20pF
N750
33pF
N750
0.01
F
2.45k
TP
1
1
2
S
1
50
XTAL
3.579545MHz
COUNTER
SUB-
CARRIER
OUTPUT
KEY
PULSE
VARIABLE
ATTENUATOR
TEST SIGNAL
GENERATOR
PULSE
GENERATOR
BURST
SYNC.
CHROMA
INPUT
SIGNAL
(A)
(B)
2.5
s
3.579545MHz
63.5
s
BURST
4
s
5
s CENTERED ON BURST
V
CHROMA
0.46V
CHROMA
1.0V
PEAK
(MIN)
Pin numbers refer to the PDIP package.
(A) Chroma input signal
(B) Key pulse input signal
CHROMA
GAIN
CONTROL
CA3126
8-36
Block Diagram
TV CHROMA PROCESSOR
NOTES:
6. Optional design features.
7. Pinout numbers refer to the PDIP package.
-
/4
SHIFTER
4
3
6
7
2
SIGNAL
SAMPLE
AND HOLD
BIAS
SAMPLE
AND HOLD
DC CONTR.
BALANCED
SHIFTER
VCO
AMPL.
LIMIT
AFPC
DET.
+
/4
SHIFTER
AMPL.
8
CARRIER
OUTPUT
ACC
AMPL.
ACC
DET.
INTERN.
REF.
ATTENU-
ATOR
OVERLOAD
DETECTOR
SECOND
CHROMA
AMPL.
13
BIAS
CONTROL
COUPLING
NETWORK
KILLER
AMPL.
12
15
DELAY
BIAS
DELAY
BIAS
SIGNAL
SAMPLE
AND HOLD
BIAS
SAMPLE
AND HOLD
BALANCE-
UNBALANCE
TRANSLATOR
10
11
1
16
FIRST
CHROMA
AMPL.
SUPPLY
VOLTAGE
2N2102
CHROMA
OUTPUT
270
10k
0.05
F
0.01
F
3.9k
ZENER
REF.
KEYER
14
9
2k
5
s WIDTH
HORIZONTAL
KEY INPUT
0V
KILLER
FILTER
CHROMA
INPUT
CHROMA
INPUT
0.01
F
2.45k
2
F
CHROMA GAIN
CONTROL
1.2k
50k
10
k
TO
TERM. 12
0.01
F
0.01
F
1
F
ACC
FILTER
CA3126
0.01
F
+11.2V
33pF
20pF
10pF
CRYSTAL
FILTER
680
2k
AFPC
FILTER
1.0
F
0.01
F
RF
BYPASS
0.01
F
GND
0.01
F
+24V
CW
CCW
(NOTE 6)
(NOTE 6)
5
CA3126
8-37
Schematic Diagram
NOTE: Pin numbers refer to the PDIP Package. Resistance values are in ohms.
R
1
300
R
4
300
R
5
700
R
2
700
R
60
1.5K
CHROMA
INPUT
FIRST CHROMA
AMPLIFIER
Q
1
Q
2
Q
3
R
6
500
R
3
250
R
8
2.2K
R
9
500
D
1
R
10
1.6K
Q
50
R
7
500
R
11
1.3K
Q
71
SECOND CHROMA
AMPLIFIER
Q
9
Q
10
SINGLE SAMPLE
AND HOLD
AFPC DETECTOR
Q
7
Q
5
Q
6
Q
4
R
12
1K
Q
8
Q
51
Q
52
Q
53
Q
11
Q
12
Q
54
R
13
4K
R
17
2K
R
20
5K
Q
13
R
16
12K
R
15
700
R
14
2.1K
R
43
2.5K
Q
80
Q
68
Q
67
Q
24
Q
65
Q
66
Q
23
R
78
1K
R
42
8K
Q
22
Q
25
R
41
1K
KILLER
AMP.
Q
20
Q
27
R
44
5K
R
40
330
R
77
750
D
3
16
13
OVERLOAD
DETECTOR
CHROMA
GAIN
CONTROL
15
OVERLOAD DETECTOR
Q
28
R
45
220
R
47
5K
R
46
5K
1
CHROMA
OUTPUT
Q
29
R
49
700
ACC
AMP.
Q
35
Q
69
Q
70
R
54
4K
Q
34
R
19
12K
R
18
1K
Q
32
Q
33
Q
31
R
50
5K
R
51
2K
Q
30
R
52
1K
D
1
Z
2
Z
3
R
55
3.5K
R
53
700
Q
47
ACC
DETECTOR
SIGNAL SAMPLE
AND HOLD
Q
72
R
57
2K
R
59
2K
5
14
ZENER
REFERENCE
GROUND
(SUBSTRATE)
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
4
RF BYPASS
C
1
10pF
C
3
5pF
Q
36
R
48
2K
R
79
300
ZENER
REFERENCE
CA3126