1
March 1998
CA3252
Quad Gated Non-Inverting Power Driver
Features
Four 600mA Non-Inverting Power Output Drivers
50V and 1A Maximum Rated Power Output Drivers
V
CE(SUS)
Capability . . . . . . . . . . . . . . . . . . . . . . . . . 35V
Inputs Compatible With TTL or 5V CMOS Logic
Suitable For Resistive, Lamp or Inductive Loads
Inductive Clamps on Each Output
High Dissipation Power-Frame Package
Operating Temperature Ranges . . . . . . -40
o
C to 105
o
C
Applications
Solenoids
Relays
Lamps
Steppers
Small Motors
Displays
System Applications
Automotive
Appliances
Industrial Controls
Robotics
Description
The CA3252 is used to interface low-level logic to high cur-
rent loads. Each Power Driver has four inverting switches
consisting of an inverting logic input stage and an inverting
low-side driver output stage. All inputs are 5V TTL/CMOS
logic compatible and have a common Enable input. On-chip
steering diodes are connected from each output (in pairs) to
the CLAMP pins (in pairs) which may be used in conjunction
with external zener diodes to protect the IC against over-volt-
age transients that result from inductive load switching. The
CA3252 may be used in a variety of automotive and indus-
trial control applications to drive relays, solenoids, lamps and
small motors.
To allow for maximum heat transfer from the chip, all ground
pins on the DIP and SOIC packages are directly connected
to the mounting pad of the chip. Integral heat spreading lead
frames directly connect the bond pad and ground leads for
good heat dissipation. In a typical application, the package is
mounted on a copper PC Board. By increasing copper
ground area on the PC Board, more heat is conducted away
from the ground leads. The junction-to-ambient thermal
resistances may be reduced to less than 40
o
C/W with
approximately two square inches of copper area.
Pinouts
CA3252E
(PDIP)
TOP VIEW
CA3252M
(SOIC)
TOP VIEW
Ordering Information
PART
NUMBER
TEMP. (
o
C)
PACKAGE
PKG. NO.
CA3252E
-40 to 105
16 Ld PDIP
E16.3
CA3252M
-40 to 105
20 Ld SOIC
M20.3
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
OUT A
CLAMP AB
OUT B
GND
GND
OUT C
CLAMP CD
OUT D
IN A
IN B
ENABLE
GND
GND
V
CC
IN C
IN D
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
CLAMP AB
NC
NC
OUT B
GND
GND
NC
OUT C
NC
CLAMP CD
OUT A
INB
ENABLE
GND
IN A
GND
V
CC
IN C
IN D
OUT D
File Number
1542.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
2
Functional Block Diagram
V+
V
CC
IN D
IN C
IN B
IN A
ENABLE
OUT D
OUT C
CLAMP
OUT B
OUT A
CLAMP
GND
GND
GND
GND
FIGURE 1. CA3252 QUAD NON-INVERTING POWER DRIVER SHOWN WITH TYPICAL APPLICATION LOADS
TRUTH TABLE (Each Output)
ENABLE
IN
OUT
H
L
L
H
H
H
L
X
H
H = High, L = Low, X = Don't Care
SOLENOID
LAMP
V
BATT
V
BATT
HIGH CURRENT
MOTOR
HIGH SIDE DR
RELAY
V
BATT
V+
V
CC
IN D
IN C
IN B
IN A
ENABLE
OUT D
OUT C
CLAMP
OUT B
OUT A
CLAMP
GND
GND
CA3252
3
FIGURE 2. SCHEMATIC OF ONE INPUT SECTION
FIGURE 3. TYPICAL LATCHED ON CIRCUIT SWITCHING CONFIGURATION. WHEN V
IN
IS SWITCHED LOW, THE OUTPUT IS
TURNED ON (LOW).
REFERENCE
VOLTAGE
1.2V
CONSTANT
IN
ENABLE
V
CC
TO SUBSEQUENT STAGES
CURRENT
SOURCE
11k
V+
V
CC
IN
ENABLE
OUT
CLAMP
GND
GND
CA3252
+5V
V
BATT
LOAD
0.001
F
12k
27k
0.001
F
27V
CA3252
4
Absolute Maximum Ratings
Thermal Information
Output Voltage, V
CEX
. . . . . . . . . . . . . . . . . . . . . . . . . -0.7 to 50V
DC
Logic Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Logic Input Voltage, V
IN
. . . . . . . . . . . . . . . . . . . . . . . . . .-0.7 to 15V
Output Sustaining Voltage, V
CE(SUS)
. . . . . . . . . . . . . . . . . . 35V
DC
Output Current, I
O
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 1A
DC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 105
o
C
Thermal Resistance (Typical, Note 2)
JA
o
C/W
CA3252E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
CA3252M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature Soldering (10s Max) . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The Maximum Ambient Temperature is limited for the sustained conditions of the I
CC(ON)
Supply Current test with all Outputs ON. The total
DC current for the CA3252 with all 4 outputs ON should not exceed 0.7A at each output for a total of (4 X 0.7A + Max. I
CC
) ~ 2.9A. This
level of sustained current will significantly increase the on-chip temperature due to increased dissipation. Under any condition, the Absolute
Maximum Junction Temperature must not exceed150
o
C. While any one loaded output may exceed 0.7A, the maximum rating limit is 1A.
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
T
A
= -40
o
C to 105
o
C, V
CC
= V
EN
= 5V; Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNITS
Output Sustaining Voltage
V
CE(SUS)
I
C
= 100mA, V
IN
= 2V, V
EN
= 2V
35
-
V
Output Leakage Current
I
CEX
V
CE
= 50V, V
IN
= 2V, V
EN
= 0.8V
-
100
A
Collector to Emitter Saturation Voltage
V
CE(SAT)
I
C
= 100mA, V
IN
= 0.8V
-
0.3
V
I
C
= 300mA, V
IN
= 0.8V
-
0.5
V
I
C
= 600mA, V
IN
= 0.8V
-
0.8
V
Input Low Voltage
V
IL
-
0.8
V
Input Low Current
I
IL
V
IN
= 0.4V
-15
10
A
Input High Voltage
V
IH
I
C
= 600mA
2
-
V
Input High Current
I
IH
I
C
= 600mA, V
IN
= 4.5V
-10
-10
A
Logic Supply Current, All Outputs ON
I
CC(ON)
I
C
= 600mA, All Outputs ON (Note 1)
-
90
mA
Logic Supply Current, All Outputs OFF
I
CC(OFF)
All Outputs OFF
-
10
mA
Clamp Diode Leakage Current
I
R
V
R
= 50V (Diode Reverse Voltage)
-
100
A
Clamp Diode Forward Voltage
V
F
I
F
= 0.6A
-
1.8
V
I
F
= 1.2A
-
2.0
V
Output Current
I
OUT
V
IN
= 0.4V, V
BATT
= +13V,
Output Load = 10
0.9
-
A
Turn-ON Propagation Delay Time
t
PHL
I
C
= 600mA
-
10
s
Turn-OFF Propagation Delay Time
t
PLH
I
C
= 600mA
-
10
s
Low Enable Voltage
V
ENL
-
0.8
V
Low Enable Current
I
ENL
V
EN
= 0.4V
-15
10
A
High Enable Voltage
V
ENH
2.0
-
V
High Enable Current
I
ENH
V
EN
2V
-250
+250
A
CA3252
5
CA3252
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the "MO Series Symbol List" in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and
are measured with the leads constrained to be per-
pendicular to datum
.
7. e
B
and e
C
are measured at the lead tips with the leads uncon-
strained. e
C
must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
C
L
E
e
A
C
e
B
e
C
-B-
E1
INDEX
1 2 3
N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A1
-A-
0.010 (0.25)
C
A
M
B S
e
A
-C-
Dual-In-Line Plastic Packages (PDIP)
E16.3
(JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
B1
0.045
0.070
1.15
1.77
8, 10
C
0.008
0.014
0.204
0.355
-
D
0.735
0.775
18.66
19.68
5
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2.54 BSC
-
e
A
0.300 BSC
7.62 BSC
6
e
B
-
0.430
-
10.92
7
L
0.115
0.150
2.93
3.81
4
N
16
16
9
Rev. 0 12/93
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