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Электронный компонент: CA3310M

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6-6
August 1997
CA3310, CA3310A
CMOS, 10-Bit, A/D Converters
with Internal Track and Hold
Features
CMOS Low Power (Typ). . . . . . . . . . . . . . . . . . . . .15mW
Single Supply Voltage . . . . . . . . . . . . . . . . . . . . 3V to 6V
Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
s
Built-In Track and Hold
Rail-to-Rail Input Range
Latched Three-state Output Drivers
Microprocessor-Compatible Control Lines
Internal or External Clock
Applications
Fast, No-Droop, Sample and Hold
Voice Grade Digital Audio
DSP Modems
Remote Low Power Data Acquisition Systems
P Controlled Systems
Description
The Intersil CA3310 is a fast, low power, 10-bit successive
approximation analog-to-digital converter, with microprocessor-
compatible outputs. It uses only a single 3V to 6V supply and
typically draws just 3mA when operating at 5V. It can accept full
rail-to-rail input signals, and features a built-in track and hold.
The track and hold will follow high bandwidth input signals, as it
has only a 100ns (typical) input time constant.
The ten data outputs feature full high-speed CMOS three-
state bus driver capability, and are latched and held through
a full conversion cycle. Separate 8 MSB and 2 LSB enables,
a data ready flag, and conversion start and ready reset
inputs complete the microprocessor interface.
An internal, adjustable clock is provided and is available as
an output. The clock may also be driven from an external
source.
Pinout
CA3310, CA3310A
(PDIP, SBDIP, SOIC)
TOP VIEW
Ordering Information
PART
NUMBER
LINEARITY
(INL, DNL)
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
CA3310E
0.75 LSB
-40 to 85
24 Ld PDIP
E24.6
CA3310AE
0.5 LSB
-40 to 85
24 Ld PDIP
E24.6
CA3310M
0.75 LSB
-40 to 85
24 Ld SOIC
M24.3
CA3310AM
0.5 LSB
-40 to 85
24 Ld SOIC
M24.3
CA3310D
0.75 LSB
-55 to 125
24 Ld SBDIP
D24.6
CA3310AD
0.5 LSB
-55 to 125
24 Ld SBDIP
D24.6
1
2
3
4
5
6
7
8
9
10
11
12
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D8
D9 (MSB)
DRDY
V
SS
(GND)
16
17
18
19
20
21
22
23
24
15
14
13
V
DD
V
REF
+
R
EXT
CLK
STRT
V
AA
+
OEL
OEM
DRST
V
IN
V
REF
-
V
AA
-
File Number
3095.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
6-7
Functional Block Diagram
16C
8C
4C
2C
C
16C
8C
4C
2C
C
C
32
31
C
V
DD
V
SS
V
IN
V
REF
+
V
AA
+
V
AA
-
V
REF
-
ALL
LOGIC
50
SUBSTRATE
RESISTANCE
10-BIT
SUCCESSIVE
APPROXIMATION
REGISTER
10-BIT
EDGE
TRIGGERED
"D"
LATCH
CONTROL
AND
TIMING
CLOCK
CLK
CLR
Q
STRT
R
EXT
CLK
DRDY
DRST
OEM
D9 (MSB)
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
OEL
CA3310, CA3310A
6-8
Typical Application Schematics
INPUT RANGE
R1
R2
R3
R4
R5
0V TO 2.5V
4.99K
9.09K
OPEN
4.99K
9.09K
0V TO 5V
4.99K
4.53K
OPEN
4.99K
4.53K
0V TO 10V
10K
4.53K
OPEN
10K
4.53K
-2.5V TO +2.5V
4.99K
9.09K
9.09K
4.99K
4.53K
-5V TO +5V
10K
9.09K
9.09K
10K
4.53K
+5V SUPPLY
0.1
F CER
D
START CONVERSATION
RESET FLAG
HIGH BYTE ENABLE
LOW BYTE ENABLE
OUTPUT DATA
DATA READY FLAG
2MHz CLOCK
NC
A
D
D
ADJUST
100
-1V
A
0.1
V
DD
STRT
DRST
OEM
OEL
D0 - D9
DRDY
CLK
R
EXT
V
SS
V
AA
+
V
REF
+
CA3310/A
V
REF
-
V
AA
-
V
IN
47pF
R5
10K
1
2
3
4
5
6
7
8
CA3140
8
ICL7663S
3
1
6
4
5
A
A
R2
R3
ADJUST
GAIN
100
10%
4.5V
75V
5K
28.7K
A
100
+8V
OPTIONAL
V
DD
R4
+
V
IN
-
R1
TO
+15V
CLAMP
A
A
0.1
A
+
4.7
F
TAN
+
A
A
4.7
F
TAN
UNLESS NOTED,
ALL RESISTORS =
1% METAL FILM,
POTS = 10 TURN, CERMET
D = DIGITAL GROUND
A = ANALOG GROUND
TO
-15V
OFF SET
+
-
CA3310, CA3310A
6-9
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage V
DD
. . . . . . . . . . . . . . . V
SS
-0.5V to V
SS
+7V
Analog Supply Voltage (V
AA
+) . . . . . . . . . . . . . . . . . . . . . V
DD
0.5V
Any Other Terminal . . . . . . . . . . . . . . . . .V
SS
-0.5V to V
DD
+ 0.5V
DC Input Current or Output (Protection Diode)
Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20mA
DC Output Drain Current, per Output . . . . . . . . . . . . . . . . . .
35mA
Total DC Supply or Ground Current . . . . . . . . . . . . . . . . . . .
70mA
Operating Conditions
Temperature Range (T
A
)
Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Package Type E, M . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
JC
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . .
75
N/A
SBDIP Package . . . . . . . . . . . . . . . . . . . .
70
22
SOIC Package . . . . . . . . . . . . . . . . . . . . .
75
N/A
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Hermetic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
o
C
Maximum Storage Temperature (T
STG
) . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
T
A
= 25
o
C, V
DD
= V
AA
+ = 5V, V
REF
+ = 4.608V, V
SS
= V
AA
- = V
REF
- = GND, CLK = External 1MHz,
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY (See Text For Definitions)
Resolution
10
-
-
Bits
Differential Linearity Error
CA3310
-
0.5
0.75
LSB
CA3310A
-
0.25
0.5
LSB
Integral Linearity Error
CA3310
-
0.5
0.75
LSB
CA3310A
-
0.25
0.5
LSB
Gain Error
CA3310
-
0.25
0.5
LSB
CA3310A
-
-
0.25
LSB
Offset Error
CA3310
-
0.25
0.5
LSB
CA3310A
-
-
0.25
LSB
ANALOG OUTPUT
Input Resistance
In Series with Input Sample
Capacitors
-
330
-
Input Capacitance
During Sample State
-
300
-
pF
Input Capacitance
During Hold State
-
20
-
pF
Input Current
At V
IN
= V
REF
+ = 5V
-
-
+300
A
At V
IN
= V
REF
- = 0V
-
-
-100
A
Static Input Current
STRT = V+, CLK = V+
At V
IN
= V
REF
+ = 5V
-
-
1
A
At V
IN
= V
REF
- = 0V
-
-
-1
A
Input + Full-Scale Range
(Note 2)
V
REF
- +1
-
V
DD
+0.3
V
Input - Full-Scale Range
(Note 2)
V
SS
-0.3
-
V
REF
+ -1
V
Input Bandwidth
From Input RC Time Constant
-
1.5
-
MHz
DIGITAL INPUTS DRST, OEL, OEM, STRT, CLK
High-Level Input Voltage
Over V
DD
= 3V to 6V (Note 2)
70
-
-
% of
V
DD
Low-Level Input Voltage
Over V
DD
= 3V to 6V (Note 2)
-
-
30
% of
V
DD
Input Leakage Current
Except CLK
-
-
1
A
Input Capacitance
(Note 2)
-
-
10
pF
Input Current
CLK Only (Note 2)
-
-
400
A
CA3310, CA3310A
6-10
DIGITAL OUTPUTS D0 - D9, DRDY
High-Level Output Voltage
I
SOURCE
= -4mA
4.6
-
-
V
Low-Level Output Voltage
I
SINK
= 6mA
-
-
0.4
V
Three-State Leakage
Except DRDY
-
-
1
A
Output Capacitance
Except DRDY (Note 2)
-
-
20
pF
CLK OUTPUT
High-Level Output Voltage
I
SOURCE
= 100
A (Note 2)
4
-
-
V
Low-Level Output Voltage
I
SlNK
= 100
A (Note 2)
-
-
1
V
TIMING
Clock Frequency
Internal, CLK and R
EXT
Open
200
300
400
kHz
Internal, CLK Shorted to R
EXT
600
800
1000
kHz
External, Applied to CLK (Note 2) (Max)
-
4
2
MHz
(Min)
100
10
-
kHz
Clock Pulse Width, t
LOW
, t
HIGH
External, Applied to CLK:
See Figure 1 (Note 2)
100
-
-
ns
Conversion Time
Internal, CLK Shorted to R
EXT
13
-
-
s
Aperture Delay, t
D
APR
See Figure 1
-
100
-
ns
Clock to Data Ready Delay, t
D1
DRDY
See Figure 1
-
150
-
ns
Clock to Data Ready Delay, t
D2
DRDY
See Figure 1
-
250
-
ns
Clock to Data Delay, t
D
Data
See Figure 1
-
200
-
ns
Start Removal Time, t
R
STRT
See Figures 3 and 4 (Note 1)
-
-120
-
ns
Start Setup Time, t
SU
STRT
See Figure 4
-
160
-
ns
Start Pulse Width, t
W
STRT
See Figures 3 and 4
-
10
-
ns
Start to Data Ready Delay, t
D3
DRDY
See Figures 3 and 4
-
170
-
ns
Clock Delay from Start, t
D
CLK
See Figure 3
-
200
-
ns
Ready Reset Removal Time, t
R
DRST
See Figure 50 (Note 1)
-
-80
-
ns
Ready Reset Pulse Width, t
W
DRST
See Figure 5
-
10
-
ns
Ready Reset to Data Ready Delay,
t
D4
DRDY
See Figure 5
-
35
-
ns
Output Enable Delay, t
EN
See Figure 2
-
40
-
ns
Output Disable Delay, t
DIS
See Figure 2
-
50
-
ns
SUPPLIES
Supply Operating Range, V
DD
or V
AA
(Note 2)
3
-
6
V
Supply Current, I
DD
+ I
AA
See Figures 14, 15
-
3
8
mA
Supply Standby Current
Clock Stopped During Cycle 1
-
3.5
-
mA
Analog Supply Rejection
At 120Hz, See Figure 13
-
25
-
mV/V
Reference Input Current
See Figure 10
-
160
-
A
TEMPERATURE DEPENDENCY
Offset Drift
At 0 to 1 Code Transition
-
-4
-
V/
o
C
Gain Drift
At 1022 to 1023 Code Transition
-
-6
-
V/
o
C
Internal Clock Speed
See Figure 7
-
-0.5
-
%/
o
C
NOTES:
1. A (-) removal time means the signal can be removed after the reference signal.
2. Parameter not tested, but guaranteed by design or characterization.
Electrical Specifications
T
A
= 25
o
C, V
DD
= V
AA
+ = 5V, V
REF
+ = 4.608V, V
SS
= V
AA
- = V
REF
- = GND, CLK = External 1MHz,
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
CA3310, CA3310A