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Электронный компонент: CD40104BMS

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7-1307
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
CD40104BMS,
CD40194BMS
CMOS 4-Bit Bidirectional
Universal Shift Register
Pinouts
CD40104BMS
TOP VIEW
CD40194BMS
TOP VIEW
Functional Diagrams
CD40104BMS
CD40194BMS
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
OUTPUT ENABLE
SHIFT RIGHT IN
D0
D1
D2
D3
VSS
SHIFT LEVEL IN
VDD
Q1
Q2
Q3
CLOCK
SELECT 1
SELECT 0
Q0
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
RESET
SHIFT RIGHT IN
D0
D1
D2
D3
VSS
SHIFT LEVEL IN
VDD
Q1
Q2
Q3
CLOCK
SELECT 1
SELECT 0
Q0
3
4
5
6
7
2
9
10
D0
D1
D2
D3
CLOCK
S0
S1
SHIFT LEFT IN
SHIFT RIGHT IN
MODE SELECT
11
15
14
13
12
Q0
Q1
Q2
Q3
OUTPUT ENABLE
1
VDD = 16
VSS = 8
3
4
5
6
7
2
9
10
D0
D1
D2
D3
CLOCK
S0
S1
SHIFT LEFT IN
SHIFT RIGHT IN
MODE SELECT
11
15
14
13
12
Q0
Q1
Q2
Q3
RESET
1
VDD = 16
VSS = 8
Features
High Voltage Type (20V Rating)
Medium Speed fCL = 12MHz (typ.) at VDD = 10V
Fully Static Operation
Synchronous Parallel or Serial Operation
Three State Outputs (CD40104BMS)
Asynchronous Master Reset (CD40194BMS)
5V, 10V and 15V Parametric Ratings
Standardized Symmetrical Output Characteristics
Meets All Requirements of JEDEC Tentative Standard
No. 13B, "Standard Specifications for Description of
`B' Series CMOS Devices"
Applications
Arithmetic Unit Bus Registers
Serial/Parallel Conversions
General Purpose Register for Bus Organized Systems
General Purpose Registers
Description
The CD40104BMS is a universal shift register featuring parallel
inputs, parallel outputs, SHIFT RIGHT and SHIFT LEFT serial
inputs, and a high impedance third output state allowing the device
to be used in bus organized systems.
In the parallel load mode (S0 and S1 are high), data is loaded into
the associated flip-flop and appears at the output after the positive
transition of the CLOCK input. During loading, serial data flow is
inhibited. Shift right and shift left are accomplished synchronously
on the positive clock edge with serial data entered at the SHIFT
RIGHT and SHIFT LEFT serial inputs, respectively. Clearing the
register is accomplished by setting both mode controls low and
clocking the register. When the output enable input is low, all outputs
assume the high impedance state.
The CD40194BMS is a universal shift register featuring parallel inputs,
parallel outputs SHIFT RIGHT and SHIFT LEFT serial inputs, and a
direct overriding clear input. In the parallel load mode (S0 and S1 are
high), data is loaded into the associated flip-flop and appears at the out-
put after the positive transition of the CLOCK input. During loading,
serial data flow is inhibited. Shift right and shift left are accomplished
synchronously on the positive clock edge with data entered at the
SHIFT RIGHT and SHIFT LEFT serial inputs, respectively. Clocking of
the register is inhibited when both mode control inputs are low. When
low, the RESET input resets all stages and forces all outputs low. The
CD40194BMS is similar to industry types 340194 and MC40194.
The CD40104BMS and CD40194BMS series types are supplied in
these 16 lead outline packages
Braze Seal DIP
*HNX,
H4W
Frit Seal DIP
*H1L,
HIF
Ceramic Flatpack
H6W
* CD40104B Only
CD40194B Only
File Number
3352
December 1992
7-1308
Specifications CD40104BMS, CD40194BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .
10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265
o
C
At Distance 1/16
1/32 Inch (1.59mm
0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
ja
jc
Ceramic DIP and FRIT Package . . . . .
80
o
C/W
20
o
C/W
Flatpack Package . . . . . . . . . . . . . . . .
70
o
C/W
20
o
C/W
Maximum Package Power Dissipation (PD) at +125
o
C
For T
A
= -55
o
C to +100
o
C (Package Type D, F, K) . . . . . . 500mW
For T
A
= +100
o
C to +125
o
C (Package Type D, F, K). . . . . . Derate
Linearity at 12mW/
o
C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For T
A
= Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
GROUP A
SUBGROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Supply Current
IDD
VDD = 20V, VIN = VDD or GND
1
+25
o
C
-
10
A
2
+125
o
C
-
1000
A
VDD = 18V, VIN = VDD or GND
3
-55
o
C
-
10
A
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20V
1
+25
o
C
-100
-
nA
2
+125
o
C
-1000
-
nA
VDD = 18V
3
-55
o
C
-100
-
nA
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20V
1
+25
o
C
-
100
nA
2
+125
o
C
-
1000
nA
VDD = 18V
3
-55
o
C
-
100
nA
Output Voltage
VOL15
VDD = 15V, No Load
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
50
mV
Output Voltage
VOH15
VDD = 15V, No Load (Note 3)
1, 2, 3
+25
o
C, +125
o
C, -55
o
C 14.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1
+25
o
C
0.53
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1
+25
o
C
1.4
-
mA
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1
+25
o
C
3.5
-
mA
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1
+25
o
C
-
-0.53
mA
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1
+25
o
C
-
-1.8
mA
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1
+25
o
C
-
-1.4
mA
Output Current (Source)
IOH15
VDD = 15V, VOUT = 13.5V
1
+25
o
C
-
-3.5
mA
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10
A
1
+25
o
C
-2.8
-0.7
V
P Threshold Voltage
VPTH
VSS = 0V, IDD = 10
A
1
+25
o
C
0.7
2.8
V
Functional
F
VDD = 2.8V, VIN = VDD or GND
7
+25
o
C
VOH >
VDD/2
VOL <
VDD/2
V
VDD = 20V, VIN = VDD or GND
7
+25
o
C
VDD = 18V, VIN = VDD or GND
8A
+125
o
C
VDD = 3V, VIN = VDD or GND
8B
-55
o
C
Input Voltage Low
(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
1.5
V
Input Voltage High
(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
3.5
-
V
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
4
V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
11
-
V
Tri-State Output
Leakage
IOZL
VIN = VDD or GND
VOUT = 0V
VDD = 20V
1
+25
o
C
-0.4
-
A
2
+125
o
C
-12
-
A
VDD = 18V
3
-55
o
C
-0.4
-
A
Tri-State Output
Leakage
IOZH
VIN = VDD or GND
VOUT = VDD
VDD = 20V
1
+25
o
C
-
0.4
A
2
+125
o
C
-
12
A
VDD = 18V
3
-55
o
C
-
0.4
A
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
7-1309
Specifications CD40104BMS, CD40194BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Propagation Delay
Clock to Q
TPHL
TPLH
VDD = 5V, VIN = VDD or GND
(Note 1, 2)
9
+25
o
C
-
440
ns
10, 11
+125
o
C, -55
o
C
-
594
ns
Propagation Delay
CD40194BMS Reset to Q
TPHL
VDD = 5V, VIN = VDD or GND
(Note 1, 2)
9
+25
o
C
-
460
ns
10, 11
+125
o
C, -55
o
C
-
621
ns
Propagation Delay
CD40104BMS 3-State
TPZH
TPZL
TPLZ
VDD = 5V, VIN = VDD or GND
(Note 2, 3)
9
+25
o
C
-
160
ns
10, 11
+125
o
C, -55
o
C
-
216
ns
Propagation Delay
CD40104BMS 3-State
TPHZ
VDD = 5V, VIN = VDD or GND
(Note 2, 3)
9
+25
o
C
-
90
ns
10, 11
+125
o
C, -55
o
C
-
122
ns
Transition Time
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
(Note 1, 2)
9
+25
o
C
-
200
ns
10, 11
+125
o
C, -55
o
C
-
270
ns
Maximum Clock Input
Frequency
FCL
VDD = 5V, VIN = VDD or GND
(Note 1, 2)
9
+25
o
C
3
-
MHz
10, 11
+125
o
C, -55
o
C
2.22
-
MHz
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55
o
C and +125
o
C limits guaranteed, 100% testing being implemented.
3. VDD = 5V, CL = 50pF, RL = 1K, Input TR, TF < 20ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Supply Current
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
-
5
A
+125
o
C
-
150
A
VDD = 10V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
-
10
A
+125
o
C
-
300
A
VDD = 15V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
-
10
A
+125
o
C
-
600
A
Output Voltage
VOL
VDD = 5V, No Load
1, 2
+25
o
C, +125
o
C,
-55
o
C
-
50
mV
Output Voltage
VOL
VDD = 10V, No Load
1, 2
+25
o
C, +125
o
C,
-55
o
C
-
50
mV
Output Voltage
VOH
VDD = 5V, No Load
1, 2
+25
o
C, +125
o
C,
-55
o
C
4.95
-
V
Output Voltage
VOH
VDD = 10V, No Load
1, 2
+25
o
C, +125
o
C,
-55
o
C
9.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1, 2
+125
o
C
0.36
-
mA
-55
o
C
0.64
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1, 2
+125
o
C
0.9
-
mA
-55
o
C
1.6
-
mA
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1, 2
+125
o
C
2.4
-
mA
-55
o
C
4.2
-
mA
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1, 2
+125
o
C
-
-0.36
mA
-55
o
C
-
-0.64
mA
7-1310
Specifications CD40104BMS, CD40194BMS
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1, 2
+125
o
C
-
-1.15
mA
-55
o
C
-
-2.0
mA
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1, 2
+125
o
C
-
-0.9
mA
-55
o
C
-
-1.6
mA
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
1, 2
+125
o
C
-
-2.4
mA
-55
o
C
-
-4.2
mA
Input Voltage Low
VIL
VDD = 10V, VOH > 9V,
VOL < 1V
1, 2
+25
o
C, +125
o
C,
-55
o
C
-
3
V
Input Voltage High
VIH
VDD = 10V, VOH > 9V,
VOL < 1V
1, 2
+25
o
C, +125
o
C,
-55
o
C
7
-
V
Propagation Delay
Clock to Q
TPHL
TPLH
VDD = 10V
1, 2, 3
+25
o
C
-
200
ns
VDD = 15V
1, 2, 3
+25
o
C
-
140
ns
Propagation Delay
CD40194B Reset to Q
TPLH
TPHL
VDD = 10V
1, 2, 3
+25
o
C
-
180
ns
VDD = 15V
1, 2, 3
+25
o
C
-
130
ns
Propagation Delay
CD40104BMS 3-State
TPZH
TPZL
TPLZ
VDD = 10V
1, 2, 3, 4
+25
o
C
-
70
ns
VDD = 15V
1, 2, 3, 4
+25
o
C
-
50
ns
Propagation Delay
CD40104BMS 3-State
TPHZ
VDD = 10V
1, 2, 4
+25
o
C
-
50
ns
VDD = 15V
1, 2, 4
+25
o
C
-
40
ns
Transition Time
TTHL
TTLH
VDD = 10V
1, 2, 3
+25
o
C
-
100
ns
VDD = 15V
1, 2, 3
+25
o
C
-
80
ns
Minimum Data Setup
Time, D0, D3, SRIN,
SLIN to Clock
TS
VDD = 5V
1, 2, 3
+25
o
C
-
100
ns
VDD = 10V
1, 2, 3
+25
o
C
-
70
ns
VDD = 15V
1, 2, 3
+25
o
C
-
50
ns
Minimum Data Hold Time
D0, D3, SRIN, SLIN to
Clock
TH
VDD = 5V
1, 2, 3
+25
o
C
-
0
ns
VDD = 10V
1, 2, 3
+25
o
C
-
0
ns
VDD = 15V
1, 2, 3
+25
o
C
-
0
ns
Minimum Clock Pulse
Width
TW
VDD = 5V
1, 2, 3
+25
o
C
-
180
ns
VDD = 10V
1, 2, 3
+25
o
C
-
80
ns
VDD = 15V
1, 2, 3
+25
o
C
-
50
ns
Maximum Clock Rise and
Fall Time
TRCL
TFCL
VDD = 5V
1, 2, 3, 5
+25
o
C
3
-
s
VDD = 10V
1, 2, 3, 5
+25
o
C
6
-
s
VDD = 15V
1, 2, 3, 5
+25
o
C
8
-
s
Minimum Data Setup
Time
Select 1, Select 0 to
Clock
TS
VDD = 5V
1, 2, 3
+25
o
C
-
400
ns
VDD = 10V
1, 2, 3
+25
o
C
-
220
ns
VDD = 15V
1, 2, 3
+25
o
C
-
130
ns
Minimum Data Hold Time
Select 1, Select 0 to
Clock
TH
VDD = 5V
1, 2, 3
+25
o
C
-
0
ns
VDD = 10V
1, 2, 3
+25
o
C
-
0
ns
VDD = 15V
1, 2, 3
+25
o
C
-
0
ns
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
7-1311
Specifications CD40104BMS, CD40194BMS
Minimum Reset Pulse
Width CD40194BMS
TW
VDD = 5V
1, 2, 3
+25
o
C
-
300
ns
VDD = 10V
1, 2, 3
+25
o
C
-
200
ns
VDD = 15V
1, 2, 3
+25
o
C
-
140
ns
Input Capacitance
CIN
Any Input
1, 2
+25
o
C
-
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
5. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Supply Current
IDD
VDD = 20V, VIN = VDD or GND
1, 4
+25
o
C
-
25
A
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10
A
1, 4
+25
o
C
-2.8
-0.2
V
N Threshold Voltage
Delta
VTN
VDD = 10V, ISS = -10
A
1, 4
+25
o
C
-
1
V
P Threshold Voltage
VTP
VSS = 0V, IDD = 10
A
1, 4
+25
o
C
0.2
2.8
V
P Threshold Voltage
Delta
VTP
VSS = 0V, IDD = 10
A
1, 4
+25
o
C
-
1
V
Functional
F
VDD = 18V, VIN = VDD or GND
1
+25
o
C
VOH >
VDD/2
VOL <
VDD/2
V
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
1, 2, 3, 4
+25
o
C
-
1.35 x
+25
o
C
Limit
ns
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25
o
C limit.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25
o
C
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
IDD
1.0
A
Output Current (Sink)
IOL5
20% x Pre-Test Reading
Output Current (Source)
IOH5A
20% x Pre-Test Reading
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX