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Электронный компонент: CD4066

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7-966
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
CD4066BMS
CMOS Quad Bilateral Switch
Description
CD4066BMS is a quad bilateral switch intended for the
transmission or multiplexing of analog or digital signals. It is
pin for pin compatible with CD4016B, but exhibits a much
lower on state resistance. In addition, the on-state resistance
is relatively constant over the full input signal range.
The CD4066BMS consists of four independent bilateral
switches. A single control signal is required per switch. Both
the p and the n device in a given switch are biased on or off
simultaneously by the control signal. As shown in Figure 1,
the well of the n channel device on each switch is either tied
to the input when the switch is on or to VSS when the switch
is off. This configuration eliminates the variation of the switch
transistor threshold voltage with input signal, and thus keeps
the on-state resistance low over the full operating signal
range.
The advantages over single channel switches include peak
input signal voltage swings equal to the full supply voltage,
and more constant on-state impedance over the input signal
range. For sample and hold applications, however, the
CD4016B is recommended.
The CD4066BMS is supplied in these 14-lead outline pack-
ages:
Pinout
CD4066BMS
TOP VIEW
Braze Seal DIP
H4Q
Frit Seal DIP
H1B
Ceramic Flatpack
H3W
IN/OUT A
OUT/IN A
OUT/IN B
IN/OUT B
CONT B
CONT C
VSS
VDD
CONT A
CONT D
IN/OUT D
OUT/IN D
OUT/IN C
IN/OUT C
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Features
For Transmission or Multiplexing of Analog or Digital
Signals
High Voltage Types (20V Rating)
15V Digital or
7.5V Peak-to-Peak Switching
125
Typical On-State Resistance for 15V Operation
Switch On-State Resistance Matched to Within 5
Over 15V Signal Input Range
On-State Resistance Flat Over Full Peak-to-Peak Sig-
nal Range
High On/Off Output Voltage Ratio
- 80dB Typ. at FIS = 10kHz, RL = 1k
High Degree of Linearity: <0.5% Distortion Typ. at
FIS = 1kHz, VIS = 5Vp-p, VDD - VSS
10V, RL = 10k
Extremely Low Off-State Switch Leakage Resulting in
Very Low Offset Current and High Effective Off-State
Resistance: 10pA Typ. at VDD - VSS = 10V, T
A
= +25
o
C
Extremely High Control Input Impedance (Control Cir-
cuit Isolated from Signal Circuit): 10
12
Typ.
Low Crosstalk Between Switches: -50dB Typ. at FIS =
8MHz, RL = 1k
Matched Control Input to Signal Output
Capacitance: Reduces Output Signal Transients
Frequency Response, Switch on = 40MHz (Typ.)
100% Tested for Quiescent Current at 20V
5V, 10V and 15V Parametric Ratings
Meets All Requirements of JEDEC Tentative Standard
No. 13B, "Standard Specifications for Description of
"B" Series CMOS Devices"
Applications
Analog Signal Switching/Multiplexing
- Signal Gating
- Modulator
- Squelch Control
- Demodulator
- Chopper
- Commutating Switch
Digital Signal Switching/Multiplexing
Transmission Gate Logic Implementation
Analog to Digital & Digital to Analog Conversion
Digital Control of Frequency, Impedance, Phase, and
Analog Signal Gain
December 1992
File Number
3319
7-967
Specifications CD4066BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .
10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265
o
C
At Distance 1/16
1/32 Inch (1.59mm
0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
ja
jc
Ceramic DIP and FRIT Package . . . . .
80
o
C/W
20
o
C/W
Flatpack Package . . . . . . . . . . . . . . . .
70
o
C/W
20
o
C/W
Maximum Package Power Dissipation (PD) at +125
o
C
For TA = -55
o
C to +100
o
C (Package Type D, F, K) . . . . . . 500mW
For TA = +100
o
C to +125
o
C (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/
o
C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
GROUP A
SUBGROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Supply Current
IDD
VDD = 20V, VIN = VDD or GND
1
+25
o
C
-
0.5
A
2
+125
o
C
-
50
A
VDD = 18V, VIN = VDD or GND
3
-55
o
C
-
0.5
A
Input Leakage Current
IIL
VC = VDD or GND
1
+25
o
C
-100
-
nA
2
+125
o
C
-1000
-
nA
3
-55
o
C
-100
-
nA
Input Leakage Current
IIH
VC = VDD or GND
1
+25
o
C
-
100
nA
2
+125
o
C
-
1000
nA
3
-55
o
C
-
100
nA
Input/Output Leakage
Current (Switch OFF)
IOZL
VC = 0V, VIS = 18V,
VOS = 0V, VIS = 0V,
VOS = 18V
VDD = 20
1
+25
o
C
-100
-
nA
2
+125
o
C
-1000
-
nA
VDD = 18V
3
-55
o
C
-100
-
nA
IOZH
VDD = 20
1
+25
o
C
-
100
nA
2
+125
o
C
-
1000
nA
VDD = 18V
3
-55
o
C
-
100
nA
On Resistance
RON5
VC = VDD, RL = 10kW
returned to VDD -
VSS/2
VIS = VSS to VDD
VDD = 5V
1
+25
o
C
1050
-
RON10
VDD = 10V
1
+25
o
C
400
-
RON15
VDD = 15V
1
+25
o
C
240
-
On Resistance
RON5
VDD = 5V
1, 2
+125
o
C
-
1300
-55
o
C
-
800
On Resistance
RON10
VDD = 10V
1, 2
+125
o
C
-
550
-55
o
C
-
310
On Resistance
RON15
VDD = 15V
1, 2
+125
o
C
-
320
-55
o
C
-
220
Functional
(Note 3)
F
VDD = 2.8V, VIN = VDD or GND
7
+25
o
C
VOH >
VDD/2
VOL <
VDD/2
V
VDD = 20V, VIN = VDD or GND
7
+25
o
C
VDD = 18V, VIN = VDD or GND
8A
+125
o
C
VDD = 3V, VIN = VDD or GND
8B
-55
o
C
Switch Threshold
RL = 100k to VDD
SWTHRH5 VDD = 5V, VC = 1.5V, VIS = GND
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
4.1
-
V
SWTHRH15 VDD = 15V, VC = 2V, VIS = GND
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
14.1
-
V
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10
A
1
+25
o
C
-2.8
-0.7
V
P Threshold Voltage
VPTH
VSS = 0V, IDD = 10
A
1
+25
o
C
0.7
2.8
V
7-968
Specifications CD4066BMS
Control Input Low
Voltage (Note 2)
|IIS| < 10
a, VIS = VSS,
VOS = VDD and
VIS = VDD, VOS = VSS
VILC5
VDD = 5V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
1
V
VILC15
VDD = 15V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
2
V
Control Input High
Voltage
(Note 2, Figure 2)
VIS = VSS and VIS =
VDD
VIHC
VDD = 5V, |IIS| = .51mA, 4.6V <
VOS < 0.4V
1
+25
o
C
3.5
-
V
VDD = 5V, |IIS| = .36mA, 4.6V <
VOS < 0.4V
2
+125
o
C
3.5
-
V
VDD = 5V, |IIS| = .64mA, 4.6V <
VOS < 0.4V
3
-55
o
C
3.5
-
V
VIHC
VDD = 15V, |IIS| = 3.4mA, 13.5V <
VOS <1.5V
1
+25
o
C
11
-
V
VDD = 15V, |IIS| = 2.4mA, 13.5V <
VOS < 1.5V
2
+125
o
C
11
-
V
VDD = 15V, |IIS| = 4.2mA, 13.5V <
VOS <1.5V
3
-55
o
C
11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
3. VDD = 2.8V/3.0V, RL = 100K to VDD
VDD = 20V/18V, RL = 10K to VDD
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Propagation Delay
Signal Input to Signal
Output
TPLH
TPHL
VC = VDD = 5V, VSS = GND
(Notes 2, 3)
9
+25
o
C
-
40
ns
10, 11
+125
o
C, -55
o
C
-
54
ns
Propagation Delay
Turn-On, Turn-Off
TPHZ/ZH
TPLZ/ZL
VIS = VDD = 5V (Notes 1, 2)
9
+25
o
C
-
70
ns
10, 11
+125
o
C, -55
o
C
-
95
ns
NOTES:
1. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
2. -55
o
C and +125
o
C limits guaranteed, 100% testing being implemented.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Supply Current
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
-
0.25
A
+125
o
C
-
7.5
A
VDD = 10V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
-
0.5
A
+125
o
C
-
15
A
VDD = 15V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
-
0.5
A
+125
o
C
-
30
A
Control Input Low
Voltage
|IIS| < 10
a, VIS = VSS,
VOS = VDD and
VIS = VDD, VOS = VSS
VILC10
VDD = 10V
1, 2
+25
o
C, +125
o
C,
-55
o
C
-
2
V
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
GROUP A
SUBGROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
7-969
Specifications CD4066BMS
Control Input High
Voltage (See Figure 2)
VIHC10
VDD = 10V, VIS = VDD or GND
2
+25
o
C, +125
o
C,
-55
o
C
7
-
V
Propagation Delay
Signal Input to
Signal Output
TPLH
TPHL
VDD = 10V
1, 2, 3
+25
o
C
-
20
ns
VDD = 15V
1, 2, 3
+25
o
C
-
15
ns
Propagation Delay
Turn-On, Turn-Off
TPHZ/ZH
TPLZ/ZL
VDD = 10V
1, 2, 3
+25
o
C
-
40
ns
VDD = 15V
1, 2, 3
+25
o
C
-
30
ns
Input Capacitance
CIN
Any Input
1, 2
+25
o
C
-
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Supply Current
IDD
VDD = 20V, VIN = VDD or GND
1, 4
+25
o
C
-
25
A
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10
A
1, 4
+25
o
C
-2.8
-0.2
V
N Threshold Voltage
Delta
VTN
VDD = 10V, ISS = -10
A
1, 4
+25
o
C
-
1
V
P Threshold Voltage
VTP
VSS = 0V, IDD = 10
A
1, 4
+25
o
C
0.2
2.8
V
P Threshold Voltage
Delta
VTP
VSS = 0V, IDD = 10
A
1, 4
+25
o
C
-
1
V
Functional
F
VDD = 18V, VIN = VDD or GND
1
+25
o
C
VOH >
VDD/2
VOL <
VDD/2
V
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
1, 2, 3, 4
+25
o
C
-
1.35 x
+25
o
C
Limit
ns
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25
o
C limit.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25
O
C
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - SSI
IDD
0.1
A
ON Resistance
RONDEL10
20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
READ AND RECORD
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A, RONDEL10
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A, RONDEL10
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A, RONDEL10
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A, RONDEL10
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
970
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Specifications CD4066BMS
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
MIL-STD-883
METHOD
TEST
READ AND RECORD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION
OPEN
GROUND
VDD
9V
-0.5V
OSCILLATOR
50kHz
25kHz
Static Burn-In 1 (Note 1)
2, 3, 9, 10
1, 4-8, 11-13
14
Static Burn-In 2 (Note 1)
2, 3, 9, 10
7
1, 4-6, 8, 11-14
Dynamic Burn-In (Note 1)
-
7
14
2, 3, 9, 10
5, 6, 12, 13
1, 4, 8, 11
Irradiation (Note 2)
2, 3, 9, 10
7
1, 4-6, 8, 11-14
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K
5%, VDD = 18V
0.5V
2. Each pin except VDD and GND will have a series resistor of 47K
5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V
0.5V
Functional Diagram
TRUTH TABLE EACH SWITCH
INPUT
OUTPUT
VC
VIS
VOS
1
0
0
1
1
1
0
0
Open
0
1
Open
Positive Logic: Switch ON VC = "1"
Switch OFF VC = "0"
TABLE 6. APPLICABLE SUBGROUPS
(Continued)
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
READ AND RECORD
IN/OUT
OUT/IN
OUT/IN
IN/OUT
CONTROL B
CONTROL C
VSS
VDD
CONTROL A
CONTROL D
IN/OUT
OUT/IN
OUT/IN
IN/OUT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
SW
A
SIG A
SW
D
SW
B
SW
C
SIG B
SIG C
SIG D