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1
FN7393.1
EL5525
18-Channel TFT-LCD Reference Voltage
Generator
The EL5525 is designed to produce the reference voltages
required in TFT-LCD applications. Each output is
programmed to the required voltage with 10 bits of
resolution. Reference pins determine the high and low
voltages of the output range, which are capable of swinging
to either supply rail. Programming of each output is
performed using the serial interface. A serial out pin enables
daisy chaining of multiple devices.
A number of the EL5525 can be stacked for applications
requiring more than 18 outputs. The reference inputs can be
tied to the rails, enabling each part to output the full voltage
range, or alternatively, they can be connected to external
resistors to split the output range and enable finer
resolutions of the outputs.
The EL5525 has 18 outputs and comes in a 38-pin HTSSOP
package. It is specified for operation over the full -40C to
+85C temperature range.
Features
18-channel reference outputs
Accuracy of 0.1%
Supply voltage of 4.5V to 16.5V
Digital supply 3.3V to 5V
Low supply current of 15mA
Rail-to-rail capability
Internal thermal protection
Pb-Free plus anneal available (RoHS compliant)
Applications
TFT-LCD drive circuits
Reference voltage generators
Pinout
EL5525
(38-PIN HTSSOP)
TOP VIEW
Ordering Information
PART
NUMBER
PACKAGE
TAPE &
REEL
PKG. DWG. #
EL5525IRE
38-Pin HTSSOP
-
MDP0048
EL5525IRE-T7
38-Pin HTSSOP
7"
MDP0048
EL5525IRE-T13
38-Pin HTSSOP
13"
MDP0048
EL5525IREZ
(See Note)
38-Pin HTSSOP
(Pb-Free)
-
MDP0048
EL5525IREZ-T7
(See Note)
38-Pin HTSSOP
(Pb-Free)
7"
MDP0048
EL5525IREZ-T13
(See Note)
38-Pin HTSSOP
(Pb-Free)
13"
MDP0048
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
2
3
4
38
37
36
35
5
6
7
34
33
32
8
31
9
10
30
29
11
12
13
28
27
26
14
25
15
24
16
17
18
23
22
21
19
20
THERMAL
PAD
ENA
SDI
SCLK
SDO
EXT_OSC
VS
VSD
NC
NC
OSC_SELECT
VS
REFH
REFL
GND
CAP
VS
NC
OUTR
OUTQ
OUTA
GND
OUTF
OUTB
OUTG
OUTE
OUTH
OUTO
OUTP
OUTI
OUTK
GND
GND
OUTJ
OUTM
OUTL
OUTN
OUTC
OUTD
Data Sheet
August 1, 2005
PRELIMINARY
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004-2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
FN7393.1
August 1, 2005
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
Absolute Maximum Ratings
(T
A
= 25C)
Supply Voltage between V
S
and GND. . . . . . 4.5V(min) to 18V(max)
Supply Voltage between V
SD
and GND 3V(min) to V
S
and +7(max)
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 125C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
V
S
= 15V, V
SD
= 5V, V
REFH
= 13V, V
REFL
= 2V,
R
L
= 1.5k
and
C
L
= 200pF to 0V, T
A
= 25C, unless
otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
I
S
Supply Current
No load
15
18
mA
I
SD
Digital Supply Current
0.17
0.35
mA
ANALOG
V
OL
Output Swing Low
Sinking 5mA (V
REFH
= 15V, V
REFL
= 0)
50
150
mV
V
OH
Output Swing High
Sourcing 5mA (V
REFH
= 15V, V
REFL
= 0)
14.85
14.95
V
I
SC
Short Circuit Current
R
L
= 10
100
140
mA
PSRR
Power Supply Rejection Ratio
V
S
+ is moved from 14V to 16V
45
60
dB
t
D
Program to Out Delay
4
ms
V
AC
Accuracy Referred to the Ideal Value
Code = 512
20
mV
V
MIS
Channel to Channel Mismatch
Code = 512
2
mV
V
DROOP
Droop Voltage
1
2
mV/ms
R
INH
Input Resistance @ V
REFH
, V
REFL
34
k
REG
Load Regulation
I
OUT
= 5mA step
0.5
1.5
mV/mA
BG
Band Gap
1.1
1.3
1.6
V
DIGITAL
V
IH
Logic 1 Input Voltage
2
V
V
IL
Logic 0 Input Voltage
1
V
F
CLK
Clock Frequency
5
MHz
t
S
Setup Time
20
ns
t
H
Hold Time
20
ns
t
LC
Load to Clock Time
20
ns
t
CE
Clock to Load Line
20
ns
t
DCO
Clock to Out Delay Time
Negative edge of SCLK
10
ns
R
SDIN
S
DIN
Input Resistance
1
G
T
PULSE
Minimum Pulse Width for EXT_OSC
Signal
5
s
Duty Cycle
Duty Cycle for EXT_OSC Signal
50
%
F_OSC
Internal Refresh Oscillator Frequency
OSC_Select = 0
21
kHz
INL
Integral Nonlinearity Error
1.3
LSB
DNL
Differential Nonlinearity Error
0.5
LSB
EL5525
3
FN7393.1
August 1, 2005
Pin Descriptions
PIN NUMBER
PIN NAME
PIN TYPE
PIN DESCRIPTION
1
ENA
Logic Input
Chip select, low enables data input to logic
2
SDI
Logic Input
Serial data input
3
SCLK
Logic Input
Serial data clock
4
SDO
Logic Output
Serial data output
5
EXT_OSC
Input/Output
Oscillator pin for synchronizing
6, 11, 16
VS
Power
Positive supply voltage for analog circuits (4.5V - 16.5V)
7
VSD
Power
Positive power supply for digital circuites (3.3V - 5V)
8, 9, 17
NC
Not connected
10
OSC_SELECT
Oscillator select, "0" = internal, "1" = external
12
REFH
Analog Input
High reference voltage
13
REFL
Analog Input
Low reference voltage
14, 24, 28, 35
GND
Power
Ground
15
CAP
Analog
Decoupling capacitor for internal reference
18
OUTR
Analog Output
Channel R output voltage
19
OUTQ
Analog Output
Channel Q output voltage
20
OUTP
Analog Output
Channel P output voltage
21
OUTO
Analog Output
Channel O output voltage
22
OUTN
Analog Output
Channel N output voltage
23
OUTM
Analog Output
Channel M output voltage
25
OUTL
Analog Output
Channel L output voltage
26
OUTK
Analog Output
Channel K output voltage
27
OUTJ
Analog Output
Channel J output voltage
29
OUTI
Analog Output
Channel I output voltage
30
OUTH
Analog Output
Channel H output voltage
31
OUTG
Analog Output
Channel G output voltage
32
OUTF
Analog Output
Channel F output voltage
33
OUTE
Analog Output
Channel E output voltage
34
OUTD
Analog Output
Channel D output voltage
36
OUTC
Analog Output
Channel C output voltage
37
OUTB
Analog Output
Channel B output voltage
38
OUTA
Analog Output
Channel A output voltage
EL5525
4
FN7393.1
August 1, 2005
Typical Performance Curves
FIGURE 1. DIFFERENTIAL NONLINEARITY vs CODE
FIGURE 2. INTEGRAL NONLINEARITY ERROR
FIGURE 3. TRANSIENT LOAD REGULATION (SOURCING)
FIGURE 4. TRANSIENT LOAD REGULATION (SINKING)
FIGURE 5. LARGE SIGNAL RESPONSE (RISING FROM 0V
TO 8V)
FIGURE 6. SMALL SIGNAL RESPONSE (FALLING FROM
200mV TO 100mV)
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
10
210
410
610
810
1010
INPUT CODE
DIFFERENTIAL NONL
INEARITY
(LS
B
)
V
S
=15V
V
SD
=5V
V
REFH
=13V
V
REFL
=2V
-1
-0.5
0
0.5
1
1.5
0
200
400
600
800
1000
1200
CODE
INL (L
SB)
REFH=13V, REFL=2V
0mA
5V
5mA/DIV
200mV/DIV
5mA
V
S
=V
REFH
=15V
C
L
=180pF
C
L
=1nF
R
S
=20
C
L
=4.7nF
R
S
=20
V
S
=V
REFH
=15V
5mA
0mA
C
L
=4.7nF
R
S
=20
C
L
=1nF
R
S
=20
C
L
=180pF
5mA/DIV
200mV/DIV
M=400ns/DIV
SCLK
SDA
ENA
OUTA
M=200s/DIV
SCLK
SDA
ENA
OUTA
M=200s/DIV
EL5525
M=400ns/DIV
5
FN7393.1
August 1, 2005
General Description
The EL5525 provides a versatile method of providing the
reference voltages that are used in setting the transfer
characteristics of LCD display panels. The V/T
(Voltage/Transmission) curve of the LCD panel requires that
a correction is applied to make it linear; however, if the panel
is to be used in more than one application, the final curve
may differ for different applications. By using the EL5525,
the V/T curve can be changed to optimize its characteristics
according to the required application of the display product.
Each of the eight reference voltage outputs can be set with a
10-bit resolution. These outputs can be driven to within
50mV of the power rails of the EL5525. As all of the output
buffers are identical, it is also possible to use the EL5525 for
applications other than LCDs where multiple voltage
references are required that can be set to 10 bit accuracy.
Digital Interface
The EL5525 uses a simple 3-wire SPI compliant digital
interface to program the outputs. The EL5525 can support
the clock rate up to 5MHz.
Serial Interface
The EL5525 is programmed through a three-wire serial
interface. The start and stop conditions are defined by the
ENA signal. While the ENA is low, the data on the SDI (serial
data input) pin is shifted into the 16-bit shift register on the
positive edge of the SCLK (serial clock) signal. The MSB
(bit 15) is loaded first and the LSB (bit 0) is loaded last (see
Table 1). After the full 16-bit data has been loaded, the ENA
is pulled high and the addressed output channel is updated.
The SCLK is disabled internally when the ENA is high. The
SCLK must be low before the ENA is pulled low.
To facilitate the system designs that use multiple EL5525
chips, a buffered serial output of the shift register (SDO pin)
is available. Data appears on the SDO pin at the 16th falling
SCLK edge after being applied to the SDI pin.
To control the multiple EL5525 chips from a single three-wire
serial port, just connect the ENA pins and the SCLK pins
together, connect the SDO pin to the SDI pin on the next
chip. While the ENA is held low, the 16m-bit data is loaded to
the SDI input of the first chip. The first 16-bit data will go to
the last chip and the last 16-bit data will go to the first chip.
While the ENA is held high, all addressed outputs will be
updated simultaneously.
The Serial Timing Diagram and parameters table show the
timing requirements for three-wire signals.
The serial data has a minimum length of 16 bits, the MSB
(most significant bit) is the first bit in the signal. The bits are
allocated to the following functions (also refer to the Control
Bits Logic Table)
Bit 15 is always set to a zero
Bits 14 through 10 select the channel to be written to, these
are binary coded with channel A = 0, and channel R = 17
The 10-bit data is on bits 9 through 0. Some examples of
data words are shown in the table of Serial Programming
Examples
Serial Timing Diagram
TABLE 1. CONTROL BITS LOGIC TABLE
BIT
NAME
DESCRIPTION
B15
Test
Always 0
B14
A4
Channel Address
B13
A3
Channel Address
B12
A2
Channel Address
B11
A1
Channel Address
B10
A0
Channel Address
B9
D9
Data
B8
D8
Data
B7
D7
Data
B6
D6
Data
B5
D5
Data
B4
D4
Data
B3
D3
Data
B2
D2
Data
B1
D1
Data
B0
D0
Data
B15
B14
B13
B12-B2
B1
B0
ENA
SCLK
SDI
MSB
LSB
t
t
HE
t
SE
t
SD
t
HD
T
t
r
t
w
t
HE
t
SE
LOAD MSB FIRST, LSB LAST
t
f
EL5525
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