1
File Number
2907.4
HA-5135
2.5MHz, Precision Operational Amplifier
The Intersil HA-5135 is a precision operational amplifier
manufactured using a combination of key technological
advancements to provide outstanding input characteristics.
A Super Beta input stage is combined with laser trimming,
dielectric isolation and matching techniques to produce
75
V (Maximum) input offset voltage and 0.4
V/
o
C input
offset voltage average drift. Other features enhanced by this
process include 9nV/
Hz (Typ) Input Noise Voltage, 1nA
Input Bias Current and 140dB Open Loop Gain.
These features coupled with 120dB CMRR and PSRR make
the HA-5135 an ideal device for precision DC instrumentation
amplifiers. Excellent input characteristics in conjunction with
2.5MHz bandwidth and 0.8V/
s slew rate, make this
amplifier extremely useful for precision integrator and
biomedical amplifier designs. This amplifier is also well
suited for precision data acquisition and for accurate
threshold detector applications.
HA-5135 offers added features over the industry standard
OP-07 in regards to bandwidth and slew rate specifications.
For the military grade product, refer to the HA-5135/883 data
sheet.
Pinout
HA-5135
(CERDIP)
TOP VIEW
NOTE: Both BAL 1 pins are connected together internally.
Features
Low Offset Voltage . . . . . . . . . . . . . . . . . . . . . 75
V (Max)
Low Offset Voltage Drift . . . . . . . . . . . . . . . . . . . 0.4
V/
o
C
Low Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9nV/
Hz
Open Loop Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 140dB
Unity Gain Bandwidth. . . . . . . . . . . . . . . . . . . . . . 2.5MHz
All Bipolar Construction
Applications
High Gain Instrumentation
Precision Data Acquisition
Precision Integrators
Biomedical Amplifiers
Precision Threshold Detectors
1
2
3
4
8
7
6
5
V+
OUT
BAL
V-
+
BAL 1
BAL 1
-IN
+IN
-
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
HA7-5135-5
0 to 75
8 Ld CERDIP
F8.3A
Data Sheet
April 1999
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Copyright
Intersil Corporation 1999
2
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . 40V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Output Short Circuit Duration. . . . . . . . . . . . . . . . . . . . . . . Indefinite
Operating Conditions
Temperature Ranges
HA-5135-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 75
o
C
Thermal Resistance (Typical, Note 2)
JA
(
o
C/W)
JC
(
o
C/W)
CERDIP Package . . . . . . . . . . . . . . . . .
135
50
Maximum Junction Temperature (Note 1) . . . . . . . . . . . . . . . . 175
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Maximum power dissipation, including output load, must be designed to maintain the maximum junction temperature below 175
o
C.
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V
SUPPLY
=
15V
PARAMETER
TEST CONDITIONS
TEMP.
(
o
C)
HA-5135-5
UNITS
MIN
TYP
MAX
INPUT CHARACTERISTICS
Offset Voltage
25
-
10
75
V
Full
-
50
130
V
Average Offset Voltage Drift
Full
-
0.4
1.3
V/
o
C
Bias Current
25
-
1
4
nA
Full
-
-
6
nA
Bias Current Average Drift
Full
-
0.02
0.04
nA/
o
C
Offset Current
25
-
-
4
nA
Full
-
-
5.5
nA
Offset Current Average Drift
Full
-
0.02
0.04
nA/
o
C
Common Mode Range
Full
12
-
-
V
Differential Input Resistance
25
20
30
-
M
Input Noise Voltage (Note 3)
0.1Hz to 10Hz
25
-
-
0.6
V
P-P
Input Noise Voltage Density
(Note 3)
f = 10Hz
25
-
13.0
18.0
nV/
Hz
f = 100Hz
-
10.0
13.0
nV/
Hz
f = 1000Hz
-
9.0
11.0
nV/
Hz
Input Noise Current (Note 3)
0.1Hz to 10Hz
25
-
15
30
pA
P-P
Input Noise Current Density
(Note 3)
f = 10Hz
25
-
0.4
0.8
pA/
Hz
f = 100Hz
-
0.17
0.23
pA/
Hz
f = 1000Hz
-
0.14
0.17
pA/
Hz
TRANSFER CHARACTERISTICS
Large Signal Voltage Gain
V
OUT
=
10V, R
L
= 2k
25
120
140
-
dB
Full
120
-
-
dB
Common Mode Rejection Ratio
V
CM
=
10V
Full
106
120
-
dB
Closed Loop Bandwidth
A
VCL
= +1
25
0.6
2.5
-
MHz
OUTPUT CHARACTERISTICS
Output Voltage Swing
R
L
= 600
25
10
12
-
V
Full
10
-
-
V
HA-5135
3
Full Power Bandwidth (Note 4)
R
L
= 2k
25
8
10
-
kHz
Output Current
V
OUT
= 10V
25
15
20
-
mA
Output Resistance
Note 5
25
-
45
-
TRANSIENT RESPONSE (Note 6)
Rise Time
25
-
340
-
ns
Slew Rate
25
0.5
0.8
-
V/
s
Settling Time (Note 7)
25
-
11
-
s
POWER SUPPLY CHARACTERISTICS
Supply Current
Full
-
1.0
1.7
mA
Power Supply Rejection Ratio
V
S
=
5V to
20V
Full
94
130
-
dB
NOTES:
3. Not tested. 90% of units meet or exceed these specifications.
4. Full power bandwidth guaranteed based on slew rate measurement using:
.
5. Output resistance measured under open loop conditions (f = 100Hz).
6. Refer to test circuits section of the data sheet.
7. Settling time is measured to 0.1% of final value for a 10V output step and A
V
= -1.
Electrical Specifications
V
SUPPLY
=
15V (Continued)
PARAMETER
TEST CONDITIONS
TEMP.
(
o
C)
HA-5135-5
UNITS
MIN
TYP
MAX
FPBW
Slew Rate
2
V
PEAK
-------------------------------
=
Test Circuits and Waveforms
FIGURE 1. SLEW RATE AND TRANSIENT RESPONSE TEST CIRCUIT
SMALL SIGNAL RESPONSE
LARGE SIGNAL RESPONSE
IN
100pF
OUT
2k
+
-
OUTPUT
INPUT
0V
0V
Vertical Scale: Input = 50mV/Div. Output = 100mV/Div.
Horizontal Scale: 1
s/Div.
OUTPUT
INPUT
0V
0V
Vertical Scale: 5V/Div.
Horizontal Scale: 5
s/Div.
HA-5135
4
Schematic Diagram
FIGURE 2. SETTLING TIME CIRCUIT
Test Circuits and Waveforms
(Continued)
+
-
A.U.T.
+15V
-15V
2k
100pF
V
OUT
5k
5k
2k
V
IN
2k
TO
OSCILLOSCOPE
2N4416
+15V
NOTES:
8. A
V
= -1.
9. Feedback and summing resistors
should be 0.1% matched.
10. Clipping diodes are optional.
HP5082-2810 recommended.
R
9
Q
35
Q
22
BALANCE
R
11
Q
56
R
7
Q
55
Q
19
Q
21
C
3
Q
8
Q
17
Q
20
R
6
Q
57
R
12
Q
37
C
2
R
8
Q
36
Q
38
Q
40
Q
39
Q
28
Q
27
Q
24
C
4
C
1
Q
14
Q
12
Q
2
Q
4
Q
15
Q
16
Q
9
Q
10
Q
6
Q
5
Q
11
Q
13
Q
1
Q
3
R
3
(-) INVERTING
INPUT
Q
52
Q
7
Q
53
R
P18
Q
46
R
19
Q
48
Q
50
Q
41
Q
49
Z
1
R
13
R
20
R
14
R
2
R
17
Q
25
Q
26
Q
42
Q
51
Q
31
(+) NON-
INPUT
INVERTING
Q
45
Q
34
Q
30
R
15
OUT
R
16
Q
33
Q
47
Q
32
Q
43
Q
58
Q
44
V+
V-
Q
54
Q
18
R
4
R
10
R
5
HA-5135
5
Application Information
Power Supply Decoupling
Although not absolutely necessary, it is recommended that
all power supply lines be decoupled with 0.01
F ceramic
capacitors to ground. Decoupling capacitors should be
located as near to the amplifier terminals as possible.
Considerations For Prototyping:
The following list of recommendations are suggested for
prototyping.
1. Resolving low level signals requires minimizing leakage
currents caused by external circuitry. Use of quality
insulating materials, thorough cleaning of insulating
surfaces and implementation of moisture barriers when
required is suggested.
2. Error voltages generated by thermocouples formed
between dissimilar metals in the presence of temperature
gradients should be minimized. Isolation of low level
circuity from heat generating components is
recommended.
3. Shielded cable input leads, guard rings and shield drivers
are recommended for the most critical applications.
Large Capacitive Loads
When driving large capacitive loads (>500pF), a small value
resistor (
50
) should be connected in series with the
output and inside the feedback loop.
Offset Voltage Adjustment (See Figure 3)
A 20k
balance potentiometer is recommended if offset
nulling is required. However, other potentiometer values
such as 10k
, 50k
and 100k
may be used. The
minimum adjustment range for given values is
2mV. V
OS
TC of the amplifier is optimized at minimal V
OS
. Tested
Offset Adjustment is |V
OS
+ 1mV| minimum referred
to output.
Saturation Recovery
Input and output saturation recovery time is negligible in
most applications. However, care should be exercised to
avoid exceeding the absolute maximum ratings of the
device.
Differential Input Voltages
Inputs are shunted with back-to-back diodes for overvoltage
protection. In applications where differential input voltages in
excess of 1V are applied between the inputs, the use of
limiting resistors at the inputs is recommended.
Typical Applications
The excellent input and gain characteristics of HA-5135 are
well suited for precision integrator applications. Accurate
integration over seven decades of frequency using HA-5135,
virtually nullifies the need for more expensive chopper-type
amplifiers.
Low V
OS
coupled with high open loop Gain, high CMRR
and high PSRR make HA-5135 ideally suited for precision
detector applications, such as the zero crossing detector
shown in Figure 5.
2
6
1
7
8
V+
+
4
3
5
R
P
(NOTE)
20k
OPTIONAL
CONNECTION
-
FIGURE 3. OFFSET NULLING CONNECTIONS
2
1
7
8
+
4
3
5
R
B
C
6
R
OUT
-
FIGURE 4. PRECISION INTEGRATOR
HA-5135
6
FIGURE 5. ZERO CROSSING DETECTOR
FIGURE 6. PRECISION INSTRUMENTATION AMPLIFIER
2
1
7
8
+
4
3
5
6
OUT
R
IN
INPUT
OPTIONAL FOR OUTPUT
SWING LIMITING
OUTPUT
13V
200
s/DIV.
INPUT
5mV
200
s/DIV.
R
F
-
4.5k
500
4.5k
HA-5135
-15V
+15V
2k
2k
2k
HA-5135
+15V
2k
-15V
HA-5135
NOTE: A
V
= 100
+
-
+
-
+
-
Typical Performance Curves
FIGURE 7. INPUT OFFSET VOLTAGE, INPUT BIAS AND
OFFSET CURRENT vs TEMPERATURE
FIGURE 8. INPUT BIAS CURRENT vs DIFFERENTIAL INPUT
VOLTAGE
80
70
60
50
40
-80
40
160
TEMPERATURE (
o
C)
INPUT OFFSET V
O
L
T
A
GE (
V)
INPUT BIAS CURRENT
30
20
10
120
80
-40
0
INPUT OFFSET CURRENT
TYPICAL
0
4
3
2
1
0
4
2
0
-4
-2
INPUT OFFSET
CURRENT (nA)
INPUT BIAS
CURRENT (nA)
|V
OS
|
6
4
2
-10
-4
-2
DIFFERENTIAL INPUT VOLTAGE (V)
BIAS CURRENT (nA)
0
-8
-6
10
4
2
8
6
0
-2
-4
-6
HA-5135
7
FIGURE 9. HA-5135 OFFSET VOLTAGE STABILITY vs TIME
FIGURE 10. INPUT NOISE vs FREQUENCY
FIGURE 11. OPEN LOOP FREQUENCY RESPONSE
FIGURE 12. CLOSED LOOP FREQUENCY RESPONSE
FIGURE 13. SMALL SIGNAL BANDWIDTH AND PHASE
MARGIN vs LOAD CAPACITANCE
FIGURE 14. OUTPUT VOLTAGE SWING vs FREQUENCY
Typical Performance Curves
(Continued)
10
5
0
-5
-10
2
6
30
TIME (DAYS)
T
O
T
AL DRIFT WITH TIME (
V)
V
SUPPLY
=
15V
20
4
T
C
=
1
o
C, A
V
= 1000
MEASUREMENT AND ENVIRONMENTAL
SYSTEMS ALLOWED 12 HOUR
STABILIZATION PERIOD
8 10
40
FREQUENCY (Hz)
14
12
10
INPUT NOISE V
O
L
T
A
GE (nV/
Hz)
10
10K
100
1K
NOISE VOLTAGE
NOISE CURRENT
8
6
4
2
0
1.4
1.2
1.0
INPUT NOISE CURRENT (pA/
Hz)
0.8
0.6
0.4
0.2
0
100K
FREQUENCY (Hz)
100K
10M
1K
100
10
160
140
120
100
-20
0
20
40
60
80
PHASE ANGLE
GAIN
1
10K
1M
OPEN LOOP V
O
L
T
A
GE GAIN (dB)
0
45
90
135
180
PHASE (DEGREES)
FREQUENCY (Hz)
CLOSED LOOP GAIN (dB)
80
0
10
20
30
40
50
60
70
-10
100K
10M
1K
100
10
1
10K
1M
LOAD CAPACITANCE (pF)
10,000
100
10
PHASE MARGIN (DEGREES)
60
1000
PHASE MARGIN
BANDWIDTH
50
40
30
20
10
0
2.6
2.5
2.4
2.35
UNITY GAIN B
AND
WIDTH (MHz)
OUTPUT V
O
L
T
A
GE SWING (V
P-P
)
10
20
35
R
L
= 2k
V
SUPPLY
=
20V
25
15
5
30
V
SUPPLY
=
15V
V
SUPPLY
=
10V
V
SUPPLY
=
5V
FREQUENCY (Hz)
100K
1K
100
10K
1M
HA-5135
8
FIGURE 15. MAXIMUM OUTPUT VOLTAGE SWING vs LOAD
RESISTANCE
FIGURE 16. NORMALIZED AC PARAMETERS vs SUPPLY
VOLTAGE
FIGURE 17. CMRR vs FREQUENCY
FIGURE 18. PSRR vs FREQUENCY
FIGURE 19. SETTLING TIME FOR VARIOUS OUTPUT STEP
VOLTAGES
FIGURE 20. POWER SUPPLY CURRENT vs TEMPERATURE
Typical Performance Curves
(Continued)
30
25
20
15
10
1
100
10K
LOAD RESISTANCE (
)
5
1K
10
OUTPUT V
O
L
T
A
GE SWING (V
P-P
)
V
SUPPLY
=
15V
V
SUPPLY
=
10V
V
SUPPLY
=
5V
0
1.1
1.0
0.9
0.8
2
16
18
20
SUPPLY VOLTAGE (
V)
NORMALIZED A
C
P
ARAMETERS
4
6
8
10
12
14
0.7
0.6
0
BANDWIDTH
SLEW RATE
REFERRED T
O
V
ALUE A
T
15V
140
120
100
80
60
40
20
0
CMRR (dB)
FREQUENCY (Hz)
10
10K
100
1K
100K
1
FREQUENCY (Hz)
PSRR (dB)
10
10K
100
1K
100K
1
140
120
100
80
60
40
20
0
SETTLING TIME (
s)
0
2
4
6
8
-10
-5
0
5
10
10
12
14
16
TO 10mV
TO 1mV
OUTPUT V
O
L
T
A
GE STEP
- V
O
L
TS FR
OM 0 V
O
L
T
S
TO 10mV
TO 1mV
V
S
=
20V
TEMPERATURE (
o
C)
SUPPL
Y CURRENT (mA)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
-80
40
160
120
80
-40
0
V
S
=
15V
V
S
=
10V
V
S
=
5V
HA-5135
9
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
Die Characteristics
DIE DIMENSIONS:
72 mils x 103 mils x 19 mils
(1840
m x 2620
m x 483
m)
METALLIZATION:
Type: Al, 1% Cu
Thickness: 16k
2k
SUBSTRATE POTENTIAL (POWERED UP):
V-
PASSIVATION:
Type: Nitride (Si
3
N
4
) over Silox (SiO
2
, 5% Phos.)
Silox Thickness: 12k
2k
Nitride Thickness: 3.5k
1.5k
TRANSISTOR COUNT:
71
PROCESS:
Bipolar Dielectric Isolation
Metallization Mask Layout
HA-5135
BAL1
V+
OUT
BAL1
V-
+IN
-IN
BAL2
HA-5135
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