CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

HC55171B

Low Cost 5 REN Ringing SLIC
for ISDN Modem/TA and WL

The HC55171B low cost, 5 REN ringing SLIC is designed to
accommodate a wide variety of short loop applications and
provides the same degree of flexibility as the high
performance HC55171. The flexible features include open
circuit tip to ring DC voltages, user defined ringing
waveforms, ring trip detection thresholds, and loop current
limits that can be tailored for many applications. Additional
features of the HC55171B are complex impedance
matching, pulse metering, and transhybrid balance. The
HC55171B is designed for use in short loop, low cost
systems where traditional ring generation is not
economically feasible.

The device is manufactured in a high voltage Dielectric
Isolation (DI) process. The DI process provides substrate
latch up immunity, resulting in a robust system design. A
thermal shutdown with an alarm output and line fault
protection are also included for operation in harsh
environments.

Features

· Load Drive Capability . . . . . . . . . . . . . . . . . . . . . . . 5 REN

· Trapezoidal, Square or Sine Wave Capability

· Ringing from -80V Battery . . . . . . . . . . . . . . . . . . . 75V

P-P

· Ringing from -75V Battery . . . . . . . . . . . . . . . . . . . 70V

P-P

· Ringing Current Independent of Loop Current Setting

· Ringing Crest Factor Independent of REN Loading

· Latchup Immune to Inductive Kick Back and Hot Plug

· Fax, Answering Machine and MTU Compatible

· Resistive and Complex Impedance Matching

· Programmable Loop Current Limit

· Switch Hook, Ring Trip and Ground Key Detection

· Single Low Voltage +5V Supply

Applications

· Solid State Line Interface Circuit for Hybrid Fiber Coax, Set

Top Box, Voice/Data Modems

· Related Literature

- AN9607, Impedance Matching Design Equations

- AN9628, AC Voltage Gain

- AN9636, Implementing an Analog Port for ISDN

- AN549, The HC-5502/4X Telephone SLIC

Block Diagram

Ordering Information

PART

NUMBER

TEMP. RANGE

(

PACKAGE

PKG. NO.

HC55171BIM

-40 to 85

28 Ld PLCC

N28.45

HC55171BIB

-40 to 85

28 Ld SOIC

M28.3

TIP FEED

TIP SENSE

RING FEED

RING SENSE 2

BAT

AGND

BGND

4-WIRE

INTERFACE

BIAS

- IN 1

OUT 1

RING

LOOP CURRENT

DETECTOR

SHD

RTD

ALM
I

LIMIT

FAULT

DETECTOR

CURRENT

LIMIT

TST

RDI

IIL LOGIC INTERFACE

REF

RELAY

DRIVER

RDO

2-WIRE

INTERFACE

RTI

RING TRIP

DETECTOR

RING SENSE 1

Data Sheet

July 1998

File Number

4422.1

Absolute Maximum Ratings

= 25

Thermal Information

Maximum Supply Voltages

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V

)-(V

BAT

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90V

Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +15V

Operating Conditions

Temperature Range

HC55171BIM, HC55171BIB . . . . . . . . . . . . . . . . . . -40

C to 85

Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to +12V
Positive Power Supply (V

) . . . . . . . . . . . . . . . . . . . . . . . +5V

Negative Power Supply (V

BAT

). . . . . . . . . . . . . . . . . . . -16V to -80V

Thermal Resistance (Typical, Note 1)

(

C/W)

PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature, Plastic Packages . . . . . . . . 150

Maximum Storage Temperature Range . . . . . . . . . .-65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300

(SOIC, PLCC - Lead Tips Only)

Die Characteristics

Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Diode Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 x 144
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

BAT

Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
ESD (Human Body Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied

NOTES:

is measured with the component mounted on an evaluation board PC board in free air.

2. All grounds (AGND, BGND) must be applied before V

or V

BAT

. Failure to do so may result in premature failure of the part. If a user

wishes to run separate grounds off a line card, the AGND must be applied first.

Electrical Specifications

Unless Otherwise Specified, Typical Parameters are at T

= 25

C, Min-Max Parameters are over

Operating Temperature Range, V

BAT

= -24V, V

= +5V, AGND = BGND = 0V. All AC Parameters are specified

at 600

2-Wire terminating impedance.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

RINGING TRANSMISSION PARAMETERS

RING

Input Impedance

(Note 3)

5.4

4-Wire to 2-Wire Gain

RING

to V

T-R

(Note 3)

V/V

AC TRANSMISSION PARAMETERS

RX Input Impedance

300Hz to 3.4kHz (Note 3)

108

OUT1 Positive Output Voltage Swing

= 10k

(Note 3)

+2.5

OUT1 Negative Output Voltage Swing

= 10k

(Note 3)

-4.5

4-Wire Input Overload Level

300Hz to 3.4kHz R

= 1200

, 600

Reference

(Note 3)

+3.1

PEAK

2-Wire Return Loss

Matched for 600

, f = 300Hz (Note 3)

Matched for 600

, f = 1000Hz (Note 3)

Matched for 600

, f = 3400Hz (Note 3)

2-Wire Longitudinal to Metallic Balance
Off Hook

Per ANSI/IEEE STD 455-1976 300Hz to 3400Hz
(Note 3)

4-Wire Longitudinal Balance Off Hook

300Hz to 3400Hz (Note 3)

Longitudinal Current Capability

LINE

= 40mA, T

= 25

C (Note 3)

RMS

Insertion Loss, 2-Wire to 4-Wire

0dBmO, 1kHz, Includes Transhybrid Amp Gain = 3

0.05

0.2

Insertion Loss, 4-Wire to 2-Wire

0dBmO,1kHz

0.05

0.2

Insertion Loss, 4-Wire to 4-Wire

0dBmO, 1kHz, Includes Transhybrid Amp Gain = 3

0.35

Frequency Response

300Hz to 3400Hz Referenced to Absolute Level
at 1kHz, 0dBm Referenced 600

0.02

0.06

HC55171B

Level Linearity

+3 to 0dBm, Referenced to -10dBm (Note 3)

0.10

0 to -40dBm, Referenced to -10dBm (Note 3)

0.12

-40 to -55dBm, Referenced to -10dBm (Note 3)

0.30

Absolute Delay, 2-Wire to 4-Wire

300Hz to 3400Hz (Note 3)

1.0

Absolute Delay, 4-Wire to 2-Wire

300Hz to 3400Hz (Note 3)

1.0

Absolute Delay, 4-Wire to 4-Wire

300Hz to 3400Hz (Note 3)

0.95

Transhybrid Loss

= 1V

P-P

at 1kH (Note 3)

Total Harmonic Distortion
2-Wire/4-Wire, 4-Wire/2-Wire, 4-Wire/4-Wire

Reference Level 0dBm at 600

300Hz to 3400Hz (Note 3)

-50

Idle Channel Noise
2-Wire and 4-Wire

C-Message (Note 3)

dBrnC

Psophometric (Note 3)

-87

dBmp

PSRR, V

to 2-Wire

30Hz to 200Hz, R

= 600

(Note 3)

PSRR, V

to 4-Wire

PSRR, VBAT to 2-Wire

PSRR, VBAT to 4-Wire

PSRR, V

to 2-Wire

200Hz to 3.4kHz, R

= 600

(Note 3)

PSRR, V

to 4-Wire

PSRR, VBAT to 2-Wire

PSRR, VBAT to 4-Wire

PSRR, V

to 2-Wire

3.4kHz to 16kHz, R

= 600

(Note 3)

PSRR, V

to 4-Wire

PSRR, VBAT to 2-Wire

PSRR, VBAT to 4-Wire

DC PARAMETERS

Loop Current Programming Range

(Note 4)

Loop Current Programming Accuracy

-15

+15

Loop Current During Power Denial

= 200

BAT

= -48V

Fault Current, Tip to Ground

(Note 3)

Fault Current, Ring to Ground

100

Fault Current, Tip and Ring to Ground

(Note 3)

130

Switch Hook Detection Threshold

Ring Trip Comparator Voltage Threshold

-0.28

-0.24

-0.22

Thermal ALARM Output

Safe Operating Die Temperature Exceeded
(Note 3)

140

160

Dial Pulse Distortion

(Note 3)

0.1

0.5

Electrical Specifications

Unless Otherwise Specified, Typical Parameters are at T

= 25

C, Min-Max Parameters are over

Operating Temperature Range, V

BAT

= -24V, V

= +5V, AGND = BGND = 0V. All AC Parameters are specified

at 600

2-Wire terminating impedance. (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

HC55171B

UNCOMMITTED RELAY DRIVER

On Voltage, V

(RDO) = 30mA

0.2

0.5

Off Leakage Current

100

TTL/CMOS LOGIC INPUTS (F0, F1, RS, TST, RDI)

Logic Low Input Voltage

0.8

Logic High Input Voltage

2.0

5.5

Input Current

, 0V

-1

Input Current

, 0V

-100

LOGIC OUTPUTS (SHD, RTD, ALM)

Logic Low Output Voltage

LOAD

= 800

0.3

0.6

Logic High Output Voltage

LOAD

= 40

2.7

5.5

POWER DISSIPATION

Power Dissipation On Hook

= +5V, V

BAT

= -80V, R

LOOP

300

= +5V, V

BAT

= -48V, R

LOOP

150

Power Dissipation Off Hook

= +5V, V

BAT

= -24V, R

LOOP

= 600

= 25mA

280

= +5V, V

BAT

= -80V, R

LOOP

= +5V, V

BAT

= -48V, R

LOOP

= +5V, V

BAT

= -24V, R

LOOP

1.9

BAT

= +5V, V

- = -80V, R

LOOP

3.6

= +5V, V

- = -48V, R

LOOP

2.6

= +5V, V

- = -24V, R

LOOP

2.3

4.5

NOTES:

3. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon

initial design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and
specification compliance.

4. This parameter directly affects device junction temperature. Refer to Power Dissipation discussion of data sheet for design information.

Electrical Specifications

Unless Otherwise Specified, Typical Parameters are at T

= 25

C, Min-Max Parameters are over

Operating Temperature Range, V

BAT

= -24V, V

= +5V, AGND = BGND = 0V. All AC Parameters are specified

at 600

2-Wire terminating impedance. (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

HC55171B

The truth table for the internal logic of the HC55171B is
provided in the above table. This family of ringing SLICs can be
configured to support traditional unbalanced ringing and
through SLIC balanced ringing. The device operating states
used by through SLIC ringing applications are loop power
denial and normal feed. During loop power denial, the tip and
ring amplifiers are disabled (high impedance) and the DC volt-
age of each amplifier approaches ground. The SLIC will not
provide current to the subscriber loop during this mode and will
not detect loop closure. Voice transmission occurs during the
normal loop feed mode. During normal loop feed the SLIC is
completely operational and performs all transmission and
supervisory functions.

Power Dissipation

Careful thermal design is required to guarantee that the
maximum junction temperature of 150

C of the device is not

exceeded. The junction temperature of the SLIC can be
calculated using:

Where T

is maximum ambient temperature and

junction to air thermal resistance (and is package
dependent). The entire term in parentheses yields the SLIC
power dissipation. The power dissipation of the subscriber
loop does not contribute to device junction temperature and
is subtracted from the power dissipation term. Operating at
85

C, the maximum PLCC SLIC power dissipation is 1.18W.

Likewise, the maximum SOIC SLIC power dissipation is
0.92W.

OUT 1

R/20

R/2

TIP

90K

RING

4.5K

25K

100K

4.5K

90K

+2V

OP AMP

RING

RF2

BIAS

NETWORK

AGND

IIL LOGIC INTERF

TSD

RFC

ALM

RTD

SHD

TST

BAT

-IN 1

BGND

R = 108k

100K

90K

SENSE

SENSE 1

RING

SENSE 2

RDO

THERM

LTD

SHD

RTD

FAULT

DET

REF

VB/2

REF

LIMIT

RDI

RTI

HC55171B DEVICE TRUTH TABLE

STATE

Loop power Denial Active

Power Down Latch RESET, Power on
RESET

RD Active (unbalanced ringing)

Normal Loop feed

BAT

LOOP

(

)

LOOP

(

)

(

)

(EQ. 1)

HC55171B

Circuit Operation and Design Information

Through SLIC Ringing

The HC55171B uses linear amplification to produce the
ringing signal. As a result the ringing SLIC can produce sinu-
soid, trapezoid or square wave ringing signals. Regardless of
the wave shape, the ringing signal is balanced. The balanced
waveform is another way of saying that the tip and ring DC
potentials are the same during ringing.

Trapezoidal Ringing

The trapezoidal ringing waveform provides a larger RMS
voltage to the handset. Larger RMS voltages to the handset
provide more power for ringing and also increase the loop
length supported by the ringing SLIC.

One set of component values will satisfy the entire ringing
loop range of the SLIC. A single resistor sets the open circuit
RMS ringing voltage, which will set the crest factor of the
ringing waveform. The crest factor of the HC55171B ringing
waveform is independent of the ringing load (REN) and the
loop length. Another robust feature of the HC55171B ringing
SLIC is the ring trip detector circuit. The suggested values for
the ring trip detector circuit cover quite a large range of
applications.

The assumptions used to design the trapezoidal ringing
application circuit are listed below:

· Loop current limit set to 25mA.

· Impedance matching is set to 600

resistive.

· 2-wire surge protection is not required.

· System able to monitor RTD and SHD.

Logic ringing signal is used to drive RC trapezoid network.

Crest Factor Programming

As previously mentioned, a single resistor is required to set
the crest factor of the trapezoidal waveform. The only design
variable in determining the crest factor is the battery voltage.
The battery voltage limits the peak signal swing and
therefore directly determines the crest factor.

A set of tables will be provided to allow selection of the crest
factor setting resistor. The tables will include crest factors
below the Bellcore minimum of 1.2 since many ringing SLIC
applications are not constrained by Bellcore requirements.

The RMS voltage listed in the table is the open circuit RMS
voltage generated by the SLIC.

SLIC DESIGN EQUATIONS

FUNCTION

EQUATION

DEFINITION OF TERMS

2-Wire to 4-Wire Gain

OUT1

= SLIC 4-wire Output

= Voltage across 2-wire load

= 2-Wire Impedance

4-Wire To 2-wire Gain

= Voltage Across 2-Wire Load

= SLIC 4-Wire Input

= 2-Wire Impedance

SLIC

= SLIC Synthesized Impedance

4-Wire To 4-wire Gain

OUT1

= SLIC 4-Wire Output

= SLIC 4-Wire Input

= 2-Wire Impedance

SLIC

= SLIC Synthesized Impedance

Loop Current Limit Programming

LIMIT

= Programmed Loop Current Limit

IL1

= Programming Resistor

IL2

= Programming Resistor

Impedance Matching

= 2-Wire Impedance

K = 100

OUT1

-------------------

200

-----------

------------

SLIC

-----------------------------------

OUT1

-------------------

SLIC

-----------------------------------

200

------------

LIMIT

0.6

(

)

IL1

IL2

(

)

200xR

IL2

(

)

--------------------------------------------------

100

(

)

K 200 2

TABLE 1. CREST FACTOR PROGRAMMING RESISTOR FOR

BAT

= -80V

TRAP

RMS

TRAP

RMS

1.10

65.0

825

1.25

57.6

389

1.15

62.6

964

1.30

55.4

640

1.20

60.0

1095

1.35

53.3

TABLE 2. CREST FACTOR PROGRAMMING RESISTOR FOR

BAT

= -75V

TRAP

RMS

TRAP

RMS

1.10

60.9

1010

1.25

53.7

500

1.15

58.3

1190

1.30

51.6

791

1.20

55.9

1334

1.35

49.7

HC55171B

The voltages listed in the tables are driven from a logic
source that will not drive the ringing input negative. If the
ringing input is driven negative by 200mV, the peak-to-peak
ringing amplitudes can be increased.

Ringing Voltage Limiting Factors

As the load impedance decreases (increasing REN), the
source impedance of the SLIC during ringing slightly
attenuates the ringing signal.

If additional surge protection resistance must be used with
the trapezoidal circuit, the loop length performance of the
circuit will decrease proportionally to the added resistance
in the Tip and Ring leads. For example if 30

protection

resistors is used in each of the Tip and Ring leads, the
ringing loop length will decrease by a total of 60

Low Level Ringing Interface

The trapezoidal application circuit only requires a cadenced
logic signal applied to the wave shaping RC network to
achieve ringing. When not ringing, the logic signal should be
held low. When the logic signal is low, Tip will be near
ground and Ring will be near battery. When the logic signal
is high, Tip will be near battery and Ring will be near ground.

Loop Detector Interface

The RTD output should be monitored for off hook detection
during the ringing period. At all other times, the SHD should
be monitored for off hook detection. The application circuit
can be modified to redirect the ring trip information through
the SHD interface. The change can be made by rewiring the
application circuit, adding a pullup resistor to pin 23 and set-
ting F0 low for the entire duration of the ringing period. The
modifications to the application circuit for the single detector
interface are shown in Figure 1.

SLIC Operating State During Ringing

The SLIC control pin F1 should always be a logic high during
ringing. The control pin F0 will either be a constant logic high
(two detector interface) or a logic low (single detector

interface). Figure 2 shows the control interface for the dual
detector interface and the single detector interface.

Additional Application Information

Transhybrid Balance

Since the receive signal and its echo are 180 degrees out of
phase, the summing node of an operational amplifier can be
used to cancel the echo. Nearly all CODECs have an inter-
nal amplifier for echo cancellation. The circuit in Figure 3
shows the cancellation amplifier circuit.

TABLE 3. CREST FACTOR PROGRAMMING RESISTOR FOR

BAT

= -65V

TRAP

RMS

TRAP

RMS

1.10

52.5

1330

1.25

45.9

660

1.15

49.8

1600

1.30

44.1

1040

1.20

47.8

1800

1.35

42.5

TABLE 4. CREST FACTOR PROGRAMMING RESISTOR FOR

BAT

= -60V

TRAP

RMS

TRAP

RMS

1.10

48.2

1460

1.25

42.0

740

1.15

45.6

1760

1.30

40.4

1129

1.20

43.7

2030

1.35

38.8

HC55171B

RING

TRAP

RING

TRAP

RDO 21

RDI 20

NU 23

ADDITIONAL PULL UP RESISTOR

FIGURE 1. APPLICATION CIRCUIT WIRING FOR SINGLE

LOOP DETECTOR INTERFACE

FIGURE 2. DETECTOR LOGIC INTERFACES

RINGING

ACTIVE

RING

MODE

(LOGIC HI)

RTD

SHD

VALID DET

RINGING

ACTIVE

RING

MODE

(LOGIC HI)

SHD

VALID DET

(SINGLE DETECTOR INTERFACE)

(DUAL DETECTOR INTERFACE)

FIGURE 3. TRANSHYBRID AMPLIFIER CIRCUIT

OUT1

HC55171B

When the SLIC is matched to a 600

load and only the sense

resistors are used, the 4-wire to 4-wire gain is equal to 5/12 as
predicted by the design equations. Therefore, by configuring
the transhybrid amplifier with a gain of 2.4 in the echo path,
cancellation can be achieved. The following equations:

Substituting the fact that V

OUT1

is -5/12 of V

Since cancellation implies that under these conditions, the
output V

should be zero, set Equation 2 equal to zero and

solve for R

Another outcome of the transhybrid gain selection is the
2-wire to 4-wire gain of the SLIC as seen by the CODEC.
The 5/12 voltage gain in the transmit path is relevant to the
receive input as well as any signals from the 2-wire side.
Therefore by setting the V

OUT1

gain to 2.4 in the previous

analysis, the 2-wire to 4-wire gain was set to unity.

Single Supply CODEC Interface

The majority of CODECs that interface to the ringing SLIC
operate from a single +5V supply and ground. Figure 4
shows the circuitry required to properly interface the ringing
SLIC to the single supply CODEC.

The CODEC signal names may vary from different
manufacturers, but the function provided will be the same.
The DC reference from the CODEC is used to bias the ana-
log signals between +5V and ground. The capacitors are
required so that the DC gain is unity for proper biasing from
the CODEC reference. Also, the capacitors block DC signals
that may interfere with SLIC or CODEC operation.

Layout Guidelines and Considerations

The printed circuit board trace length to all high impedance
nodes should be kept as short as possible. Minimizing length
will reduce the risk of noise or other unwanted signal pickup.
The short lead length also applies to all high gain inputs. The
set of circuit nodes that can be categorized as such are:

· V

pin 27, the 4-wire voice input (low gain input).

· -IN1 pin 13, the inverting input of the internal amplifier.

· V

REF

pin 3, the noninverting input to ring feed amplifier.

· V

RING

pin 24, the 20V/V input for the ringing signal.

For multi layer boards, the traces connected to tip should not
cross the traces connected to ring. Since they will be carry-
ing high voltages, and could be subject to lightning or surge
depending on the application, using a larger than minimum
trace width is advised.

The 4-wire transmit and receive signal paths should not
cross. The receive path is any trace associated with the V

input and the transmit path is any trace associated with V

output. The physical distance between the two signal paths
should be maximized to reduce crosstalk, or separated by a
ground trace.

The operating mode control signals and detector outputs
should be routed away from the analog circuitry. Though
the digital signals are nearly static, care should be taken to
minimize coupling of the sharp digital edges to the analog
signals.

The part has two ground pins, one is labeled AGND and the
other BGND. Both pins should be connected together as
close as possible to the SLIC. If a ground plane is available,
then both AGND and BGND should be connected directly to
the ground plane.

A ground plane that provides a low impedance return path
for the supply currents should be used. A ground plane
provides isolation between analog and digital signals. If the
layout density does not accommodate a ground plane, a
single point grounding scheme should be used.

--------

OUT1

--------

(EQ. 2)

--------

------

--------

(EQ. 3)

2.4

--------

(EQ. 4)

FIGURE 4. SINGLE SUPPLY CODEC INTERFACE

HC5517B

CODEC

+2.5V

OUT1

RX OUT

TX IN

HC55171B

Pin Descriptions

PLCC

SYMBOL

DESCRIPTION

AGND

Analog Ground - Serves as a reference for the transmit output and receive input terminals.

Positive Voltage Source - Most Positive Supply.

REF

An external voltage connected to this pin will override the internal V

BAT

/2 reference.

Power Denial - An active low TTL compatible logic control input. When enabled, the output of the ring amplifier
will ramp close to the output voltage of the tip amplifier.

TTL compatible logic control input that must be tied high for proper SLIC operation.

SHD

Switch Hook Detection - An active low TTL compatible logic output. Indicates an off-hook condition.

RTD

Ring Trip Detection - An active low TTL compatible logic output. Indicates an off-hook condition when the
phone is ringing.

TST

A TTL logic input. A low on this pin will keep the SLIC in a power down mode. The TST pin in conjunction with
the ALM pin can provide thermal shutdown protection for the SLIC. Thermal shutdown is implemented by a
system controller that monitors the ALM pin. When the ALM pin is active (low) the system controller issues a
command to the TST pin (low) to power down the SLIC. The timing of the thermal recovery is controlled by
the system controller.

ALM

A TTL compatible active low output which responds to the thermal detector circuit when a safe operating die
temperature has been exceeded.

LMT

Loop Current Limit - Voltage on this pin sets the short loop current limiting conditions.

OUT1

The analog output of the spare operational amplifier.

-IN1

The inverting analog input of the spare operational amplifier. The non-inverting input is internally connected

to AGND.

TIP SENSE

An analog input connected to the TIP (more positive) side of the subscriber loop through a feed resistor.
Functions with the RING terminal to receive voice signals and for loop monitoring purpose.

RING SENSE 1

An analog input connected to the RING (more negative) side of the subscriber loop through a feed resistor.

Functions with the TIP terminal to receive voice signals and for loop monitoring purposes.

RING SENSE 2

This is an internal sense mode that must be tied to RING SENSE 1 for proper SLIC operation.

Receive Input, 4-Wire Side - A high impedance analog input. AC signals appearing at this input drive the Tip
Feed and Ring Feed amplifiers deferentially.

Not used in this application. This pin should be left floating.

Transmit Output, 4-Wire Side - A low impedance analog output which represents the differential voltage across
TIP and RING. Since the DC level of this output varies with loop current, capacitive coupling to the next stage
is necessary.

RDI

TTL compatible input to drive the uncommitted relay driver.

RDO

This is the output of the uncommitted relay driver.

BGND

Battery Ground - All loop current and some quiescent current flows into this terminal.

Not used in this application. This pin should be either grounded or left floating.

RING

Ring signal input.

This is the output of the tip amplifier.

This is the output of the ring amplifier.

BAT

The negative battery source.

RTI

Ring Trip Input - This pin is connected to the external negative peak detector output for ring trip detection.

HC55171B

Trapezoidal Ringing Application Circuit

Pinouts

HC55171B (PLCC)

TOP VIEW

HC55171B (SOIC)

TOP VIEW

RING

RING SENSE 2

RING SENSE 1

BGND

RDO

RDI

GND

LIMIT

OUT 1

-IN 1

TIP SENSE

REF

SHD

RTD

TST

ALM

AGND

REF

SHD

RTD

TST

ALM

LIMIT

OUT 1

-IN 1

TIP SENSE

RTI

RING

RDO

RING SENSE 2

RING SENSE 1

BAT

BGND

RDI

TIP

LIMIT

TIP SENSE

IL1

HC55171B

REF

RING

SHD

RTD

ALM

TST

RT3

RT2

-IN1

OUT1

RING

RTI

BAT

BGND

AGND

RING SENSE 1

RING SENSE 2

PS1

PS2

TRAP

IL2

V-REC

FIGURE 5. TRAPEZOIDAL RINGING APPLICATION CIRCUIT

RT1

V-XMIT

RING

BAT

SHD

RTD

ALM

TST

RDI

TRAP

HC55171B

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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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HC5517B Trapezoidal Ringing Application Circuit Parts List

COMPONENT

VALUE

TOLERANCE

RATING

COMPONENT

VALUE

TOLERANCE

RATING

U1 - Ringing SLIC

HC55171B

N/A

IL2

7.68k

, R

49.9

TRAP

User-Defined

, R

IL1

56.2k

PS1

, C

PS2

0.1

10%

100V

RT1

49.9k

, C

0.47

10%

50V

RT2

1.5M

TRAP

4.7

10%

10V

RT3

51.1k

, D

TRAP

1N914

Generic Rectifier Diode

45.3k

HC55171B

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