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Электронный компонент: HFA3761

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4-1
TM
HFA3761
400MHz AGC and Quadrature IF
Demodulator
The HFA3761 is a highly integrated
baseband converter for quadrature
demodulation applications. The
HFA3761 400MHz AGC and
quadrature IF demodulator is one of the
seven chips in the PRISM full duplex chip set (see Typical
Application Diagram). It features all the necessary blocks for
baseband demodulation of I and Q signals. It has a two
stage integrated AGC IF amplifier with 82dB of voltage gain
and 76dB of gain control range. Baseband antialiasing and
shaping filters are integrated in the design. Four filter
bandwidths are programmable via a two bit digital control
interface. In addition, these filters are continuously tunable
over a
20% frequency range via one external resistor. To
achieve broadband operation, the Local Oscillator
frequency input is required to be twice the desired
frequency of demodulation. A selectable buffered divide by
2 LO output and a stable reference voltage are provided for
convenience of the user. The device is housed in a thin 80
lead TQFP package well suited for PCMCIA board
applications.
Features
Integrates all IF and AGC Receive Functions
Broad Frequency Range . . . . . . . . . . 10MHz to 400MHz
I/Q Amplitude and Phase Balance . . . . 0.2dB, 2 Degrees
5th Order Programmable
Low Pass Filter . . . . . . . . . . . . . . . . . 2.2MHz to 17.6MHz
400MHz AGC Gain Strip . . . . . . . . . . . . . . . . . . . . . 82dB
AGC Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75dB
Low LO Drive Level . . . . . . . . . . . . . . . . . . . . . . . -15dBm
Fast AGC Switching . . . . . . . . . . . . . . . . . . . . . . . . . . 1
s
Power Management/Standby Mode
Single Supply 2.7V to 5.5V Operation
Applications
Wireless Local Loop
Wireless Local Area Networks
PCMCIA Wireless Transceivers
ISM Systems
CDMA Radios
PCS/Wireless PBX
Simplified Block Diagram
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
HFA3761IN
-40 to 85
80 Ld TQFP
Q80.14x14
0
o
/90
o
AGC1_IN
DEMOD_LO_IN
A
GC1_OUT
A
GC2_IN
LPF_RXQ _OUT
DEMOD_LO_OUT
A
GC2_OUT
LPF_TUNE_1
LPF_RX_I
LPF_RX_Q
DEMOD_RX_I
DEMOD_RX_Q
DEMOD_IF_IN
2
LPF_SEL0
LPF_SEL1
2V
REF
2V REF
LPF_TUNE_0
LPF_RXI_OUT
LO_GND
AGC1_V
AGC
AGC2_V
AGC
AGC_SEL
I
Q
Data Sheet
July 1999
File Number
4236.4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright
Intersil Corporation 2000
PRISM is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.
4-2
Pinout
80 LEAD TQFP
TOP VIEW
Typical Full Duplex Application Diagram
For additional information on the PRISM Full Duplex Radio
Chip Set, call (321) 724-7800 to access Intersil' AnswerFAX
system. When prompted, key in the four-digit document
number (File #) of the data sheets you wish to receive.
The four-digit file numbers are shown in Typical Application
Diagram, and correspond to the appropriate circuit.
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LPF_RX_PE
GND
NC
LPF_RXI+
GND
DEMOD_RXI-
GND
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
GND
GND
LO_GND
DEMOD_IFIN-
DEMOD_IFIN+
DEMOD_V
CC
LO_OUT
DEMOD_V
CC
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
AGC2_OUT+
AGC2_OUT-
AGC2_V
CC
AGC2_PE
GND
GND
GND
GND
GND
GND
GND
63 62 61
37 38 39 40
NC
NC
NC
NC
LO_IN
DEMOD_RX_PE
DEMOD_V
CC
GND
44
43
42
41
17
18
19
20
80
NC
NC
NC
LPF_RXQ-
LPF_RXQ+
LPF_RXI-
DEMOD_RXI+
DEMOD_RXQ+
DEMOD_RXQ-
A
GC2_BYP+
A
GC2_IN+
A
GC2_IN-
AGC2_V
AGC
A
GC2_BYP-
GND
GND
LPF_V
CC
2V REF
NC
NC
LPF_RXI_OUT
LPF_RXQ_OUT
LPF_SEL1
LPF_SEL0
LPF_TUNE1
LPF_TUNE0
GND
LPF_BYP
GND
GND
GND
AGC2_V
CC
A
GC1_OUT+
A
GC1_OUT
-
A
GC1_V
CC
A
GC1_PE
AGC1_BYP+
AGC1_IN+
AGC1_IN-
A
GC1_V
AG
C
AGC1_BYP-
GND
GND
AGC_SEL
A
GC1_V
CC
GND
SYNTHESIZER
LNA
BPF
RF/IF
CONVERTER
IF AGC
LPF
QMODEM
IF/RF
CONVERTER
BASEBAND
FILTER
SYNTHESIZER
HFA3424/21
HFA3661
HFA3524
HFA3663 (File #4241)
HFA3925
HFA3761 (File #4236)
HFA3763
LPF
AGC
LPF
QMODEM
LPF
D/A
PA
BPF
HFA3664 (File #4242)
(File #4240)
(File #4062)
HFA3524
(File #4062)
(File #4132)
(File #4131)
(File #4237)
PRISM FULL DUPLEX RADIO
CHIP SET, FILE #4238
A/D
PRISM FULL DUPLEX CHIP SET
AGC
LNA
IF LO1
IF LO2
RF LO1
RF LO2
D
U
P
L
E
X
E
R
OPTIONAL WHEN IN
ANALOG MODE
HFA3761
4-3
Block Diagram
NOTE: V
CC
, GND and Bypass capacitors not shown.
0
o
/9
0
o
IF
A
GC1_IN+
A
GC1_IN-
DEMOD_LO_IN
AGC1_OUT +
AGC1_OUT -
AGC2_IN-
AGC2_IN+
LPF_RXI_OUT
DEMOD_LO_OUT
AGC2_OUT +
AGC2_OUT -
LPF_TUNE1
LPF_RX I +
LPF_RX I -
LPF_RX Q +
LPF_RX Q -
DEMOD_RX I +
DEMOD_RX I -
DEMOD_RX Q +
DEMOD_RX Q -
DEMOD_IF_IN +
DEMOD_IF_IN -
2
LPF_SEL0
LPF_SEL1
2V REF
LPF_TUNE0
LPF_RXQ_OUT
SA
W
50
DO
WN CONV
LO_GND
AGC1_PE
AGC2_PE
DEMOD_RX PE
LPF_RX PE
IF
IN
(2XLO)
IF
A
GC1_V
AG
C
A
GC2_V
AG
C
A
GC CTRL
A
GC_SEL
OPTIONAL FILTER
HFA3761
4-4
Pin Descriptions
PIN
SYMBOL
DESCRIPTION
1
AGC1_BYP+
DC feedback pin for AGC amplifier 1. Requires good decoupling and minimum wire length to a solid signal ground.
2
AGC1_In+
Non-inverting analog input of AGC amplifier 1.
3
GND
Ground. Connect to a solid ground plane.
4
AGC_Sel
This pin selects either differential or single ended input configuration for the first stage AGC. Ground this pin for
differential input configuration. Leave it floating for single ended input configuration.
5,
AGC1_In-
Inverting analog input of AGC amplifier 1.
6,
AGC1_BYP-
DC feedback pin for AGC amplifier 1. Requires good decoupling and minimum wire length to a solid signal ground.
7, 8
GND
Ground. Connect to a solid ground plane.
9
LPF_V
CC
Supply pin for the Low pass filter. Use high quality decoupling capacitors right at the pin.
10
2V REF
Stable 2V reference voltage output for external applications. Loading must be higher than 10k
. A bypass
capacitor of at least 0.1
F is required.
11
LPF_BYP
Internal reference bypass pin. This is the common voltage (V
CM
) used for the LPF digital thresholds. Requires
0.1
F decoupling capacitor.
12
NC
Connected internally for test purposes. Pin must be left floating.
13
NC
Connected internally for test purposes. Pin must be left floating.
14
LPF_RXI_Out
Low pass filter in phase (I) channel receive output. Requires AC coupling.
15
LPF_RXQ_Out
Low pass filter quadrature (Q) channel receive output. Requires AC coupling.
16
LPF_Sel1
Digital control input pins. Selects four programed cut off frequencies for the receive channel. Tuning speed from
one cutoff to another is less than 1
s.
SEL1
SEL0
CUTOFF FREQUENCY
SEL1
SEL0
CUTOFF FREQUENCY
LO
LO
2.2MHz
HI
LO
8.8MHz
LO
HI
4.4MHz
HI
HI
17.6MHz
17
LPF_Sel0
18
LPF_Tune1
These two pins are used to fine tune the Low pass filter cutoff frequency. A resistor connected between the two
pins (R
TUNE
) will fine tune both transmit and receive filters. Refer to the tuning equation in the LPF AC
specifications.
19
LPF_Tune0
20
GND
Ground. Connect to a solid ground plane.
21
LPF_RX_PE
Digital input control pin to enable the LPF receive mode of operation. Enable logic level is High.
22
GND
Ground. Connect to a solid ground plane.
23
NC
Connected internally for test purposes. Pin must be left floating.
24
NC
Connected internally for test purposes. Pin must be left floating.
25
NC
Connected internally for test purposes. Pin must be left floating.
26
NC
Connected internally for test purposes. Pin must be left floating.
27
LPF_RXQ-
Low pass filter inverting input of the receive quadrature channel. AC coupling is required. This input is normally
coupled to the negative output of the quadrature demodulator (Mod_RXQ-), pin 36.
28
LPF_RXQ+
Low pass filter non inverting input of the receive quadrature channel. AC coupling is required. This input is
normally coupled to the positive output of the quadrature demodulator (Mod_RXQ+), pin 35.
29
LPF_RXI-
Low pass filter inverting input of the receive in phase channel. AC coupling is required. This input is normally
coupled to the negative output of the in phase demodulator (Mod_RXI-), pin 34.
30
LPF_RXI+
Low pass filter non inverting input of the receive in phase channel. AC coupling is required. This input is normally
coupled to the positive output of the in phase demodulator (DEMOD_RXI-), pin 33.
31, 32
GND
Ground. Connect to a solid ground plane.
33
DEMOD_RXI+
In phase demodulator positive output. AC coupling is required. Normally connects to the non inverting input of the
Low pass filter (LPF_RXI+), pin 30.
34
DEMOD_RXI-
In phase demodulator negative output. AC coupling is required. Normally connects to the inverting input of the
Low pass filter (LPF_RXI-), pin 29.
HFA3761
4-5
35
DEMOD_RXQ+
Quadrature demodulator positive output. AC coupling is required. Normally connects to the non inverting input of
the Low pass filter (LPF_RXQ+), pin 28.
36
DEMOD_RXQ-
Quadrature demodulator negative output. AC coupling is required. Normally connects to the inverting input of the
Low pass filter (LPF_RXQ+), pin 27.
37
NC
Connected internally for test purposes. Pin must be left floating.
38
NC
Connected internally for test purposes. Pin must be left floating.
39
NC
Connected internally for test purposes. Pin must be left floating.
40
NC
Connected internally for test purposes. Pin must be left floating.
41
GND
Ground. Connect to a solid ground plane.
42
DEMOD_V
CC
Supply pin for the Demodulator. Use high quality decoupling capacitors right at the pin.
43
DEM_RX_PE
Digital input control to enable the demodulator section. Enable logic level is High.
44
DEM_LO_In
(2XLO)
Single ended local oscillator current input. Frequency of input signal must be twice the required demodulator LO
frequency. Input current is optimum at 200
A
RMS
. Input matching networks and filters can be designed for a wide
range of power and impedances at this port. Typical input impedance is 130
.
This pin requires AC coupling.
NOTE: High second harmonic content input waveforms may degrade I/Q phase accuracy.
45
DEMOD_V
CC
Supply pin for the Demodulator. Use high quality decoupling capacitors right at the pin.
46
DEM_LO_Out
Divide by 2 buffered output reference from "DEMOD_LO_in" input. Used for external applications where the
demodulating carrier reference frequency is required. 50
single end driving capability. This output can be
disabled by use of pin 50. AC coupling is required.
47
DEMOD_V
CC
Supply pin for the Demodulator. Use high quality decoupling capacitors right at the pin.
48
DEMOD_IFIN+
Demodulator, non-inverting input. Requires AC coupling.
49
DEMOD_IFIN-
Demodulator, inverting input. Requires AC coupling.
50
LO_GND
When grounded, this pin enables the LO buffer (DEMOD_LO_Out). When open (NC) it disables the LO buffer.
51, 52, 53
GND
Ground. Connect to a solid ground plane.
54
AGC2_V
CC
Supply pin for the AGC amplifier 2. Use high quality decoupling capacitors right at the pin.
55
AGC2_Out-
Positive output of AGC amplifier 2. Requires AC coupling.
56
AGC2_Out+
Negative output of AGC amplifier 2. Requires AC coupling.
57
AGC2_PE
Digital input control to enable the AGC amplifier 2. Enable logic level is High.
58
AGC2_V
CC
Supply pin for the AGC amplifier 2. Use high quality decoupling capacitors right at the pin.
59
GND
Ground. Connect to a solid ground plane.
60
AGC2_V
AGC
AGC amplifier 2, AGC control input.
61
AGC2_BYP+
DC feedback pin for AGC amplifier 2. Requires good decoupling and minimum wire length to a solid signal ground.
62
AGC2_In+
Non-inverting analog input of AGC amplifier 2.
63
GND
Ground. Connect to a solid ground plane.
64
AGC2_In-
Inverting input of AGC amplifier 2.
65
AGC2_BYP-
DC feedback pin for AGC amplifier 2. Requires good decoupling and minimum wire length to a solid signal ground.
66 - 73
GND
Ground. Connect to a solid ground plane.
74
AGC1_V
CC
AGC amplifier 1 supply pin. Use high quality decoupling capacitors right at the pin.
75
AGC1_Out-
Negative output of AGC amplifier 1. Requires AC coupling.
76
AGC1_Out+
Positive output of AGC amplifier 1. Requires AC coupling.
77
AGC1_PE
Digital input control to enable the AGC amplifier 1. Enable logic level is High.
78
AGC1_V
CC
AGC amplifier 1 supply pin. Use high quality decoupling capacitors right at the pin.
79
GND
Ground. Connect to a solid ground plane.
80
AGC1_V
AGC
AGC amplifier 1, AGC control input.
Pin Descriptions
(Continued)
PIN
SYMBOL
DESCRIPTION
HFA3761