File Number

4661.2

Microsoft® and Windows® are registered trademarks of Microsoft Corporation.

1-888-INTERSIL or 321-724-7143

Intersil and Design is a trademark of Intersil Corporation.

Intersil Corporation 2000

PRISM® is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.

P R E L I M I N A R Y

HFA3841

Wireless LAN Medium Access Controller

The Intersil HFA3841 Wireless LAN
Medium Access Controller is part of the
PRISM® Enterprise 2.4GHz WLAN
chip set. The HFA3841 directly
interfaces with the Intersil HFA386x

family of Baseband Processors, offering a complete end-to-
end chip set solution for wireless LAN products. Protocol and
PHY support are implemented in firmware to allow custom
protocol and different PHY transceivers.

The HFA3841 is designed to provide maximum performance
with minimum power consumption. External pin layout is
organized to provide optimal PC board layout to all user
interfaces.

Firmware implements the full IEEE 802.11 Wireless LAN
MAC protocol. It supports BSS and IBSS operation under
DCF, and operation under the optional Point Coordination
Function (PCF). Low level protocol functions such as
RTS/CTS generation and acknowledgement, fragmentation
and de-fragmentation, and automatic beacon monitoring are
handed without host intervention. Active scanning is
performed autonomously once initiated by host command.
Host interface command and status handshakes allow
concurrent operations from multi-threaded I/O drivers.
Additional firmware functions specific to access point
applications are also available.

Designing wireless protocol systems using the HFA3841 is
made easier with the availability of evaluation board,
firmware, software device drivers, and complete
documentation.

Features

· IEEE802.11 Standard Data Rates: 1, 2, 5.5 and 11Mbps

· Part of the Intersil PRISM Wireless LAN Chip Set

· Full Implementation of the MAC Protocol Specified in

IEEE Std. 802.11-1999 and the 802.11b Draft Standard

· Host Interface Supports Full 16-Bit Implementation of PC

Card 95, also ISA PnP with Additional Chip

· Host Interface Provides Dual Buffer Access Paths

· External Memory Interface Supports up to 4M bytes RAM

· Internal Encryption Engine Executes IEEE802.11 WEP

· Low Power Operation; 25mA Active, 8mA Doze, <1mA Sleep

· Operation at 2.7V to 3.6V Supply

· 3V to 5V Tolerant Input/Outputs

· 128 Pin LQFP Package Targeted for Type II PC Cards

· IEEE802.11 Wireless LAN MAC Protocol Firmware and

Microsoft® Windows® Software Drivers

Applications

· High Data Rate Wireless LAN

· PC Card Wireless LAN Adapters

· ISA, ISA PnP WLAN Cards

· PCI Wireless LAN Cards (Using Ext. Bridge Chip)

· Wireless LAN Modules

· Wireless LAN Access Points

· Wireless Bridge Products

· Wireless Point-to-Multipoint Systems

Ordering Information

PART

NUMBER

TEMP. RANGE

(

PACKAGE

PKG. NO.

HFA3841CN

0 to 70

128 Ld LQFP

Q128.14x20

HFA3841CN96

0 to 70

Tape and Reel

Data Sheet

January 2000

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Pinout

Simplified Block Diagram

103

MA8

MA7

MA6

MA5

MA3

MA2

MA4

MA9

MA17

MA16

MA15

MA14

MA12

MA11

MA10

_IO3

MA13

MA18

HD8

HD9

HD10

PL7

MOE-

RAMCS-

NVCS-

_IO3

PJ4

_IO3

MWEL-

MA1

MA0

PJ2

PJ1

PJ3

PK7

PK6

_CORE3

PL2

PL1

PL3

PJ0

PL0

_CORE3

PL5

TCLKIN

RESET

TXD

TXC

RXD

RXC

PJ7

HD6

HD7

HCE1-

HD5

HD4

HD3

PJ6

PJ5

PL6

_IO3

HD2

HD1

HD0

HREG-

PK5

INDEX

PK2

PK1

PK0

HSTSCHG-

_CORE3

CLK

OUT

_CORE3

XTALI

XTALO

_IO3

PL4

MD15

MD14

MD13

MD12

MD11

MD10

MD9

MD8

_IO3

_CORE3

MD7

MD6

MD5

MD4

MD3

MD2

MD1

MD0

TRST-

PK3

PK4

100

101

102

104
105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127
128

HINPACK-

HWAIT-

HA0

HA1

HA2

HA3

HA4

HA5

HA6

HA7

HIREQ-

_IO3

HWE-

HA8

HA9

HIOWR-

HIORD-

HOE-

HCE2-

HD15

_IO3

HD14

HD13

HD12

HD11

_IO5

PRISM RADIO

BASEBAND

PROCESSOR

TXD/RXD

CTRL/STATUS

SERIAL CONTROL

PHY

INTERFACE

(MDI)

SERIAL

CONTROL

(MMI)

PRISM RADIO

RF SECTION

RADIO AND SYNTH

SERIAL CONTROL

MICRO-

PROGRAMMED

MAC ENGINE

MEMORY

CONTROLLER

WEP

ENGINE

PC CARD

HOST

INTERFACE

ON-CHIP

MEMORY

44MHz CLOCK

SOURCE

ADDRESS

SELECT

EXTERNAL
SRAM AND

FLASH

MEMORY

HOST

COMPUTER

DATA

ADDRESS

CONTROL

HFA3841

Preliminary - HFA3841

HFA3841 Pin Descriptions

Host Interface Pins

PIN NAME

PIN NUMBER

PIN I/O TYPE

DESCRIPTION

HA0-9

106-113, 117, 118 5V tol, CMOS, Input, 50K Pull Down

PC Card address input, bits 0 to 9

HCE1-

5V tol, CMOS, Input, 50K Pull Up

PC Card card select, low byte

HCE2-

122

5V tol, CMOS, Input, 50K Pull Up

PC Card card select, high byte

HD0-15

101-99, 6-2,

96-94, 128-125,

123

5V tol, BiDir, 2mA, 50K Pull Down

PC Card data bus, bit 0 to 15

HINPACK-

103

CMOS Output, 2mA

PC Card I/O decode confirmation

HIORD-

120

5V tol, CMOS, Input, 50K Pull Up

PC Card I/O space read

HIOWR-

119

5V tol, CMOS, Input, 50K Pull Up

PC Card I/O space write

HRDY/HIREQ-

114

CMOS Output, 4mA

PC Card interrupt request (I/O mode) Card ready
(memory mode)

HOE-

121

5V tol, CMOS, Input, 50K Pull Up

PC Card memory attribute space output enable

HREG-

102

5V tol, CMOS, Input, 50K Pull Up

PC Card attribute space select

HRESET

5V tol, CMOS, ST Input, 50K Pull Up Hardware Re-
set

HSTSCHG-

CMOS Output, 4mA

PC Card status change

HWAIT-

104

CMOS Output, 4mA

PC Card not ready (force host wait state)

HWE-

116

5V tol, CMOS Input, 50K Pull Up

PC Card memory attribute space write enable

Memory Interface Pins

PIN NAME

PIN NUMBER

PIN I/O TYPE

DESCRIPTION

MA0 MWEH-

CMOS TS Output, 2mA

MBUS address bit 0 (byte) for x8 memory High byte
write enable for x16 memory

MA1-18

73-81, 84-92

CMOS TS Output, 2mA

MBUS address bits 1 to 18

PL4

CMOS BiDir, 2mA

MBUS address bit 19

PL5

CMOS BiDir, 2mA, 50K Pull Up

MBUS address bit 20

PL6

CMOS BiDir, 2mA

MBUS address bit 21

MOE-

CMOS TS Output, 2mA

Memory output enable

MWEL-

CMOS TS Output, 2mA

Low (or only) byte memory write enable

RAMCS-

CMOS TS Output, 2mA

RAM select

NVCS-

CMOS TS Output, 2mA

NV memory select

MD0-7

61-54

5V tol, CMOS, BiDir, 2mA, 100K Pull Up

MBUS low data byte, bits 0 to 7

MD8-15

51-44

5V tol, CMOS, BiDir, 2mA 50K Pull Down

MBUS high data byte, bits 8 to 15

Preliminary - HFA3841

Radio Interface and General Purpose Port Pins

PIN NAME

PIN NUMBER

PIN I/O TYPE

DESCRIPTION OF FUNCTION

(IF OTHER THAN IO PORT)

TXD

CMOS Output, 2mA, 50K Pull Down

Transmit data out

TXC

5V tol, CMOS, BiDir 2mA, ST

Transmit clock in/out

RXD

CMOS Input

Receive data in

RXC

CMOS Input, ST

Receive clock in

PJ0

CMOS BiDir, 2mA, ST, 50K Pull Down

MMI serial clock in/out

PJ1

CMOS BiDir, 2mA, 50K Pull Down

MMI serial data in/out

PJ2

CMOS BiDir, 2mA, 50K Pull Down

MMI serial data read/write control, or data output

PJ3

CMOS BiDir, 2mA

MMI device enable

PJ4

CMOS BiDir, 2mA

PJ5

CMOS BiDir, 2mA, 50K Pull Up

PJ6

CMOS BiDir, 2mA

PJ7

CMOS BiDir, 2mA, 50K Pull Up

PK0

CMOS BiDir, 2mA, ST, 50K Pull Down

PK1

CMOS BiDir, 2mA, 50K Pull Down

PK2

CMOS BiDir, 2mA, 50K Pull Down

PK3

CMOS BiDir, 2mA

PK4

CMOS BiDir, 2mA

PK5

CMOS BiDir, 2mA

MDREADY - PHY or MAC data available (in)

PK6

CMOS BiDir, 2mA

Medium busy (CCA from PHY)

PK7

CMOS BiDir, 2mA

PL0

CMOS BiDir, 2mA

Transmitter enable

PL1

CMOS BiDir, 2mA

Receiver enable (or PHY sleep control)

PL2

CMOS BiDir, 2mA

PL3

CMOS BiDir, 2mA

PL4

CMOS BiDir, 2mA

MBUS address bit 19

PL5

CMOS BiDir, 2mA, 50K Pull Up MBUS address bit
20

PL6

CMOS BiDir, 2mA

MBUS address bit 21 or PHY control I/O

PL7

CMOS BiDir, 2mA

Transmitter ready

Clocks

PIN NAME

PIN NUMBER

PIN I/O TYPE

DESCRIPTION

XTALI

CMOS Input, ST

Crystal or external clock input (at >= 2X desired
MCLK frequency)

XTALO

CMOS Output, 2mA

Crystal output

CLKOUT

CMOS, TS Output, 2mA

Clock output (selectable as OSC or MCLK)

TCLKIN

CMOS Input, ST, 50K Pull Down

Timebase Reference Clock Input

Preliminary - HFA3841

Power

PIN NAME

PIN NUMBER

PIN I/O TYPE

DESCRIPTION

VCC_CORE3

14, 25, 39, 53

3.3V Core Supply

VCC_IO3

66, 83, 98. 124

3.3V I/O Supply

VCC_IO5

105

5V Tolerance Supply

VSS_CORE3

13, 24, 37

Core V

VSS_IO3

42, 52, 67, 82, 97, 115

I/O V

TRST-

CMOS Input

Reserved - Must be tied low through 1K

ST = Schmitt Trigger (Hysteresis), TS = Three-State. Signals ending with "-" are active low.

NOTE: Output pins typically drive to positive voltage rail less 0.1V. Hence with a supply of 2.7V the output will just meet 5V TTL signal levels at
rated loads.

Port Pin Uses for PRISM Application

PIN

NAME

PRISM I USE

PRISM IITM USE

RXC

RXC - Receive clock

RXD

RXD - Receive data

TXC

TXC - Transmit clock

TXD

TXD - Transmit data

PJ0

SCLK - Clock for the SD serial bus.

PJ1

SD - Serial bi-directional data bus

PJ2

R/W - An input to the HFA3860A used to change
the direction of the SD bus when reading or writing
data on the SD bus.

Not Used

PJ3

CS - A Chip select for the device to activate the se-
rial control port. (active low)

CS_BAR - Chip select for HFA3861 baseband
(active low)

PJ4

Not Used

PE1 - Power Enable 1

PJ5

SYNTH_LE - Latches a frame of 22 bits after it has
been shifted by the SCLK into the synthesizer reg-
isters.

LE_IF - Load enable for HFA3783 Quad IF

PJ6

LED - Activity indicator

PJ7

Not Used

RADIO_PE - RF power enable

PK0

Not Used

LE_RF - Load enable for HFA3983 RF chip

PK1

Not Used

SYNTHCLK - Serial clock to front end chips

PK2

Not Used

SYNTHDATA - Serial data to front end chips

PK3

TX_PE_RF - Power Enable

PA_PE - Transmit PA power enable

PK4

RX_PE_RF - Power Enable

PE2 - Power Enable 2

PK5

MD_RDY - Header data and data packet are ready
to be transferred from Baseband on RXD

MDREADY - Header data and data packet are
ready to be transferred from Baseband on RXD

PK6

CCA - Signal that the channel is clear to transmit.

PK7

RADIO_PE - Master power control for the RF
section

CAL_EN - Calibration mode enable

PL0

TX_PE and PA_PE - Transmit Enable to Baseband TX_PE - Transmit Enable to Baseband

PL1

RX_PE - Receive Enable to Baseband

PL2

RESET - Reset to Baseband

RESET_BB - Reset Baseband

PL3

Not Used

T/R-SW_BAR - Transient/Receive Control (Inverted)

PL4

MA19 (if required)

PL5

MA20 (if required)

PL6

MA21 (if required)

Reserved

PL7

TX_RDY - Baseband ready to receive data on TXD
(not used by firmware)

T/R_SW - Transmit/Receive Control

Preliminary - HFA3841

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