File Number

8020

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil and Design is a trademark of Intersil Americas Inc.

P RE L I M I N A RY

HFA3842B

PCMCIA/USB Wireless LAN Medium
Access Controller

The Intersil HFA3842B Wireless LAN
Medium Access Controller is part of
the PRISM® 2.4GHz radio chip set.
The HFA3842B directly interfaces

with the Intersil HFA386x family of Baseband Processors,
offering a complete end-to-end chip set solution for wireless
LAN products. Protocol and PHY support are implemented in
firmware to allow custom protocol and different PHY
transceivers.

The HFA3842B is designed to provide maximum
performance with minimum power consumption. Package
pin layout provides optimal PC board layout to all user
interfaces including PCMCIA and USB.

Firmware implements the full IEEE 802.11 Wireless LAN
MAC protocol. It supports BSS and IBSS operation under
DCF, and operation under the optional Point Coordination
Function (PCF). Low level protocol functions such as
RTS/CTS generation and acknowledgement, fragmentation
and de-fragmentation, and automatic beacon monitoring are
handed without host intervention. Active scanning is
performed autonomously once initiated by host command.
Host interface command and status handshakes allow
concurrent operations from multi-threaded I/O drivers.
Additional firmware functions specific to access point
applications are also available.

Designing wireless protocol systems using the HFA3842B is
made easier with the availability of evaluation board, firm-
ware, software device drivers, and complete documentation.

The HFA3842B is a WLAN MAC Controller IC, based on the
HFA3841. Pin-for-pin upgrade replacement for the HFA3841.

Applications

· High Data Rate Wireless LAN

· PC Card Wireless LAN Adapters

· USB Wireless LAN Adapters

· PCI Wireless LAN Cards (Using Ext. Bridge Chip)

· Wireless LAN Modules

· Wireless LAN Access Points

· Wireless Bridge Products

· Wireless Point-to-Multipoint Systems

· ISA, ISA PNP WLAN Cards

Features

· USB Host Interface supports USB V1.1 at 12Mbps, and is

an alternative to the PC Card host interface.

· New start up modes allow the PCMCIA Card Information

Structure to be initialized from a serial EEPROM. This
allows firmware to be downloaded from the host,
eliminating the parallel Flash memory device.

· Firmware can be loaded from serial Flash memory.

· Direct attachment to a typical x16 SRAM using five control

signals (RAMCS_, MOE_, MWEL_, MLBE_, and MUBE_).

· Low frequency crystal oscillator to maintain time and allow

baseband clock source to power off during sleep mode.

· Improved performance of internal WEP engine.

· On-chip execution can now be viewed while in debug

mode.

· Independent programmable cycle timing for external chip

selects allows attachment of slow memory devices without
compromising higher speed instruction execution.

· Pinout is backward compatible with HFA3841.

· IEEE802.11 Standard Data Rates: 1, 2, 5.5 and 11Mbps

· Part of the Intersil PRISM Wireless LAN Chip Set

· Full Implementation of the MAC Protocol Specified in IEEE

Standards 802.11-1999 and 802.11b

· PCMCIA Host Interface Supports Full 16-Bit

Implementation of PC Card 16 (1995), also ISA PNP with
Additional Chip

· Host Interface Provides Dual Buffer Access Paths

· External Memory Interface Supports up to 4M bytes RAM

· Internal Encryption Engine Executes IEEE802.11 WEP

· Low Power Operation; 25mA Active, 8mA Doze, <1mA

Sleep

· Operation at 2.7V to 3.6V Supply

· 5V Tolerant Host Interface Input/Outputs

· 128 Pin LQFP Package Targeted for Type II PC Cards

· IEEE802.11 Wireless LAN MAC Protocol Firmware and

Microsoft® Windows® Software Drivers

· Pin for Pin Replacement for the HFA3841 Supporting all

Functions and operations of the HFA3841

Ordering Information

PART

NUMBER

TEMP. RANGE

(

PACKAGE

PKG. NO.

HFA3842BIN

-40 to 85

128 Ld LQFP

Q128.14x20

HFA3842BIN-TK

-40 to 85

Tape and Reel

Data Sheet

June 2001

Microsoft® and Windows® are registered trademarks of Microsoft Corporation.

PRISM® is a registered trademark of Intersil Americas Inc.

PRISM and design is a trademark of Intersil Americas Inc.

Pinout

128 LEAD LQFP

Simplified Block Diagram

103

_IO

HD8

HD9

HD1

RAM

_IO

0/M

B+

I
N

SET

HD6

HD7

HCE

HD5

HD4

HD3

B-

_IO

HD2

HD1

HD0

HRE

INDEX

CHG

LFXTALI

CLKIN

LFXTALO

_IO3

PL4

MD15

MD14

MD13

MD12

MD11

MD10

MD9

MD8

_IO3

_CORE3

MD7

MD6

MD5

MD4

MD3

MD2

MD1

MD0

MLBE-

PK3

PK4

104
105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127
128

HINPACK-

HWAIT-

HA0

HA1

HA2

HA3

HA4

HA5

HA6

HA7

HIREQ-

_IO3

HWE-

HA8

HA9

HIOWR-

HIORD-

HOE-

HCE2-

HD15

_IO3

HD14

HD13

HD12

HD11

SB ATTACHED

PRISM RADIO

TXD/RXD

CTRL/STATUS

SERIAL CONTROL

PHY

SERIAL

CONTROL

(MMI)

PRISM RADIO

RADIO AND SYNTH

MICRO-

PROGRAMMED

MAC ENGINE

MEMORY

WEP

ENGINE

PC CARD

ON-CHIP

RAM

44MHz CLOCK

SOURCE

EXTERNAL
SRAM AND

FLASH

MEMORY

HOST

COMPUTER

DATA
ADDRESS

HFA3842B

USB

HOST

INTERFACE

USB

CONTROL

ON-CHIP

ROM

BASEBAND

PROCESSOR

RF SECTION

SERIAL CONTROL

INTERFACE

(MDI)

CONTROLLER

HOST

INTERFACE

THE 3842 MUST BE SUPPLIED WITH A

SEPARATE 48MHz CLOCK WHEN USB IS USED.

HFA3842B

HFA3842B Pin Descriptions

HOST INTERFACE PINS

PIN NAME

PIN NUMBER

PIN I/O TYPE

DESCRIPTION

HA0-9

106-113, 117, 118 5V Tol, CMOS, Input, 50K Pull Down

PC Card Address Input, Bits 0 to 9

HCE1-

5V Tol, CMOS, Input, 50K Pull Up

PC Card Select, Low Byte

HCE2-

122

5V Tol, CMOS, Input, 50K Pull Up

PC Card Select, High Byte

HD0-15

101-99, 6-2,

96-94, 128-125,

123

5V Tol, BiDir, 2mA, 50K Pull Down

PC Card Data Bus, Bit 0 to 15

HINPACK-

103

CMOS Output, 2mA

PC Card I/O Decode Confirmation

HIORD-

120

5V Tol, CMOS, Input, 50K Pull Up

PC Card I/O Space Read

HIOWR-

119

5V Tol, CMOS, Input, 50K Pull Up

PC Card I/O Space Write

HRDY/HIREQ-

114

CMOS Output, 4mA

PC Card interrupt Request (I/O Mode) Card Ready
(Memory Mode)

HOE-

121

5V Tol, CMOS, Input, 50K Pull Up

PC Card Memory Attribute Space Output Enable

HREG-

102

5V Tol, CMOS, Input, 50K Pull Up

PC Card Attribute Space Select

HRESET

5V Tol, CMOS, ST Input, 50K Pull Up

Hardware Reset

HSTSCHG-

CMOS Output, 4mA

PC Card Status Change

HWAIT-

104

CMOS Output, 4mA

PC Card Not Ready (Force Host Wait State)

HWE-

116

5V Tol, CMOS Input, 50K Pull Up

PC Card Memory Attribute Space Write Enable

USB+

CMOS BiDir, 2mA, (Also USB Transceiver)

USB, MBUS Address Bit 20, or I/O as PL5

USB-

CMOS BiDir, 2mA, (Also USB Transceiver)

USB, MBUS Address Bit 21, or I/O or I/O as PL6

USB ATTACHED

105

Input, 5V Tolerant, Pull-Down

Sense USB VBUS to Indicate Cable Attachment

TABLE 1. MEMORY INTERFACE PINS

PIN NAME

PIN NUMBER

PIN I/O TYPE

DESCRIPTION

MUBE- / MA0 /
MWEH-

CMOS TS Output, 2mA

MBUS Upper Byte Enable for x16 Memory; MBUS
Address Bit 0 (byte) for x8 Memory; High Byte Write
Enable for 2 x8 Memories

MA1-18

73-81, 84-92

CMOS TS Output, 2mA

MBUS Address Bits 1 to 18

PL4

CMOS BiDir, 2mA

MBUS Address Bit 19

PL5

CMOS BiDir, 2mA, 50K Pull Up

MBUS Address Bit 20 (See Note 1)

PL6

CMOS BiDir, 2mA

MBUS Address Bit 21 (See Note 1)

MLBE-

CMOS TS Output, 2mA, 50K Pull Up

MBUS Lower Byte Enable, or I/O as PM2

MOE-

CMOS TS Output, 2mA

Memory Output Enable

MWE- / MWEL-

CMOS TS Output, 2mA

Low (or only) Byte Memory Write Enable

RAMCS-

CMOS TS Output, 2mA

RAM Select

NVCS-

CMOS TS Output, 2mA

NV Memory Select

MD0-7

61-54

5V Tol, CMOS, BiDir, 2mA, 100K Pull Up

MBUS Low Data Byte, Bits 0 to 7

MD8-15

51-44

5V Tol, CMOS, BiDir, 2mA 50K Pull Down

MBUS High Data Byte, Bits 8 to 15

NOTE:

1. Not available if USB interface is used.

TABLE 2. GENERAL PURPOSE AND EEPROM PORT PINS

PIN NAME

PIN NUMBER

PIN I/O TYPE

DESCRIPTION OF FUNCTION

(IF OTHER THAN IO PORT)

GENERAL PURPOSE PORT PINS

TXD

CMOS BiDir, 2mA, 50K Pull Down

Transmit Data Out

TXC

CMOS BiDir, 2mA

Transmit Clock In/Out

RXD

CMOS Input

Receive Data In

RXC

CMOS Input

Receive Clock In

HFA3842B

PJ0

CMOS BiDir, 2mA, 50K Pull Down

MMI Clock (SCLK)

PJ1

CMOS BiDir, 2mA, 50K Pull Down

MMI Serial Data (SD)

PJ3

CMOS BiDir, 2mA

MMI Device Enable 0 (CS_BAR)

PJ4

CMOS BiDir, 2mA

MMI Device Enable 1 (PE1)

PJ5

CMOS BiDir, 2mA, 50K Pull Up

MBUS Request (LE_IF)

PJ6

CMOS BiDir, 2mA

MBUS Grant; LED

PJ7

CMOS BiDir, 2mA, 50K Pull Up

(RADIO_PE)

PK0

CMOS BiDir, 2mA, ST, 50K Pull Down

MPSI Clock (LE_RF)

PK1

CMOS BiDir, 2mA, 50K Pull Down

MPSI Data Out (SYNTHCLK)

PK2

CMOS BiDir, 2mA, 50K Pull Down

MPSI Data In (SYNTHDATA)

PK3

CMOS BiDir, 2mA

MPSI Device Select 0 (PA_PE)

PK4

CMOS BiDir, 2mA

MPSI Device Select 1 (PE2)

PK5

CMOS BiDir, 2mA

PHY Data Available (MDREADY)

PK6

CMOS BiDir, 2mA

PHY Medium Busy (CCA)

PK7

CMOS BiDir, 2mA

PHY Energy Detect (CAL_EN)

PL0

CMOS BiDir, 2mA

Transmitter Enable (TX_PE)

PL1

CMOS BiDir, 2mA

Receiver Enable (or PHY Sleep Control) (RX_PE)

PL2

CMOS BiDir, 2mA

PHY Reset (RESET_BB)

PL3

CMOS BiDir, 2mA

Antenna Select (T/R_SW_BAR)

PL4

CMOS BiDir, 2mA

MBUS Address Bit 19 (MA19)

PL5 (USB+)

CMOS BiDir, 2mA, (Also USB Transceiver)

MBUS Address Bit 20 (USB+)

PL6 (USB-)

CMOS BiDir, 2mA, (Also USB Transceiver)

MBUS Address Bit 21 (USB-)

PL7

CMOS BiDir, 2mA, Pull Down

PHY Transmit Ready (T/R_SW)

SERIAL EEPROM PORT PINS

PJ0

CMOS BiDir

SCLK, Serial Clock

PJ1

CMOS BiDir, 50K Pull Down

SD, Serial Data Out

PJ2

CMOS BiDir, 50K Pull Down

MISO, Serial Data IN

TCLKIN (CS_)

CMOS BiDir

CS_, Chip Select

TABLE 3. CLOCKS

PIN NAME

PIN NUMBER

PIN I/O TYPE

DESCRIPTION

CLKIN

CMOS Input, ST Pull Down

External Clock Input (at >= 2X Desired MCLK
Frequency, Typically 44-48MHz)

LFXTALI

Analog Input

32.768kHz Crystal Input (Note 2)

LFXTALO

CMOS Output, 2mA

32.768kHz Crystal Output

CLKOUT

CMOS, TS Output, 2mA

Clock Output (Selectable as MCLK, TCLK, or
TOUT0)

TCLKIN

CMOS BiDir, 2mA, 50K Pull Down

Alternate clock input for timers

TABLE 4. POWER

PIN NAME

PIN NUMBER

PIN I/O TYPE

DESCRIPTION

14, 25, 53, 66, 83, 98, 124

3.3V Supply

_IO5

105

5V Tolerance Supply

13, 24, 37, 42, 52, 67, 82, 97, 115

GND

ST = Schmitt Trigger (Hysteresis), TS = Three-State. Signals ending with "-" are active low.
NOTE:

2. Pin 39 (V

_CORE3 in 3841), has been reassigned as LFXTALI. For 3841 compatibility, it may be tied to V

Pin 62 (TRST- in 3841) has been reassigned as MLBE. For 3841 compatibility, it may be tied low through 1K.
Pin 105 (V

_IO5 in 3841) has been reassigned as USB ATTACHED. For 3841 compatibility, it may be tied to V

Output pins typically drive to positive voltage rail less 0.1V. Hence with a supply of 2.7V the output will just meet 5V TTL signal levels at
rated loads.

TABLE 2. GENERAL PURPOSE AND EEPROM PORT PINS (Continued)

PIN NAME

PIN NUMBER

PIN I/O TYPE

DESCRIPTION OF FUNCTION

(IF OTHER THAN IO PORT)

HFA3842B

TABLE 5. PORT PIN USES FOR PRISM APPLICATION

PIN

NAME

PRISM I USE

PRISM II USE

RXC

RXC - Receive Clock

RXD

RXD - Receive Data

TXC

TXC - Transmit Clock

TXD

TXD - Transmit Data

PJ0

SCLK - Clock for the SD Serial Bus

PJ1

SD - Serial Bidirectional Data Bus

SD - Serial Bi-Directional Data Bus

PJ2

R/W - An input to the HFA3860A Used to Change
the Direction of the SD Bus When Reading or
Writing Data on the SD Bus

Not Used

PJ3

CS - A Chip Select for the Device to Activate the
Serial Control Port (Active Low)

CS_BAR - Chip Select for HFA3861 Baseband
(Active Low)

PJ4

Not Used

PE1 - Power Enable 1

PJ5

SYNTH_LE - Latches a Frame of 22 Bits After it has
Been Shifted by the SCLK into the Synthesizer
Registers

LE_IF - Load Enable for HFA3783 Quad IF

PJ6

LED - Activity Indicator

PJ7

Not Used

RADIO_PE - RF Power Enable

PK0

Not Used

LE_RF - Load Enable for HFA3683 RF Chip

PK1

Not Used

SYNTHCLK - Serial Clock to Front End Chips

PK2

Not Used

SYNTHDATA - Serial Data to Front End Chips

PK3

TX_PE_RF - Power Enable

PA_PE - Transmit PA Power Enable

PK4

RX_PE_RF - Power Enable

PE2 - Power Enable 2

PK5

MD_RDY - Header Data and Data Packet are
Ready to be Transferred From Baseband on RXD

MDREADY - Header Data and Data Packet are
Ready to be Transferred from Baseband on RXD

PK6

CCA - Signal that the Channel is Clear to Transmit

PK7

RADIO_PE - Master Power Control for the RF
Section

CAL_EN - Calibration Mode Enable

PL0

TX_PE and PA_PE - Transmit Enable to Baseband TX_PE - Transmit Enable to Baseband

PL1

RX_PE - Receive Enable to Baseband

PL2

RESET - Reset to Baseband

RESET_BB - Reset Baseband

PL3

Not Used

T/R-SW_BAR - Transient/Receive Control (Inverted)

PL4

MA19 (If Required)

PL5

MA20 (If Required)

MA20 (If Required) or USB+

PL6

MA21 (If Required)

MA21 (If Required) or USB-

PL7

TX_RDY - Baseband Ready to Receive Data on
TXD (Not Used By Firmware)

T/R_SW - Transmit/Receive Control

HFA3842B

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