4-1062
August 1997
HI1172
6-Bit, 20 MSPS,
Video A/D Converter (CMOS)
Features
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-Bit
Maximum Sampling Frequency . . . . . . . . . . . 20 MSPS
Low Power Consumption at 20 MSPS (Typ)
(Reference Current Excluded) . . . . . . . . . . . . . . .40mW
Built-In Sample and Hold Circuit
Three-State TTL Compatible Output
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Single
Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . 4pF
Reference Impedance . . . . . . . . . . . . . . . . . . 250
(Typ)
Applications
Video Digitizing
Wireless Communications
Description
HI1172 is a 6-bit, CMOS A/D converter for video use. The
adoption of a 2-step parallel conversion achieves speeds of
20 MSPS minimum, 35 MSPS typical.
Pinout
HI1172
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART
NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
HI1172JCP
-20 to 75
16 Ld PDIP
E16.3A-S
HI1172JCB
-20 to 75
16 Ld SOIC
M16.2-S
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
D
0
D
1
D
2
D
3
D
4
D
5
DV
SS
CLK
AV
SS
AV
DD
V
RB
V
IN
V
RT
AV
DD
DV
DD
DV
DD
File Number
4102.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
4-1065
Absolute Maximum Ratings
T
A
= 25
o
C
Thermal Information
Supply Voltage (V
DD
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Reference Voltage (V
RT
, V
RB
) . . . . . . . . . . . . . . . . . . . . V
DD
to V
SS
Analog Input Voltage (V
IN
) . . . . . . . . . . . . . . . . . . . . . . . V
DD
to V
SS
Digital Input Voltage (CLK) . . . . . . . . . . . . . . . . . . . . . . . V
DD
to V
SS
Digital Output Voltage (V
OH
, V
OL
) . . . . . . . . . . . . . . . . . V
DD
to V
SS
Operating Conditions
Supply Voltage Range, AV
DD
, AV
SS
. . . . . . . . . . . . 4.75V to 5.25V
Reference Voltage, DV
DD
, DV
SS
V
RT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9V to 5V
V
RB
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 4.1V
V
RT
- V
RB
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.9V to AV
DD
Analog Input Voltage (V
IN
) . . . . . . . . . . . . . . . . . . . . . . . V
RB
to V
RT
Clock Pulse Width
t
PW1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min)
t
PW0
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min)
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -20
o
C to 75
o
C
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
94
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V
DD
= +5V, V
RB
= 1V, V
RT
= 2V, T
A
= 25
o
C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Conversion Speed, f
C
f
C
V
IN
= 1V to 2V
f
IN
= 1kHz Ramp
0.5
-
20
MSPS
Integral Non-Linearity
E
L
f
C
= 20 MSPS
V
IN
= 1V to 2V
-
0.3
0.5
LSB
Differential Non-Linearity
E
D
f
C
= 20 MSPS
V
IN
= 1V to 2V
-
0.3
0.5
LSB
Supply Current
I
DD
f
C
= 20 MSPS
NTSC Ramp Wave Input
-
7
12
mA
Reference Pin Current
I
REF
3
4
5.7
mA
Analog Input (-1dB)
BW
-
18
-
MHz
Analog Input Capacitance
C
IN
V
IN
= 1.5V + 0.07V
RMS
-
4
-
pF
Reference Resistance (V
RT
to V
RB
)
R
REF
175
250
325
Offset Voltage
E
OT
0
-20
-40
mV
E
OB
15
35
55
mV
Digital Input Voltage
V
IH
4.0
-
-
V
V
IL
-
-
1.0
V
Digital Input Current
I
IH
V
DD
= Max
V
IH
= V
DD
-
-
5
A
I
IL
V
IL
= 0V
-
-
5
A
Digital Output Current
I
OH
V
DD
= Min
V
OH
= V
DD
= 0.5V
-1.1
-
-
mA
I
OL
V
OL
= 0.4V
3.7
-
-
mA
Output Data Delay
T
DL
With TTL 1 Gate and 10pF Load
-
18
30
ns
Differential Gain Error
DG
NTSC 40 IRE Mod
-
1.0
-
%
Differential Phase Error
DP
Ramp, f
C
= 14.3 MSPS
-
1.0
-
deg
Aperture Jitter
t
AJ
-
40
-
ps
Sampling Delay
t
SD
-
4
-
ns
HI1172
4-1066
Test Circuits
I
I
-
V
IN
HI1172
DUT
6
CLK (20MHz)
+
A<B
A>B
COMPARATOR
A6
A1
A0
B6
B1
B0
"0"
"1"
6
S1
S2
-V
+V
S1 : ON IF A < B
S2 : ON IF B > A
BUFFER
DVM
CONTROLLER
6
TO
111 10
000 00
FIGURE 1. INTEGRAL NON-LINEARITY ERROR, DIFFERENTIAL NON-LINEARITY, OFFSET VOLTAGE
SIGNAL
SOURCE
NTSC
SG
V
IN
6
6
SCOPE
VECTOR
620
DG
ERROR RATE
SG
(CW)
AMP
HI1172
ECL
TTL
D/A
10-BIT
-5.2V
CLK
1
2
1
2
HPF
COUNTER
DP
620
-5.2V
ECL
TTL
f
C
-40
0
100
IAE
SYNC
BURST
1V
2V
40 IRE
MODULATION
1V
2V
f
C
-1kHz
HI20201
FIGURE 2. MAXIMUM OPERATIONAL SPEED, DIFFERENTIAL GAIN ERROR, DIFFERENTIAL PHASE ERROR
V
RT
V
IN
V
RB
CLK
GND
V
DD
1.0V
2.0V
V
OL
I
OL
+
-
V
RT
V
IN
V
RB
CLK
GND
V
DD
1.0V
2.0V
V
OH
I
OH
+
-
FIGURE 3. DIGITAL OUTPUT CURRENT TEST CIRCUIT
HI1172
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