Электронный компонент: HI1-7151T-2

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1

�

December 1997

HI-7151

10-Bit, High Speed, A/D Converter

with Track and Hold

Features

� Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

�s

� Continuous Throughput Rate . . . . . . . . . . . . . . . 100kHz

� No Offset or Gain Adjustments Necessary

� Internal Track and Hold Amplifier

� Analog and Reference Inputs Fully Buffered

�

�P Compatible Byte Organized Outputs

� Low Power Consumption . . . . . . . . . . . . . . . . . . 150mW

� Uses a Single 2.5V Reference for

�2.5 V Input Range

Applications

�

�P Controlled Data Acquisition Systems

� DSP

- Avionics
- Sonar

� Process Control

- Automotive Transducer Sensing
- Industrial

� Robotics

� Digital Communications

� Image Processing

Description

The Intersil HI-7151 is a high speed 10-bit A/D converter
which uses a 2-Step Flash algorithm to achieve throughput
rates of 100kHz. A unique switched capacitor technique
allows a new input voltage to be sampled while a conversion
is taking place.
A Track and Hold amplifier is included on the chip, consisting
of two high speed amplifiers and an internal hold capacitor.
Microprocessor bus interfacing is simplified by the use of
standard Chip Select, Read, and Write control signals. The
digital three-state outputs are byte organized for interfacing
the either 8- or 16-bit systems. An Over-Range pin, together
with the MSB, can be used to indicate an out-of-range
condition.
The HI-7151 operates with

�5V supplies. A single +2.5V

reference is required to provide a bipolar input range from
-2.5V to +2.5V.
Internal high speed CMOS buffers at both the analog and
reference inputs simplify external drive requirements.

Pinout

HI-7151

(PDIP, CERDIP)

TOP VIEW

Ordering Information

PART

NUMBER

LINEARITY

(MAX. DLE)

TEMP.

RANGE (

o

C)

PACKAGE

HI3-7151J-5

�1 LSB

0 to 75

28 Ld PDIP

HI3-7151K-5

�

1

/

2

LSB

0 to 75

28 Ld PDIP

HI3-7151A-9

�1 LSB

0 to 85

28 Ld PDIP

HI3-7151B-9

�

1

/

2

LSB

0 to 85

28 Ld PDIP

HI1-7151S-2

�1 LSB

-55 to 125

28 Ld CERDIP

HI1-7151T-2

�

1

/

2

LSB

-55 to 125

28 Ld CERDIP

GND

V-

V

REF

AG

V

IN

SET

BUSY

CLK

HOLD

WR

CS

RD

SMODE

DG

V+

D9

D8

D7

D6

D4

D2

D1

D0

HBE

BUS

OVR

D5

D3

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143

|

Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright � Intersil Americas Inc. 2002. All Rights Reserved

File Number

3099.1

NOT

REC

OMM

END

ED F

OR N

EW D

ESIG

NS

2

Functional Diagram

REF

AMP

REF

INVERT

INPUT

BUFFER

AMP

TRACK

HOLD

AMP

TWO

STEP

FLASH

POWER

SUPPLY

DISTRIBUTION

CONTROL

LOGIC

V

REF

AG

(ANALOG GROUND)

V

IN

(ANALOG INPUT)

V+

V-

GND

DG

(DIGITAL GROUND)

28

2

1

14

5

4

3

RESISTOR

LADDER

LATCHES

AND

(33)

(1)

OUTPUT

BUFFERS

BUS

CTRL

(+)

(-)

16

15

7

27

26

17

HBE

BUS

BUSY

OVR

D9

DATA

OUTPUTS

D0

9

HOLD

12

RD

10

WR

11

CS

13

SMODE

8
6

CLK
SET

HI-7151

3

Pin Descriptions

PIN

NAME

DESCRIPTION

1

GND

Ground return for comparators (0V).

2

V-

Negative supply voltage input (-5V).

3

V

REF

Reference voltage input (+2.5V).

4

AG

Analog ground reference (0V).

5

V

IN

Analog Input Voltage.

6

SET

Connect to V+ for proper operation.

7

BUSY

Output High-Conversion complete. Output Low - Conversion in progress. Output floats when chip is not selected (RD
and CS both high).

8

CLK

Clock input.

9

HOLD

Indicates start of conversion. Active low.

10

WR

Write input. With CS low, starts conversion when pulsed low; continuous conversions when kept low.

11

CS

Chip select input. Active low.

12

RD

Read input. With CS low, enables output buffers when pulsed low; outputs updated at end of conversion when kept low.

13

SMODE Slow memory mode input. Active high.

14

DG

Digital ground (0V).

15

BUS

Bus select input. High = all outputs enabled together D0 - D9, OVR. Low = outputs enabled by HBE.

16

HBE

Byte select (HBE/LBE) input for 8-bit bus. Input high-High byte select, D8-D9, OVR Input low-low byte select, D0-D7.

17

D0

Bit 0 (Least significant, LSB).

Output Data Bits

(High = True)

Low

Byte

18

D1

Bit 1.

19

D2

Bit 2.

20

D3`

Bit 3.

21

D4

Bit 4.

22

D5

Bit 5.

23

D6

Bit 6.

24

D7

Bit 7.

25

D8

Bit 8 (Most Significant).

High
Byte

26

D9

Bit 9 (Sign).

27

OVR

Out of Range flag. Valid at end of conversion when output exceeds full scale.

28

V+

Positive supply voltage input (+5V).

HI-7151

4

Absolute Maximum Ratings

(Note 1)

Thermal Information

Supply Voltage

V+ to Gnd (DG/AG/GND) . . . . . . . . . . . . . . . . -0.3V < V+ < +5.7V
V- to Gnd (DG/AG/GND). . . . . . . . . . . . . . . . . .-5.7V < V- < +0.3V

Analog Input Pins . . . . . . . . . . . . . . . . . V- -0.3V < V

INA

< V+ +0.3V

Digital I/O Pins . . . . . . . . . . . . . . . . . . .DG - 0.3V < V

I/O

< V+ +0.3V

Operating Conditions

Temperature Range

HI3-7151X-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0

o

C to 75

o

C

HI3-7151X-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40

o

C to 85

o

C

Thermal Resistance (Typical)

JA

(

o

C/W)

JC

(

o

C/W)

PDIP Package . . . . . . . . . . . . . . . . . . .

__

N/A

CERDIP Package . . . . . . . . . . . . . . . .

__

__

Maximum Power Dissipation (Note 2). . . . . . . . . . . . . . . . . <500mW
Maximum Storage Temperature Range . . . . . . . . . . -65

o

C to 150

o

C

Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300

o

C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Input voltages may exceed the supply voltage provided the inputs current is limited to

�1mA.

2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board (derate above 75

o

C at -10mW/

o

C).

Electrical Specifications

V+ = +5V, V- = -5V, V

REF

= 2.5V, f

CLK

= 300kHz, 50% Duty Cycle, Unless Otherwise Specified (Note 4)

PARAMETER

SYMBOL

(NOTE 3)

TEMPERATURE

J, A GRADE

K, B GRADE

UNITS

MIN

TYP

MAX

MIN

TYP

MAX

ACCURACY

Resolution (Note 5) (With
no missing codes)

RES

T

A

= -25

o

C

10

-

-

10

-

-

Bits

T

MIN

to T

MAX

10

-

-

10

-

-

Bits

Integral Linearity Error

ILE

T

A

= 25

o

C

-

�0.5

�1.0

-

�0.3

�-0.5

LSB

T

MIN

to T

MAX

-

�0.75

�1.0

-

�0.5

�0.75

LSB

Differential Linearity Error

DLE

T

A

= 25

o

C

-

-

�1.0

-

-

�0.5

LSB

T

MIN

to T

MAX

-

-

�1.0

-

-

�0.75

LSB

Bipolar Offset Error

V

OS

T

A

= 25

o

C

-

�1.0

�2.5

-

�0.6

�1.5

LSB

T

MIN

to T

MAX

-

�1.5

�3.0

-

�1.0

�2.0

LSB

Unadjusted Gain Error

eG+ and

eG-

T

A

= 25

o

C

-

�1.0

�2.5

-

�0.6

�1.5

LSB

T

MIN

to T

MAX

-

�1.5

�3.0

-

�1.0

�2.0

LSB

NOTE:

3. T

MIN

to T

MAX

: See Ordering Information Table.

DC Electrical Specifications

V+ = 5V, V- = -5V, V

REF

= 2.5V, T

A

= 25

o

C, f

CLK

= 300kHz, 50% Duty Cycle,

Unless Otherwise Specified

PARAMETER

SYMBOL

(NOTE 4)

CONDITIONS

25

o

C

0

o

C to 75

o

C

-40

o

C to 85

o

C

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

ANALOG INPUT

Analog Input Range

V

IR

V

IN

= 0V

-V

REF

-

V

REF

-V

REF

V

REF

-V

REF

V

REF

V

Analog INput Bias Current

I

BI

-

0.01

100

-

100

-

100

nA

Analog Input Capacitance
(Note 5)

CV

IN

-

8

20

-

-

-

-

pF

REFERENCE INPUT

Reference Input Range
(Note 6)

V

RR

V

REF

= 2.5V

2.2

2.5

2.6

2.2

2.6

2.2

2.6

V

Reference Input Bias Current

I

BR

-

0.01

100

-

100

-

100

nA

Reference Input Capacitance
(Note 5)

CV

R

-

7

20

-

-

-

-

pF

HI-7151

5

TRACK AND HOLD (See Text)

Slew Rate

SR

-

9

-

-

-

-

-

V/

�s

Bandwidth

BW

-

1.5

-

-

-

-

-

MHz

Aperture Time

-

30

-

-

-

-

-

ns

Aperture Uncertainty

-

2

-

-

-

-

-

ns

Feedthrough in HOLD

f

IN

= 100kHz

-

-80

-

-

-

-

-

dB

Acquisition Time

-

1.5

-

-

-

-

-

�s

LOGIC INPUTS

Input High Voltage

V

IH

2.0

-

-

2.0

-

2.0

-

V

Input Low Voltage

V

IL

-

-

0.8

-

0.8

-

0.8

V

Logic Input Current

I

IL

V

IN

= 0V, V+

-

0.05

1

-

1

-

1

�A

Input Capacitance (Note 5)

C

IN

-

5

17

-

-

-

-

pF

LOGIC OUTPUTS

Output High Voltage

V

OH

I

OH

= -200

�A

2.4

-

-

2.4

-

2.4

-

V

Output Low Voltage

V

OL

I

OL

= 1.6mA

-

-

0.4

-

0.4

-

0.4

V

Output Leakage Current

I

OL

RD = V+, V

OUT

= V+

-

0.04

1

-

10

-

10

�A

RD = V+, V

OUT

= 0V

-1

-0.01

-

-10

-

-10

-

�A

Output Capacitance (Note 5)

C

OUT

High-Z State

-

7

15

-

-

-

-

pF

POWER SUPPLY VOLTAGE RANGE

(Note 7)

V+

Function Operation
Only

4.5

5.0

5.5

4.5

5.5

4.5

5.5

V

(Note 7)

V-

-4.5

-5.0

-5.5

-4.5

-5.5

-4.5

-5.5

V

POWER SUPPLY REJECTION

V+, V- Gain Coefficient

eGVS

V+ = 5V, V- = -4.75V,
-5.25V

-

�0.1

�0.05

-

�0.6

-

�0.6

LSB

V- = -5V, V+ = 4.75V,
5.25V

-

�0.1

�0.5

-

�0.6

-

�0.6

LSB

V+, V- Offset Coefficient

VOSVS

V+ = 5V, V- = -4.75V,
-5.25V

-

�0.1

�0.5

-

�0.6

-

�0.6

LSB

V- = -5V, V+ = 4.75V,
5.25V

-

�0.1

�0.5

-

�0.6

-

�0.6

LSB

SUPPLY CURRENTS

V+ Supply Current

I+

V+ = 5V

�10%

V- = -5V

�10%

V

IN

= 0V, Digital

Outputs are
Unloaded

-

20

30

-

30

-

30

mA

V- Supply Current

I-

-

-10

-15

-

-15

-

-15

mA

GND Current

I

GND

-

-8

-15

-

-15

-

-15

mA

DG Current

I

DG

-

-2

-3

-

-3

-

-3

mA

AG Current

I

AG

-

0.02

10

-

10

-

10

�A

NOTES:

4. FSR (Full Scale Range) = 2 X V

REF

(5V at V

REF

= 2.5V). LSB (Least Significant Bit) = FSR/1024 (4.88mV at V

REF

= 2.5V)

5. Parameter not tested. Parameter guaranteed by design, simulation, or characterization.
6. Only V

OS

and GAIN ERROR functionality tested at 2.2V and 2.6V.

7. Guaranteed by functionality test.

DC Electrical Specifications

V+ = 5V, V- = -5V, V

REF

= 2.5V, T

A

= 25

o

C, f

CLK

= 300kHz, 50% Duty Cycle,

Unless Otherwise Specified (Continued)

PARAMETER

SYMBOL

(NOTE 4)

CONDITIONS

25

o

C

0

o

C to 75

o

C

-40

o

C to 85

o

C

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HI-7151

Document Outline

• HI-7151
• HI-7151
• HI-7151
• HI-7151
• HI-7151
• HI-7151
• HI-7151
• HI-7151
• HI-7151
• HI-7151
• HI-7151
• HI-7151
• HI-7151
• HI-7151
• HI-7151
  • December 1997
• HI-7151
  • 10-Bit, High Speed, A/D Converter with Track and Hold
  • Description
    • The Intersil HI-7151 is a high speed 10-bit A/D converter which uses a 2-Step Flash algorithm to ...
    • A Track and Hold amplifier is included on the chip, consisting of two high speed amplifiers and a...
    • Microprocessor bus interfacing is simplified by the use of standard Chip Select, Read, and Write ...
    • The HI-7151 operates with �5V supplies. A single +2.5V reference is required to provide a bipola...
    • Internal high speed CMOS buffers at both the analog and reference inputs simplify external drive ...
      • �1 LSB
      • 0 to 75
      • �1/2 LSB
      • 0 to 75
      • �1 LSB
      • 0 to 85
      • �1/2 LSB
      • 0 to 85
      • �1 LSB
      • -55 to 125
      • �1/2 LSB
      • -55 to 125
    • Pinout
      • HI-7151 (PDIP, CERDIP)
        • TOP VIEW
• Functional Diagram
• Pin Descriptions
  • 1
  • GND
  • 2
  • V-
  • 3
  • VREF
  • 4
  • AG
  • 5
  • VIN
  • 6
  • SET
  • 7
  • BUSY
  • 8
  • CLK
  • 9
  • HOLD
  • 10
  • WR
  • 11
  • CS
  • 12
  • RD
  • 13
  • SMODE
  • 14
  • DG
  • 15
  • BUS
  • 16
  • HBE
  • 17
  • D0
  • Output Data Bits (High = True)
  • Low
  • Byte
  • 18
  • D1
  • 19
  • D2
  • 20
  • D3�
  • 21
  • D4
  • 22
  • D5
  • 23
  • D6
  • 24
  • D7
  • 25
  • D8
  • High Byte
  • 26
  • D9
  • 27
  • OVR
  • 28
  • V+
    • Thermal Information
    • Operating Conditions
      • 1. Input voltages may exceed the supply voltage provided the inputs current is limited to �1mA.
      • 2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board...
  • RES
  • 10
  • -
  • -
  • 10
  • -
  • -
  • Bits
  • 10
  • -
  • -
  • 10
  • -
  • -
  • Bits
  • ILE
  • -
  • �0.5
  • �1.0
  • -
  • �0.3
  • �-0.5
  • LSB
  • -
  • �0.75
  • �1.0
  • -
  • �0.5
  • �0.75
  • LSB
  • DLE
  • -
  • -
  • �1.0
  • -
  • -
  • �0.5
  • LSB
  • -
  • -
  • �1.0
  • -
  • -
  • �0.75
  • LSB
  • VOS
  • -
  • �1.0
  • �2.5
  • -
  • �0.6
  • �1.5
  • LSB
  • -
  • �1.5
  • �3.0
  • -
  • �1.0
  • �2.0
  • LSB
  • eG+ and eG-
  • -
  • �1.0
  • �2.5
  • -
  • �0.6
  • �1.5
  • LSB
  • -
  • �1.5
  • �3.0
  • -
  • �1.0
  • �2.0
  • LSB
    • 3. TMIN to TMAX:See Ordering Information Table.
    • DC Electrical SpecificationsV+ = 5V, V- = -5V, VREF = 2.5V, TA = 25oC, fCLK = 300kHz, 50% Duty C...
  • VIR
  • -VREF
  • -
  • VREF
  • -VREF
  • VREF
  • -VREF
  • VREF
  • V
  • IBI
  • -
  • 0.01
  • 100
  • -
  • 100
  • -
  • 100
  • nA
  • CVIN
  • -
  • 8
  • 20
  • -
  • -
  • -
  • -
  • pF
  • VRR
  • 2.2
  • 2.5
  • 2.6
  • 2.2
  • 2.6
  • 2.2
  • 2.6
  • V
  • IBR
  • -
  • 0.01
  • 100
  • -
  • 100
  • -
  • 100
  • nA
  • CVR
  • -
  • 7
  • 20
  • -
  • -
  • -
  • -
  • pF
  • SR
  • -
  • 9
  • -
  • -
  • -
  • -
  • -
  • V/ms
  • BW
  • -
  • 1.5
  • -
  • -
  • -
  • -
  • -
  • MHz
  • -
  • 30
  • -
  • -
  • -
  • -
  • -
  • ns
  • -
  • 2
  • -
  • -
  • -
  • -
  • -
  • ns
  • -
  • -80
  • -
  • -
  • -
  • -
  • -
  • dB
  • -
  • 1.5
  • -
  • -
  • -
  • -
  • -
  • ms
  • VIH
  • 2.0
  • -
  • -
  • 2.0
  • -
  • 2.0
  • -
  • V
  • VIL
  • -
  • -
  • 0.8
  • -
  • 0.8
  • -
  • 0.8
  • V
  • IIL
  • -
  • 0.05
  • 1
  • -
  • 1
  • -
  • 1
  • mA
  • CIN
  • -
  • 5
  • 17
  • -
  • -
  • -
  • -
  • pF
  • VOH
  • 2.4
  • -
  • -
  • 2.4
  • -
  • 2.4
  • -
  • V
  • VOL
  • -
  • -
  • 0.4
  • -
  • 0.4
  • -
  • 0.4
  • V
  • IOL
  • -
  • 0.04
  • 1
  • -
  • 10
  • -
  • 10
  • mA
  • -1
  • -0.01
  • -
  • -10
  • -
  • -10
  • -
  • mA
  • COUT
  • -
  • 7
  • 15
  • -
  • -
  • -
  • -
  • pF
  • V+
  • 4.5
  • 5.0
  • 5.5
  • 4.5
  • 5.5
  • 4.5
  • 5.5
  • V
  • V-
  • -4.5
  • -5.0
  • -5.5
  • -4.5
  • -5.5
  • -4.5
  • -5.5
  • V
  • eGVS
  • -
  • �0.1
  • �0.05
  • -
  • �0.6
  • -
  • �0.6
  • LSB
  • -
  • �0.1
  • �0.5
  • -
  • �0.6
  • -
  • �0.6
  • LSB
  • VOSVS
  • -
  • �0.1
  • �0.5
  • -
  • �0.6
  • -
  • �0.6
  • LSB
  • -
  • �0.1
  • �0.5
  • -
  • �0.6
  • -
  • �0.6
  • LSB
  • I+
  • -
  • 20
  • 30
  • -
  • 30
  • -
  • 30
  • mA
  • I-
  • -
  • -10
  • -15
  • -
  • -15
  • -
  • -15
  • mA
  • IGND
  • -
  • -8
  • -15
  • -
  • -15
  • -
  • -15
  • mA
  • IDG
  • -
  • -2
  • -3
  • -
  • -3
  • -
  • -3
  • mA
  • IAG
  • -
  • 0.02
  • 10
  • -
  • 10
  • -
  • 10
  • mA
    • 4. FSR (Full Scale Range) = 2 X VREF (5V at VREF = 2.5V). LSB (Least Significant Bit) = FSR/1024...
    • 5. Parameter not tested. Parameter guaranteed by design, simulation, or characterization.
    • 6. Only VOS and GAIN ERROR functionality tested at 2.2V and 2.6V.
    • 7. Guaranteed by functionality test.
    • AC Electrical SpecificationsV+ = 5V �10%, V- = -5V �10%, VREF = 2.5V, TA = 25oC, fCLK = 300kHz, ...
  • D
  • 5
  • 45
  • 50
  • 55
  • 45
  • 55
  • 45
  • 55
  • %
  • tSPS
  • 9
  • -
  • -
  • 3tck
  • -
  • 3tck
  • -
  • 3tck
  • ms
  • 9
  • 60
  • -
  • 10
  • 60
  • 10
  • 60
  • 10
  • ms
  • tCONV
  • 5, 8
  • -
  • -
  • 4tck +0.9
  • -
  • 4tck +0.9
  • -
  • 4tck +0.9
  • ms
  • tCYC
  • 9
  • -
  • -
  • fCLK/3
  • -
  • fCLK/3
  • -
  • fCLK/3/ 3
  • sps
  • tCK
  • -
  • -
  • 1/fCLK
  • -
  • -
  • -
  • -
  • -
  • tCKHR
  • 5
  • 150
  • 290
  • 500
  • 140
  • 525
  • 120
  • 525
  • ns
  • tWRL
  • 5, 8, 10
  • 200
  • 113
  • tck/2
  • 225
  • tck/2
  • 225
  • tck/2
  • ns
  • tHOLD
  • 5, 8
  • -
  • 80
  • 170
  • -
  • 200
  • -
  • 200
  • ns
  • tBD
  • 5, 8
  • -
  • 40
  • 200
  • -
  • 230
  • -
  • 230
  • ns
  • tWRD
  • 5, 8
  • 100
  • -
  • -
  • 100
  • -
  • 100
  • -
  • ns
  • tCKHF
  • 5, 9
  • 50
  • 125
  • 250
  • 40
  • 275
  • 25
  • 275
  • ns
  • tDATA
  • 5, 9
  • 100
  • 200
  • 400
  • 90
  • 550
  • 70
  • 550
  • ns
  • tRD
  • 5, 13
  • -
  • 75
  • 150
  • -
  • 190
  • -
  • 190
  • ns
  • tRX
  • 5, 14
  • -
  • 25
  • 60
  • -
  • 80
  • -
  • 80
  • ns
  • tAD
  • 5
  • -
  • 70
  • 150
  • -
  • 165
  • -
  • 165
  • ns
  • tCD
  • 5
  • -
  • 95
  • 180
  • -
  • 210
  • -
  • 210
  • ns
  • tBUSY
  • 5
  • -
  • 35
  • 200
  • -
  • 200
  • -
  • 200
  • ns
  • tr
  • 5, 12
  • -
  • 50
  • 100
  • -
  • 125
  • -
  • 125
  • ns
  • tf
  • 5, 12
  • -
  • 45
  • 100
  • -
  • 120
  • -
  • 120
  • ns
    • 8. Slow memory mode timing.
    • 9. Fast memory or DMA mode of operation, except the first conversion which is equal to tCONV.
    • 10. Maximum specification to prevent multiple triggering with WR.
    • 11. All input drive signals are specified with tr = tf � 20ns and shall swing from VIL -0.4V to ...
    • 12. tr and tf load is CL = 100pF (including stray capacitance) to DG and is measured from the 10...
    • 13. tRD is the time required for the data output level to change by 10% in response to RD crossi...
    • 14. trx is the time required for the data output level to change by 10% in response to RD crossi...
• Timing Diagrams 
  • FIGURE 1A. SLOW MEMORY MODE (16-BIT DATA BUS)
  • FIGURE 1B. FAST MEMORY MODE (8-BIT DATA BUS)
  • FIGURE 1C. DMA MODE
  • FIGURE 2. DETAILED BLOCK DIAGRAM
• Detailed Description
  • The HI-7151 is a high speed 10-bit A/D converter which achieves throughput rates of 100kHz by use...
• A/D Section
  • The HI-7151 uses a conversion algorithm which is generally called a �Two Step Flash� algorithm. T...
  • The input voltage is first converted into a 5-bit result (plus Out of Range information) by the f...
  • The reference input to the HI-7151 is buffered by a high speed CMOS amplifier which is used to dr...
  • The 5-bit result of the first flash conversion is latched into the upper five bits of double buff...
  • The 5-bit result of the second flash conversion is latched into the lower five bits of double buf...
  • The conversion takes place in three clock cycles and is illustrated in Figure 3. When the conver...
    • FIGURE 3. INTERNAL ADC TIMING DIAGRAM
    • TABLE 1. A/D OUTPUT CODE TABLE
    • 1
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 1
    • 1
    • 1
    • 1
    • 1
    • 1
    • 1
    • 1
    • 1
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 1
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 1
    • 1
    • 1
    • 1
    • 1
    • 1
    • 1
    • 1
    • 1
    • 1
    • 0
    • 1
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 1
    • 1
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
    • 0
• Track and Hold Analog Input
  • A Track and Hold amplifier has been fully integrated on the front end of the A/D converter. Becau...
  • The timing signals for the Track and Hold amplifier are generated internally, and are also provi...
  • Acquisition of the analog input signal is the time required by the T/H for its output to reach it...
  • Aperture delay time is the time required for the T/H switch to open following the internal hold c...
  • Aperture uncertainty (jitter) is a range of variation in the aperture time. The greater the apert...
  • All of the internal amplifiers are offset trimmed at the factory to give improved accuracy and to...
• Reference Input
  • The reference input to the HI-7151 is buffered by a high speed CMOS amplifier. The reference inpu...
• Power Requirements
  • Power to the chip should be applied in the following order: V, V+, and VREF. In applications wh...
• Initialization
  • In fast memory and DMA modes (after proper power, VREF, and clock) up to 6 clock cycles are requ...
• Microprocessor Interface
  • The HI-7151 can be interfaced to microprocessors through the use of standard Write, Read, Chip Se...
  • The HI-7151 can be interfaced to a microprocessor using one of three modes: slow memory, fast mem...
• Slow Memory Mode
  • In slow memory mode, the conversion will be initiated by the microprocessor by selecting the chip...
    • TABLE 2. SLOW MEMORY MODE I/O TRUTH TABLE (SMODE = V+)
    • 0
    • 0
    • X
    • X
    • X
    • 1
    • X
    • X
    • X
    • X
    • 0
    • X
    • 0
    • 1
    • X
    • 0
    • X
    • 0
    • 0
    • 0
    • 0
    • X
    • 0
    • 0
    • 1
    • X
    • X
    • 1
    • X
    • X
• Fast Memory Mode
  • The fast memory mode of operation is selected by tying the SMODE and WR pins to DG. In this mode,...
  • Data can be read a byte at a time or all 11 bits at once. The internal logic disables the output ...
  • The data can be defined in time by monitoring the HOLD pin. The conversion data can be read after...
    • TABLE 3. FAST MEMORY MODE I/O TRUTH TABLE (SMODE = DG)
    • X
    • 0
    • X
    • X
    • X
    • 1
    • X
    • X
    • X
    • X
    • 0
    • X
    • 0
    • 1
    • X
    • 0
    • X
    • 0
    • 0
    • 1
    • 0
    • X
    • 0
    • 0
    • 0
    • X
    • X
    • 1
    • X
    • X
• DMA Mode
  • This mode is a complete hardware mode where the HI-7151 continuously converts. The user implement...
    • TABLE 4. DMA MODE I/O TRUTH TABLE (SMODE = V+, CS = WR, RD = DG)
    • 1
    • X
    • 0
    • 0
    • 0
    • 1
• Optimizing System Performance
  • The HI-7151 has three ground pins (AG, DG, GND) for improved system accuracy. Proper grounding an...
  • As in any analog system, good supply bypassing is necessary in order to achieve optimum system p...
  • The pins on the HI-7151 are arranged such that the analog pins are well isolated from the digital...
• Applications
  • Typical applications are illustrated in Figures 5 through 7 for the slow memory, fast memory, and...
  • Figure 8 illustrates an application where the HI-7151 is used with an analog multiplexer to form ...
  • An intelligent system which performs a scale factor adjustment under software control with the a...
  • The accuracy of the programmable gain amplifier should be better than 0.05%. For optimum system p...
  • Figure 10 illustrates the HI-7151 interfaced to FIFO memories for use in DMA applications.
    • FIGURE 4. GROUND AND POWER SUPPLY DECOUPLING
    • FIGURE 5. SLOW MEMORY MODE APPLICATION
    • FIGURE 6. FAST MEMORY MODE APPLICATION
    • FIGURE 7. DMA MODE APPLICATION
    • FIGURE 8. MULTI-CHANNEL DATA ACQUISITION SYSTEM
    • FIGURE 9. MULTI-CHANNEL DATA ACQUISITION SYSTEM WITH PROGRAMMABLE GAIN
    • FIGURE 10. DMA/FIFO DATA ACQUISITION SYSTEM