CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil Corporation 1999

HI2303

Triple 8-Bit, 50 MSPS, Video A/D
Converter with Clamp Function

The HI2303 is a highly integrated 8-bit, 3-channel analog-to-
digital converter that is designed for component (like RGB)
digitizing applications. The internal DC Restore (video
clamp) function and voltage reference simplifies system
design and saves board space. The HI2303 can digitize
RGB, YUV, YIQ and any other analog component color
signals used in video systems. The variety of sub-sampling
modes is compatible with RGB, YUV and YIQ color systems
where 4:4:4, 4:2:2 and 4:1:1 data reduction is needed. The
2-step architecture boasts, low power operation, and
excellent video performance.

Features

· Resolution 8-Bit 1/2 LSB (DL)

· Low Power Consumption (at 50 MSPS Typ)

(Reference Current Excluded) . . . . . . . . . . . . . . . .500mW

· Synchronizing Digital Clamp Function

· Clamp ON/OFF Function

· Reference Voltage Self-Bias Circuit

· Input CMOS/TTL Compatible

· Three-State TTL Compatible Output

· Single 5V Power Supply or Dual 5V or 3.3V Power Supplies

· Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . .15pF

· Different Digital Output Multiplex Format

- 4:4:4

- 4:2:2

- 4:1:1

· Direct Replacement for Sony CXD2303

Applications

· Video Digitizing (Composite and Y-C)

· LCD Projectors

· LCD Panels

· RGB Graphics Processing

Pinout

HI2303 (MQFP)

TOP VIEW

Ordering Information

PART NUMBER

TEMP.

RANGE (

PACKAGE

PKG. NO.

HI2303JCQ

-40 to 85

80 Ld MQFP

Q80.14x20-S

HI2303EVAL

Evaluation Kit

2 1

26
27
28
29
30
31
32

A0 (LSB)

A7 (MSB)

TGR

CTL0

XCOE

XBOE

TEST

CTL1

CLE

REF3

REF2

REF1

CLP

CLK

SEL

CTL2

REF0

TEST

RBS

RTS

RBS

B0 (LSB)

B7 (MSB)

RTS

C0 (LSB)

C7 (MSB)

Data Sheet

December 1998

File Number

4106.2

Functional Block Diagram

A0 (LSB)

A7 (MSB)

XAOE

B0 (LSB)

B7 (MSB)

XBOE

C0 (LSB)

C7 (MSB)

XCOE

TGR

TEST

A-CH

8-BIT ADC

8-BIT

DAC

B-CH

8-BIT ADC

8-BIT

DAC

C-CH

8-BIT ADC

8-BIT

DAC

DIGITAL

CLAMP

CIRCUIT

DIGITAL

CLAMP

CIRCUIT

DIGITAL

CLAMP

CIRCUIT

DATA

SELECTOR

LATCH

DIGITAL CONTROL

DECODER

RBS

RTS

RBS

RTS

RBS

RTS

60 61 65

REF3

REF0

SEL

CLP

CLE

CLK

CTL0

CTL2

48 CTL1

HI2303

Pin Description

PIN NO.

SYMBOL

EQUIVALENT CIRCUIT

DESCRIPTION

1, 2, 22, 23

Digital Power Supply.
+5V or +3.3V.

13 to 20

3 to 10

73 to 80

A0 to A7
B0 to B7

C0 to C7

Digital output.
A0 (LSB) to A7 (MSB)
B0 (LSB) to B7 (MSB)
C0 (LSB) to C7 (MSB).

TGR

Trigger Output

11, 12, 71, 72

Digital Ground.

24, 27, 38, 60, 61,

Analog Ground.

25
40
63

ARBS
BRBS
CRBS

Shorting the RBS pins to AVSS
generates voltage of approxi-
mately 0.6V at the ARB, BRB and
CRB pins.

26
39
64

ARB
BRB
CRB

Reference Voltage (Bottom).

31
34
69

ART
BRT
CRT

Reference Voltage (Top).

32
33
70

ARTS
BRTS
CRTS

Shorting the RTS pins to AV

generates voltage of about 2.5V at
the ART, BRT and CRT pins.

28
37
66

AIN
BIN
CIN

Analog Input.

29
36
67

AIO
BIO
CIO

Analog Output. These pins are the
D/A

converter

outputs

which

comprise the digital clamp circuit.

REF

RTS

RBS

200

HI2303

30, 35, 41, 42, 62,

Analog +5V Power Supply.

43
59

TEST

Normally open. Pull-down
resistors are incorporated.

44
45
46

XAOE
XBOE

XCOE

Output Enable Input. When these
pins are Low, data is output from
the digital output pins. When these
pins are High, the digital output
pins are High impedance. The A, B
and C Channels can be controlled
separately. Also, these pins are not
synchronized with the clock signal.
Pull-down

resistors

are

incorporated.

47
48
49

CTL0
CTL1

CLT2

Determines

the

digital

output

mode. See the Mode tables and
Timing

Charts.

Pull-down

resistors are incorporated.

Controls the digital output mode
switching timing. The mode is
switched

detecting

the

transition point where this pin
changes from Low to High. See
the Mode Tables and Timing
Charts for details. A pull-down
resister is incorporated.

SEL

Controls the CLP signal polarity.
When this pin is Low, CLP is High
active.
When this pin is High, CLP is Low
active. This pin has a built-in pull-
down resistor.

CLK

Clock Input. A pull-down resistor is
incorporated.

CLP

Clamp Pulse Input. The polarity
can be set to either High or Low by
setting SEL. This pin has a built-in
pull-down resistor.

54
55
56
57

REF0
REF1
REF2
REF3

Determines

the

clamp

circuit

reference data. See the mode
tables for the set data. These pins
are not synchronized with the
clock

input

signal.

Pull-down

resistors are incorporated.

CLE

Clamp Enable. When this pin is Low
the clamp circuit does not operate.
When this pin is High, the clamp
circuit

operates.

pull-down

resistor is incorporated.

Pin Description

(Continued)

PIN NO.

SYMBOL

EQUIVALENT CIRCUIT

DESCRIPTION

HI2303

Absolute Maximum Ratings

= 25

Thermal Information

Supply Voltage (AV

, DV

) . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V

Input Voltage (V

, All Pins). . . . . . . . . . . . V

+0.5V to V

-0.5V

Output Voltage (V

, Digital) . . . . . . . . . . . . V

+0.5V to V

-0.5V

Operating Conditions

Supply Voltage:

, AV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.25V

, DV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0V to 5.5V

, AV

| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0mV to 100mV

Reference Input Voltage:

ARB

, V

BRB

, V

CRB

. . . . . . . . . . . . . . . . . . . . . . . . . . . 0V or More

ART

, V

BRT

, V

CRT

. . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V or Less

Analog Input:

, B

, C

. . . . . . . . . . . . . . . . . . . . . . . . . . . .1.7V

P-P

or More

Clock Pulse Width:
t

PW1

, t

PW0

. . . . . . . . . . . . . . . . . . . . . . . . . 9ns (Min) to 1.1ms (Max)

Ambient Temperature (TOPR) . . . . . . . . . . . . . . . . . . -40

C to 85

Thermal Resistance (Typical, Note 1)

(

C/W)

MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature (Plastic Package) . . . . . . . .150

Maximum Storage Temperature Range (T

STG

). . . . -65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

(Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

= 50 MSPS, AV

= 5V, DV

= 3.0V to 5.0V, V

= 0.5V, V

= 2.5V, T

= 25

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

ANALOG CHARACTERISTICS

= 3V to 5.5V

Conversion Rate

= 4.75V to 5.25V, T

= -20

C to 75

= 0.5V to 2.5V, f

= 1kHz Triangular Wave

0.5

MSPS

Analog Input Band (-1dB)

Envelope

-1dB

MHz

= 33

-3dB

100

MHz

Differential Non-Linearity Error

End Point

0.3

0.5

LSB

Integral Non-Linearity Error

0.7

1.5

LSB

Offset Voltage (Note 2)

Potential Difference to A

, B

, C

-50

-10

Potential Difference to A

, B

, C

Differential Gain Error

NTSC 40 IRE Mod Ramp, f

= 14.3 MSPS

Differential Phase Error

1.5

Deg

Cross Talk

= 1MHz Sinewave

Clamp Offset Voltage

= DC

= 10

PCW

= 2.75

CLK

= 14.3MHz

CLP

= 15.75kHz

Ref Data = 00010000

LSB

Ref Data = 10000000

LSB

Signal To Noise Ratio

SNR

= 150kHz

= 500kHz

= 1MHz

= 3MHz

= 10MHz

= 20MHz

HI2303

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HI2303EVAL1