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Электронный компонент: HI2315JCQ

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10-1
August 1997
HI2315
10-Bit, 80 MSPS D/A Converter
(Ultra-Low Glitch Version)
Features
Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . 80MHz
Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150mW
Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . +5V
Differential Linearity Error . . . . . . . . . . . . . . .
0.5 LSB
TTL/CMOS Compatible Inputs
Built in Bandgap Voltage Reference
Power Down and Blanking Control Pins
Low Glitch
Pin Compatible with Sony CXD2306
Direct Replacement for Sony CXD2315Q
Applications
Wireless Communications
Direct Digital Frequency Synthesis
Signal Reconstruction
Test Equipment
High Resolution Imaging and Graphics Systems
Description
The HI2315 is a 10-bit, 80MHz, high speed, low power CMOS
D/A converter. The converter incorporates a 10-bit input data
register with current outputs. The HI2315 includes a power
down feature that reduces power consumption and a blanking
control. The on-chip bandgap reference can be used to set the
output current range of the D/A.
Pinout
HI2315
(MQFP)
TOP VIEW
Ordering Information
PART
NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
HI2315JCQ
-20 to 75
32 Ld MQFP
Q32.7x7-S
NC
DV
SS
VB
DV
DD
NC
CE
BLK
CLK
AV
SS
NC
DV
SS
DV
DD
NC
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D8
D9 (MSB)
NC
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
IO
IO
VG
AV
DD
AV
DD
V
REF
S
REF
I
REF
File Number
4119.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
10-2
Functional Block Diagram
Pin Descriptions
PIN NO.
SYMBOL
EQUIVALENT CIRCUIT
DESCRIPTION
30 to 32
1 to 7
D0 to D9
Digital Input.
10
BLK
Blanking pin. No signal (0V output) at high and
output state at low.
14
VB
Connect a capacitor of approximately 0.1
F.
9
CLK
Clock pin.
30
31
32
1
2
3
4
5
6
7
28
10
13
15
27
9
14
11
18
20
21
17
19
22
23
25
24 IO
AV
SS
IO
VG
V
REF
I
REF
AV
DD
AV
DD
S
REF
BAND GAP
REFERENCE
BIAS VOLTAGE
GENERATOR
CURRENT CELLS
(FOR FULL SCALE)
CURRENT
CELLS
6 MSBs
CURRENT
CELLS
4 LSBs
DECODER
DECODER
GENERATOR
CLOCK
(LSB) D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DV
DD
BLK
DV
DD
DV
SS
DV
SS
CLK
VB
CE
LATCHES
+
-
30
7
TO
DV
DD
DV
SS
10
DV
DD
DV
SS
DV
SS
DV
DD
+
-
14
DV
DD
9
DV
SS
DV
DD
HI2315
10-3
15, 27
DV
SS
Digital GND.
25
AV
SS
Analog GND.
17
I
REF
Connect resistance "16R" which is 16 times output
resistance "R".
19
V
REF
Sets output full scale value.
22
VG
Connect a capacitor of approximately 0.1
F.
20, 21
AV
DD
Analog V
DD
.
24
IO
Current Output pin. Output can be retrieved by
connecting resistance. The standard is 200
.
23
IO
Inverted Current Output pin. Connect to GND
normally.
13, 28
DV
DD
Digital V
DD
.
11
CE
Chip Enable pin. No signal (0V output) at high makes
power consumption minimum.
18
S
REF
Independent Constant-Voltage Source Output pin
using band gap reference. Stable voltage
independent of the fluctuation for supply voltage can
be obtained by connecting to V
REF
. See Application
Circuit 2 for details.
Pin Descriptions
(Continued)
PIN NO.
SYMBOL
EQUIVALENT CIRCUIT
DESCRIPTION
17
19
22
AV
DD
AV
DD
AV
DD
AV
DD
AV
SS
AV
SS
AV
SS
+
-
23
AV
DD
AV
SS
AV
SS
AV
DD
24
DV
DD
11
DV
SS
AV
SS
AV
DD
18
HI2315
10-4
Absolute Maximum Ratings
T
A
= 25
o
C
Thermal Information
Supply Voltage (V
DD
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Input Voltage (V
IN
) . . . . . . . . . . . . . . . . . . .V
SS
-0.5V to V
DD
+ 0.5V
Output Voltage (I
OUT
). . . . . . . . . . . . . . . . . . . . . . . . . .0mA to 15mA
Operating Conditions
Supply Voltage
AV
DD
, AV
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0V
0.25V
DV
DD
, DV
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.0V
0.25V
Reference Input Voltage (V
REF
) . . . . . . . . . . . . . . . . . . .0.5V to 2.0V
Clock Pulse Width (t
PW1
, t
PW0
) . . . . . . . . . . . . . . . . . . 6.25ns (Min)
Temperature Range (T
OPR
) . . . . . . . . . . . . . . . . . . . . -20
o
C to 75
o
C
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
122
Maximum Junction Temperature (MQFP Package) . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(MQFP - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
T
A
= 25
o
C, f
CLK
= 80MHz, V
DD
= 5V, R = 200
, V
REF
= 2.0V, 16R = 3.3k
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
n
-
10
-
Bit
Maximum Conversion Rate
f
MAX
80
-
-
MHz
Linearity Error
EL
-1.5
-
1.5
LSB
Differential Linearity Error
ED
-0.5
-
0.5
LSB
Output Full-Scale Voltage
V
FS
1.8
1.94
2.0
V
Output Full-Scale Current
I
FS
9.0
9.7
10
mA
Output Off-Set Voltage
V
OS
-
-
1
mV
Output Impedance
-
300
-
k
Supply Current
I
DD
-
-
30
mA
Digital Input Current
High Level
I
IH
-
-
5
A
Low Level
I
IL
-5
-
-
A
Digital Input Voltage
High Level
V
IH
2.45
-
-
V
Low Level
V
IL
-
-
0.85
V
Accuracy Guarantee Output Voltage Range
V
OC
1.8
1.94
2.0
V
Setup Time
t
S
3.0
-
-
ns
Hold Time
t
H
3.0
-
-
ns
Rise Time
t
r
5.0
-
-
ns
Propagation Delay Time
t
PD
-
5
-
ns
Glitch Energy
GE
R
OUT
= 200
, 2V
P-P
-
-
30
pV/s
Differential Gain
DG
-
-
1.0
%
Differential Phase
DP
-
-
1.0
Degrees
S
REF
Output Voltage
S
REF
T
A
= 25
o
C
1.0
1.2
1.4
V
HI2315
10-5
Test Circuits
FIGURE 1. MAXIMUM CONVERSION RATE TEST CIRCUIT
FIGURE 2. DC CHARACTERISTICS TEST CIRCUIT
FIGURE 3. PROPAGATION DELAY TIME TEST CIRCUIT
FIGURE 4. SETUP HOLD TIME AND GLITCH ENERGY TEST CIRCUIT
14
0.1
200
11
10
9
7
31
30
23
22
19
17
0.1
AV
DD
5K
AV
SS
3.3K
2V
IO
VG
V
REF
I
REF
D0 (LSB)
D9 (MSB)
CLK
BLK
CE
VB
10-BIT
COUNTER
WITH
LATCH
CLK
80MHz (MAX)
SQUARE
WAVE
OSCILLOSCOPE
14
0.1
200
11
10
9
7
31
30
23
22
19
17
0.1
AV
DD
5K
AV
SS
3.3K
2V
IO
VG
V
REF
I
REF
D0 (LSB)
D9 (MSB)
CLK
BLK
CE
VB
CLK
80MHz
SQUARE
WAVE
DVM
CONTROLLER
14
0.1
200
11
10
9
7
31
30
23
22
19
0.1
AV
DD
5K
AV
SS
3.3K
2V
IO
VG
V
REF
I
REF
D0 (LSB)
D9 (MSB)
CLK
BLK
CE
VB
FREQUENCY
DEMULTIPLIER
CLK
10MHz (MAX)
SQUARE
WAVE
OSCILLOSCOPE
17
14
0.1
200
11
10
9
7
31
30
23
22
19
17
0.1
AV
DD
5K
AV
SS
3.3K
2V
IO
VG
V
REF
I
REF
D0 (LSB)
D9 (MSB)
CLK
BLK
CE
VB
10-BIT
COUNTER
WITH
LATCH
CLK
1MHz
SQUARE
WAVE
OSCILLOSCOPE
DELAY
CONTROLLER
DELAY
CONTROLLER
HI2315
10-6
Timing Diagram
t
PW1
t
PW0
t
S
t
S
t
S
t
H
t
H
t
H
t
PD
t
PD
t
PD
DATA
D/A OUT
100%
50%
0%
CLK
TABLE 1. I/O CORRESPONDENCE TABLE
(2.00V Output Full Scale Voltage)
INPUT CODE
OUTPUT VOLTAGE
MSB
LSB
1
1
1
1
1
1
1
1
1
1
2.0V
1
0
0
0
0
0
0
0
0
0
1.0V
0
0
0
0
0
0
0
0
0
0
0V
Typical Application Circuits
NOTE:
2. When 5.0V supply voltage (DV
DD
and AV
DD
). Digital input from pins 30 to 32 and pins 1 to 7. Pin 18 is Left Open When Using Normally.
R1 = 200
,
R2 = 3.3
(Resistance 16 Times R1), R3 = 3.0k
, R4 = 2.0k
,
C = 0.1
F.
FIGURE 5. APPLICATION CIRCUIT 1
17
18
19
20
21
22
23
24
8
7
6
5
4
3
2
1
16
15
14
13
12
11
10
9
25
26
27
28
29
30
31
32
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
NC
CLK
BLK
CE
NC
DV
DD
DV
SS
VB
I
REF
S
REF
V
REF
AV
DD
AV
SS
NC
DV
SS
AV
DD
AV
DD
AV
SS
IO
IO VG
CLOCK INPUT
C
C
C
C
DV
DD
DV
SS
NC
R1
R3
R4
R2
DV
DD
NC
HI2315
10-7
NOTE:
3. When 5.0V supply voltage (DV
DD
and AV
DD
). Digital input from pins 30 to 32 and pins 1 to 7. R1 = 200
,
R2 = 2.0k
, C = 0.1
F.
FIGURE 6. APPLICATION CIRCUIT 2
Typical Application Circuits
(Continued)
17
18
19
20
21
22
23
24
8
7
6
5
4
3
2
1
16
15
14
13
12
11
10
9
25
26
27
28
29
30
31
32
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
NC
CLK
BLK
CE
NC
DV
DD
DV
SS
VB
I
REF
S
REF
V
REF
AV
DD
AV
SS
NC
DV
SS
AV
DD
AV
DD
AV
SS
IO
IO VG
CLOCK INPUT
C
C
C
C
DV
DD
DV
SS
NC
R1
R2
DV
DD
NC
Typical Performance Curves
FIGURE 7. OUTPUT FULL SCALE VOLTAGE (V
FS
) vs
REFERENCE VOLTAGE (V
REF
)
FIGURE 8. OUTPUT FULL SCALE VOLTAGE vs AMBIENT
TEMPERATURE
2.0
1.0
2.0
1.0
OUTPUT FULL SCALE V
O
L
T
A
GE (V)
REFERENCE VOLTAGE (V)
-25
0
25
50
75
0
AMBIENT TEMPERATURE (
o
C)
1.93
1.95
OUTPUT FULL SCALE V
O
L
T
A
GE (V)
V = 0.2mV/
o
C
HI2315
10-8
GE (Glitch Energy)
GE, as described in the HI2315, is a spike noise which
appears synchronizing with the clock falling edge when the
input data (for 1 to 1024 input) changes to 128, 256, 384,
512, 640, 768, 896, and 1024. Figure 11 shows the change
state of GE for the staircase wave output, and Figure 12
shows the repetitive output waveform where the GE
appears. These figures exhibit the difference of this IC from
the convention device.
The HI2315 reduces the GE as shown in Figures 11 and 12.
FIGURE 9. S
REF
vs AMBIENT TEMPERATURE
FIGURE 10. OUTPUT FREQUENCY vs CURRENT CONSUMPTION
NOTE:
4. Standard Measurement Conditions and Description: V
DD
= 5.0V, V
REF
= 2.0V, R = 200
, 16R - 3.3k
, T
A
= 25
o
C. The temperature
characteristics of external input data in Figure 10 = all "0" and "1" of rectangular wave; clock frequency = 80MHz.
Typical Performance Curves
(Continued)
-25
0
25
50
75
0
AMBIENT TEMPERATURE (
o
C)
1.15
1.25
S
REF
OUTPUT V
O
L
T
A
GE (V)
V = 0.7mV/
o
C
1
10
20
30
40
0
OUTPUT FREQUENCY (MHz)
20
30
CURRENT CONSUMPTION (mA)
DIGITAL INPUT (V)
ANALOG OUTPUT (V)
0
512
1024
2.0
1.0
CLK
HI2315
CONVENTIONAL
DEVICE
FIGURE 11. CHANGE OF GE FOR STAIRCASE WAVE OUTPUT
HI2315
10-9
Notes On Operation
Selecting the Output Resistance
- HI2315 is a current output type D/A converter. To create
the output voltage, connect the resistor to the current
output pin.
Specifications:
Output full-scale voltage V
FS
(Max) = 2.0V
Output full-scale current I
FS
(Max) = 10mA
- Calculate the output resistance from V
FS
= I
FS
x R.
Connect a resistance sixteen times the output
resistance to the reference current pin I
REF
. In some
cases, as this value may not exist, a similar value can
be used instead.
Note that the V
FS
will be the following:
V
FS
= V
REF
x 16 R/R'.
- R is the resistor to be connected to the IO and R' is the
resistor to be connected to the I
REF
. Power consump-
tion can be reduced by increasing the resistance, but
this will on the contrary increase the glitch energy and
data settling time. Set the best values according to the
purpose of use.
Correlation between Data and Clock
- For the HI2315 to display the desired performance as a
D/A converter, the data transmitted form outside and the
clock must be synchronized properly. Adjust the setup
time (t
S
) and hold time (t
H
) as specified in "Electrical
Characteristics."
V
DD
, V
SS
- Separate the analog and digital signals around the
device to reduce noise effects. By-pass the V
DD
pin to
each GND with a 0.1
F ceramics capacitor as near to
the pin as possible for both the digital and analog
signals.
Latch up
- The AV
DD
and DV
DD
pins must be able to share the
same power supply of the board. This is prevent latch
up caused by potential difference between the two pins
when the power is turned on.
I
REF
pin
- The I
REF
pin is very sensitive to improve the AC
characteristics. Pay attention for capacitance
component not to attach to this pin because its output
may become unstable.
VG Pin
- It is recommended to use a 1
F capacitor to improve
the AC characteristics though the typical capacitance
value externally connected to the VG pin is 0.1
F.
S
REF
- The S
REF
is independent regulated current source. By
connecting it to the V
REF
, stable output amplitudes that
do not depend on fluctuations in the power supply can
be obtained.
- In this case, as V
FS
= S
REF
x 16R/R', set the V
FS
according to R'.
- Do not use this pin as a reference power supply for
other ICs because this is dedicated for the D/A
converter.
FIGURE 12. REPETITIVE OUTPUT WAVEFORM WHERE GE APPEARS (FOR 200
, 2V
P-P
OUTPUT)
HI5780 (GE TYP = 200pV/S)
HI2315 (GE TYP = 10pV/S)
HI2315
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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