4-1406
August 1997
HI3086
6-Bit, 140 MSPS, Flash A/D Converter
Features
Differential Linearity Error. . . . . . . . . . . . . . . . .
0.2 LSB
Integral Linearity Error . . . . . . . . . . . . . . . . . .
0.2 LSB
Single +5V Power Supply Operation Available
Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . 7pF
Wide Analog Input Bandwidth . . . . . . . . . . . . . 200MHz
Low Power Consumption . . . . . . . . . . . . . . . . . .360mW
CLK/2 Clock Output Pin
Excellent Temperature Characteristics
1:2 Demultiplexed Output
Internal
1
/
2
Frequency Divider Circuit
(With Reset Function)
Compatible with ECL, PECL and TTL Digital Input Levels
Direct Replacement for Sony CXA3086
Applications
RGB Graphics Processing (LCD, PDP)
Digital Communications (QPSK, QAM)
Magnetic Recording (PRML)
Description
The HI3086 is a 6-bit, high-speed, flash analog-to-digital con-
verter optimized for high speed, low power, and ease of use.
With a 140 MSPS encode rate capability and full-power analog
bandwidth of 200MHz, this component is ideal for applications
requiring the highest possible dynamic performance.
To minimize system cost and power dissipation, only a +5V
power supply is required. The HI3086's clock input interfaces
directly to TTL, ECL, or PECL logic and will operate with single-
ended inputs. The user may select 16-bit demultiplexed output
or 8-bit single-channel digital outputs. The demultiplexed mode
interleaves the data through two 8-bit channels at
1
/
2
the clock
rate. Operation in demultiplexed mode reduces the speed and
cost of external digital interfaces, while allowing the A/D
converter to be clocked to the full 140 MSPS conversion rate.
Fabricated with an advanced bipolar process, the HI3086 is
provided in a space-saving 48-lead MQFP surface mount
plastic package and is specified over the -20
o
C to 75
o
C
temperature range.
Pinout
HI3086 (MQFP)
TOP VIEW
Ordering Information
PART
NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
HI3086JCQ
-20 to 75
48 Ld MQFP
Q48.12x12-S
HI3086EVAL
25
Evaluation Board
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
9
10
11
12
13 14 15 16
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
DGND2
P1D5 (MSB)
P1D4
P1D3
P1D2
P1D1
P1D0 (LSB)
DGND2
DV
CC2
CLK/T
CLKN/E
CLK/E
DGND2
P2D0 (LSB)
P2D1
P2D2
P2D3
DGND2
DV
CC2
RESETN/T
RESET/E
RESETN/E
P2D4
P2D5 (MSB)
DV
CC2
DV
CC1
DGND1
NC
PS
INV
SELECT
NC
DGND1
DV
CC1
DV
CC2
CLK
OUT
DV
EE3
A
GND
V
RBS
V
RB
AV
CC
NC
V
IN
AV
CC
V
RT
V
RT
S
A
GND
DGND3
File Number
4110.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
4-1408
Pin Descriptions
PIN
NO.
SYMBOL
I/O
TYPICAL
VOLTAGE
LEVEL
EQUIVALENT CIRCUIT
DESCRIPTION
14, 23
AGND
GND
Analog Ground. Separated from
the digital ground.
17, 20
AV
CC
+5V (Typ)
Analog Power Supply. Separated
from the digital power supply.
1, 8, 29,
36, 39,
46
DGND1
DGND2
GND
Digital Ground.
9, 28,
37, 38,
47, 48
DV
CC1
DV
CC2
+5V (Typ)
Digital Power Supply.
24
DGND3
+5V (Typ) (With a
Single Power
Supply)
Digital Power Supply. Ground for
ECL input. +5V for PECL and TTL
input.
GND (With Dual
Power Supplies)
13
D
VEE3
GND (With a
Single Power
Supply)
Digital Power Supply. Ground for
ECL input. -5V for PECL and TTL
input.
-5V (Typ) (With
Dual Power
Supplies)
18, 40,
45
NC
No Connect pin. Not connected
with the internal circuits.
25
CLK/E
I
ECL/PECL
Clock input.
26
CLKN/E
I
CLK/E Complementary Input. When
left open, this pin goes to the thresh-
old potential. Only CLK/E can be
used for operation, but complemen-
tary input is recommended to attain
fast and stable operation.
12
RESETN/E
I
Reset Input. When the input is set to
low level, the built-in CLK frequency
divider circuit can be reset.
11
RESET/E
I
RESETN/E Complementary Input.
When left open, this pin goes to the
threshold voltage. Only RESETN/E
can be used for operation.
12 25
26
11
DGND3
DV
EE3
1.2V
R
R
R
R
HI3086
4-1409
27
CLK/T
I
TTL
Clock Input.
10
RESETN/T
I
Reset Input. When left open, this
input goes to high level. When the
input is set to low level, the built-in
CLK frequency divider circuit can
be reset.
42
INV
I
TTL
Data Output Polarity Inversion Input.
When left open, this input goes to
high level. (See Table 1; I/O
Correspondence Table).
44
PS
I
TTL
Power Saving Input. When the input
is set to low level, the power saving
mode is set. In this time the all TTL
ouputs go into the high impedance
state. Normally, set to high level or
left open.
41
SELECT
V
CC
or GND
Data Output Mode Selection. (See
Table 2, Operating Mode Table).
Pin Descriptions
(Continued)
PIN
NO.
SYMBOL
I/O
TYPICAL
VOLTAGE
LEVEL
EQUIVALENT CIRCUIT
DESCRIPTION
27
10
D
VCC1
1.5V
R
R/2
DGND1
DV
EE3
44
D
VCC1
DGND1
D
VEE3
42
41
D
VCC1
DGND1
D
VEE3
HI3086
4-1410
22
V
RTS
O
+4.0V (Typ)
Reference Voltage Sense. Bypass
to AGND with a 0.1
F chip
capacitor.
21
V
RT
I
V
RTS
+ R1 x I
REF
Top Reference Voltage. Bypass to
AGND with a 1
F tantal capacitor
and 0.1
F chip capacitor.
16
V
RB
I
V
RBS
-R2 x I
REF
Bottom Reference Voltage. Bypass
to AGND with a 1
F tantal capacitor
and a 0.1
F chip capacitor.
15
V
RBS
O
+2.0V (Typ)
Reference Voltage Sense. Bypass
to AGND with a 0.1
F chip
capacitor.
19
V
IN
I
V
RT
to V
RB
Analog Input.
30 to 35
P1D0 to P1D5
O
TTL
Port 1 Side Data Output.
2 to 7
P2D0 to P2D5
O
Port 2 Side Data Output.
43
CLKOUT
O
Clock Output. (See Table 2.
Operating Mode Table.)
Pin Descriptions
(Continued)
PIN
NO.
SYMBOL
I/O
TYPICAL
VOLTAGE
LEVEL
EQUIVALENT CIRCUIT
DESCRIPTION
21
15
R2
R
R
R
R
R
R
R1
COMPARATOR 1
COMPARATOR 2
COMPARATOR 62
COMPARATOR 63
22
16
R
R
19
AV
CC
DV
EE3
COMPARATOR
AV
CC
AGND
V
REF
2
30
43
35
7
DV
CC2
TO
TO
DGND2
DV
EE3
DGND1
DV
CC1
100K
HI3086
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