4-1424
August 1997
HI3304
4-Bit, 25 MSPS, Flash A/D Converter
Features
CMOS Low Power (Typ). . . . . . . . . . . . . . . . . . . . 35mW
Parallel Conversion Technique
Single Power Supply Voltage . . . . . . . . . . . . 3V to 7.5V
Sampling Rate at 5V Supply . . . . . . . . . . . . . . . . . 25MHz
4-Bit Latched Three-State Output with Overflow and
Data Change Outputs
Maximum Nonlinearity. . . . . . . . . . . . . . . . . . . .
1
/
8
LSB
Inherent Resistance to Latch-Up
Bipolar Input Range with Optional Second Supply
Input Bandwidth (Typ) . . . . . . . . . . . . . . . . . . . . . 40MHz
Linearity (INL, DNL):
- HI3304JIP . . . . . . . . . . . . . . . . . . . . . . . . . .
0.25 LSB
- HI3304JIB . . . . . . . . . . . . . . . . . . . . . . . . . .
0.25 LSB
Sampling Rate:
- HI3304JIP . . . . . . . . . . . . . . . . . . . . . . . 25MHz (40ns)
- HI3304JIB . . . . . . . . . . . . . . . . . . . . . . . 25MHz (40ns)
Applications
Video Digitizing
High Speed Data Acquisition
Digital Communication Systems
Radar Signal Processing
Description
The Intersil HI3304 is a CMOS parallel (FLASH) analog-to-
digital converter designed for applications demanding both
low-power consumption and high speed digitization. Digitiz-
ing at 25MHz, for example, requires only about 35mW.
The HI3304 operates over a wide, full-scale signal input volt-
age range of 0.5V up to the supply voltage. Power consump-
tion is as low as 10mW, depending upon the clock frequency
selected.
Sixteen paralleled auto-balanced voltage comparators mea-
sure the input voltage with respect to a known reference to
produce the parallel-bit outputs in the HI3304. Fifteen com-
parators are required to quantize all input voltage levels in
this 4-bit converter, and the additional comparator is required
for the overflow bit. A data change pin indicates when the
present output differs from the previous, thus allowing com-
paction of data storage.
Pinout
HI3304
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
HI3304JIP
-40 to 85
16 Ld PDIP
E16.3
HI3304JIB
-40 to 85
16 Ld SOIC
M16.3
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
BIT 1 (LSB)
BIT 2
BIT 3
BIT 4
DATA CHANGE (DC)
OVERFLOW (OF)
V
SS
CE2
V
DD
V
AA
-
V
REF
-
V
REF
+
V
IN
V
AA
+
CE1
CLK
File Number
4137.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
4-1425
Functional Block Diagram
Cascaded Auto Balance (CAB)
NOTE:
CE1 and CE2 inputs and data outputs have standard CMOS protection networks to V
DD
and V
SS
. Analog inputs and clock have
standard CMOS protection networks to V
AA
+ and V
AA
-.
9
7
1
D Q
CLK
D Q
CLK
D Q
CLK
D Q
CLK
D Q
CLK
D Q
CLK
5
2
3
4
6
ENCODER
LOGIC
ARRAY
D
LATCH
16
Q
COUNT
16
COUNT
8
D
LATCH
8
Q
D
LATCH
0
Q
COUNT
1
8
14
V
AA
-
V
SS
CAB COMPARATOR #1
1 (AUTO BALANCE)
2 (SAMPLE UNKNOWN)
50k
CLOCK
15
13
V
REF
-
V
REF
+
V
IN
11
16
10
V
AA
+
V
DD
1
1
1
1
2
2
1
/
2
R
1
/
2
R
R
R
R
CAB #8
CAB #16
OUTPUT
REGISTER
THREE-STATE
DRIVERS
DATA
CHANGE
OVERFLOW
BIT 4
BIT 3
BIT 2
BIT 1 (LSB)
CE1
CE2
R
12
HI3304
HI3304
4-1426
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range (V
DD
or V
AA
+)
(Voltage Referenced to V
SS
or V
AA
- Terminal,
Whichever is More Negative) . . . . . . . . . . . . . . . . . . -0.5V to +8V
Input Voltage Range
CE1, CE2 Inputs . . . . . . . . . . . . . . . . . . . V
SS
-0.5V to V
DD
+0.5V
Clock, V
REF
+, V
REF
-, V
IN
Inputs . . . . . . V
AA
-0.5V to V
AA
+0.5V
DC Input Current, Any Input . . . . . . . . . . . . . . . . . . . . . . . . .
20mA
Operating Conditions
Supply Voltage Range (V
DD
or V
AA
+) . . . . . . . . . . . . . . . . . .3V to 7.5V
V
AA
+ Voltage Range . . . . . . . . . . . . . . . . . . V
DD
-1V to V
DD
+2.5V
V
AA
- Voltage Range . . . . . . . . . . . . . . . . . . . . V
SS
-2.5V to V
SS
+1V
Operating Temperature Range . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range (T
STG
) . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
T
A
= 25
o
C, V
REF
+ = 2V, V
DD
= V
AA
+ = 5V, V
AA
- = V
REF
- = V
SS
= GND, f
CLK
= 25MHz
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM PERFORMANCE
Resolution
4
-
-
Bits
Input Errors
Integral Linearity Error
-
0.125
0.25
LSB
Differential Linearity Error
-
0.125
0.25
LSB
Offset Error (Unadjusted)
-
-
1.0
LSB
Gain Error (Unadjusted)
-
-
1.0
LSB
DYNAMIC CHARACTERISTICS Input Signal Level 0.5dB Below Full Scale
Conversion Timing
Aperture Delay
-
3
-
ns
Signal to Noise Ratio (SNR)
f
S
= 25MHz, f
IN
= 100kHz
-
23.7
-
dB
f
S
= 25MHz, f
IN
= 5MHz
-
23.6
-
dB
Signal to Noise Ratio (SINAD)
f
S
= 25MHz, f
IN
= 100kHz
-
23.4
-
dB
f
S
= 25MHz, f
IN
= 5MHz
-
22.8
-
dB
Total Harmonic Distortion, THD
f
S
= 25MHz, f
IN
= 100kHz
-
-34.5
-
dBc
f
S
= 25MHz, f
IN
= 5MHz
-
-31.0
-
dBc
Effective Number of Bits, ENOB
f
S
= 25MHz, f
IN
= 100kHz
-
3.67
-
Bits
f
S
= 25MHz, f
IN
= 5MHz
-
3.57
-
Bits
ANALOG INPUTS
Input Range
Full Scale Input Range
(Notes 1, 4)
0.5
-
V
AA
V
Input Loading
Input Capacitance
-
10
-
pF
Input Current
V
IN
= 2V (Note 2)
-
150
200
A
-3dB Input Bandwidth
-
40
-
MHz
=
RMS Signal
RMS Noise
----------------------------------
=
RMS Signal
RMSNoise + Distortion
----------------------------------------------------------------
HI3304
HI3304
4-1427
REFERENCE INPUTS
Input Range
V
REF
+ Range
(Note 4)
V
AA
- +0.5
-
V
AA
+
V
V
REF
- Range
(Note 4)
V
AA
-
-
V
AA
+ -0.5
V
Input Loading
Resistor Ladder Impedance
V
IN
= 5V, CLK = Low
640
-
960
DIGITAL INPUTS
Digital Input
Maximum V
IN
, Low
CLOCK
(Notes 3, 4)
-
-
0.3 x V
AA
V
CE1, CE2
(Note 4)
-
-
0.3 x V
DD
V
Minimum V
IN
, High
CLOCK
(Notes 3, 4)
0.7 x V
AA
-
-
V
CE1, CE2
(Note 4)
0.7 x V
DD
-
-
V
Input Leakage, Except CLK
V = 0V, 5V
-
-
1
A
Input Leakage, CLK
(Note 3)
-
100
150
A
DIGITAL OUTPUTS
Digital Outputs
Output Low (Sink) Current
V
O
= 0.4V
6
-
-
mA
Output High (Source) Current
V
O
= 4.6V
-3
-
-
mA
Three-State Leakage Current
V
O
= 0V, 5V
-
0.2
5
A
TIMING CHARACTERISTICS
Conversion Timing
Maximum Conversion Speed
CLK = Square Wave
25
35
-
MSPS
Auto-Balance Time (
1)
20
-
-
ns
Sample Time (
2)
20
-
5000
ns
Output Timing
Data Valid Delay
(Note 4)
-
30
40
ns
Data Hold Time
(Note 4)
15
25
-
ns
Output Enable Time
-
15
-
ns
Output Disable Time
-
10
-
ns
POWER SUPPLY CHARACTERISTICS
Device Current, I
AA
Continuous Clock
-
5.5
-
mA
Continuous
2
-
0.4
-
mA
Continuous
1
-
2
-
mA
Device Current, I
DD
Continuous Clock
-
1.5
-
mA
V
AA
+ = 5V,
V
SS
= CE1 = V
AA
- = CLK = GND
Continuous
2
-
5
10
mA
V
AA
+ = 7V
Continuous
1
-
5
20
mA
NOTES:
1. Full scale input range, V
REF
+ - V
REF
-, may be in the range of 0.5V to V
AA
+ -V
AA
- volts. Linearity errors increase at lower full scale ranges,
however.
2. Input current is due to energy transferred to the input at the start of the sample period. The average value is dependent on input and VDD
voltage.
3. The CLK input is a CMOS inverter with a 50k
feedback resistor. It operates from the V
AA
+ and V
AA
- supplies. It may be AC-coupled
with a 1V
P-P
minimum source.
4. Parameter not tested, but guaranteed by design or characterization.
Electrical Specifications
T
A
= 25
o
C, V
REF
+ = 2V, V
DD
= V
AA
+ = 5V, V
AA
- = V
REF
- = V
SS
= GND, f
CLK
= 25MHz
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HI3304
HI3304
4-1428
HI3304
Timing Diagrams
FIGURE 1. TIMING DIAGRAM
FIGURE 2. OUTPUT ENABLE/DISABLE TIMING
FIGURE 3A.
With
2 as standby state (fastest method, but standby limited to 5
s
maximum)
FIGURE 3B.
With
1 as standby state (indefinite standby, double pulse needed)
FIGURE 3C.
With
2 as standby state (indefinite standby, lower power than 3B)
FIGURE 3. PULSE-MODE TIMING DIAGRAMS
CLOCK
B1 - B4, DC AND OF
COMPARATOR DATA
DATA VALID 2
1
2
t
HO
1
1
0
0
AUTO
BALANCE
AUTO
BALANCE
AUTO
BALANCE
SAMPLE 1
SAMPLE 2
SAMPLE 3
LATCHED
DATA SHIFTED INTO
OUTPUT REGISTERS
DATA VALID 1
DATA VALID 0
t
D
BITS 1-4
DC, OF
t
DIS
HIGH
CE2
CE1
IMPEDANCE
HIGH
IMPEDANCE
HIGH
IMPEDANCE
t
EN
t
EN
t
DIS
CLOCK
OUTPUT
SAMPLE ENDS
OLD DATA
NEW DATA
2
1
2
t
D
CLOCK
OUTPUT
SAMPLE ENDS
OLD DATA
NEW DATA
2
1
2
t
D
OLD DATA + 1
1
1
CLOCK
OUTPUT
SAMPLE ENDS
OLD DATA
NEW DATA
1
2
1
t
D
INVALID DATA
2
2
HI3304
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