1
FN4607.3
HS-565BRH
Radiation Hardened High Speed,
Monolithic Digital-to-Analog Converter
The HS-565BRH is a fast, radiation hardened 12-bit current
output, digital-to-analog converter. This part replaces the
HS-565ARH, which is no longer available. The monolithic
chip includes a precision voltage reference, thin-film R-2R
ladder, reference control amplifier and twelve high-speed
bipolar current switches.
The Intersil Corporation Dielectric Isolation process provides
latch-up free operation while minimizing stray capacitance
and leakage currents, to produce an excellent combination
of speed and accuracy. Also, ground currents are minimized
to produce a low and constant current through the ground
terminal, which reduces error due to code-dependent ground
currents.
HS-565BRH die are laser trimmed for a maximum integral
nonlinearity error of
0.25 LSB at 25
o
C. In addition, the low
noise buried zener reference is trimmed both for absolute
value and minimum temperature coefficient.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-96755. A "hot-link" is provided
on our website for downloading.
Features
Electrically Screened to SMD # 5962-96755
QML Qualified per MIL-PRF-38535 Requirements
Total Dose . . . . . . . . . . . . . . . . . . . . . 100 krad (Si) (Max)
DAC and Reference on a Single Chip
Pin Compatible with AD-565A and HI-565A
Very High Speed: Settles to 0.50 LSB in 500ns Max
Monotonicity Guaranteed Over Temperature
0.50 LSB Max Nonlinearity Guaranteed Over Temperature
Low Gain Drift
(Max., DAC Plus Reference) . . . . . . . . . . . . . . .50ppm/
o
C
0.75 LSB Accuracy Guaranteed Over Temperature
(
0.125 LSB Typical at 25
o
C)
Applications
High Speed A/D Converters
Precision Instrumentation
Signal Reconstruction
Functional Diagram
Ordering Information
ORDERING NUMBER
INTERNAL
MKT. NUMBER
TEMP. RANGE
(
o
C)
5962R9675502V9A
HS0-565BRH-Q
25
5962R9675502VJC
HS1-565BRH-Q
-55 to 125
5962R9675502VXC
HS9-565BRH-Q
-55 to 125
HS9-565BRH/PROTO
HS9-565BRH/PROTO
-55 to 125
REF OUT VCC
4
3
+
-
19.95K
REF
10V
6
5
REF
+
-
3.5K
3K
IREF
0.5mA
-VEE PWR
GND
7
12
24 . . . 13
MSB LSB
(4X IREF
X CODE)
GND
IN
20V
SPAN
10V
SPAN
OUT
IO
DAC
9.95K
BIP.
OFF.
8
5K
5K
2.5K
11
10
9
Data Sheet
January 2003
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
Pinouts
HS1-565BRH
MIL-STD-1835 CDIP2-T24
(SBDIP)
TOP VIEW
HS9-565BRH
MIL-STD-1835 CDFP4-F24
(CERAMIC FLATPACK)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
21
22
23
24
15
14
13
NC
NC
VCC
REF OUT
REF GND
REF IN
-VEE
BIPOLAR RIN
IDAC OUT
10V SPAN
20V SPAN
PWR GND
BIT 1 IN (MSB)
BIT 3 IN
BIT 4 IN
BIT 5 IN
BIT 6 IN
BIT 8 IN
BIT 10 IN
BIT 11 IN
BIT 12 IN (LSB)
BIT 2 IN
BIT 7 IN
BIT 9 IN
24
23
22
21
20
19
18
17
16
15
14
13
2
3
4
5
6
7
8
9
10
11
12
1
NC
NC
VCC
REF OUT
REF GND
REF IN
-VEE
BIPOLAR RIN
IDAC OUT
10V SPAN
20V SPAN
PWR GND
BIT 1 IN
BIT 3 IN
BIT 4 IN
BIT 5 IN
BIT 6 IN
BIT 8 IN
BIT 10 IN
BIT 11 IN
BIT 12 IN
BIT 2 IN
BIT 7 IN
BIT 9 IN
(LSB)
(MSB)
HS-565BRH
3
Burn-In Bias Circuit
NOTES:
D1 = D2 = D3 = IN4002 or Equivalent
F0 to F11:
VIH = 5.0V
0.5V
VIL = 0.0V
0.5V
F0 = 100kHz
10% (50% Duty Cycle)
F1 = F0/2
F7 = F0/128
F2 = F0/4
F8 = F0/256
F3 = F0/8
F9 = F0/512
F4 = F0/16
F10 = F0/1024
F5 = F0/32
F11 = F0/2048
F6 = F0/64
Radiation Bias Circuit
NOTE: Power Supply Levels are 0.5V
Definitions of Specifications
Digital Inputs
The HS-565BRH accepts digital input codes in binary format
and may be user connected for any one of three binary
codes. Straight binary, Two's Complement (see note below),
or Offset Binary, (See Operating Instructions).
Accuracy
Nonlinearity - Nonlinearity of a D/A converter is an
important measure of its accuracy. It describes the deviation
from an ideal straight line transfer curve drawn between zero
(all bits OFF) and full scale (all bits ON).
Differential Nonlinearity - For a D/A converter, it is the
difference between the actual output voltage change and the
ideal (1 LSB) voltage change for a one bit change in code. A
Differential Nonlinearity of
1 LSB or less guarantees
monotonicity; i.e., the output always increases and never
decreases for an increasing input.
Settling Time
Settling time is the time required for the output to settle to
within the specified error band for any input code transition.
It is usually specified for a full scale or major carry transition,
settling to within 0.50
LSB of final value.
Drift
Gain Drift - The change in full scale analog output over the
specified temperature range expressed in parts per million of
full scale range per
o
C (ppm of FSR/
o
C). Gain error is
measured with respect to 25
o
C at high (TH) and low (TL)
temperatures. Gain drift is calculated for both high (TH -
25
o
C) and low ranges (25
o
C - TL) by dividing the gain error by
the respective change in temperature. The specification is the
larger of the two representing worst case drift.
Offset Drift - The change in analog output with all bits OFF
over the specified temperature range expressed in parts per
million of full scale range per
o
C (ppm of FSR/
o
C). Offset
error is measured with respect to 25
o
C at high (TH) and low
(TL) temperatures. Offset drift is calculated for both high (TH
- 25
o
C) and low (25
o
C - TL) ranges by dividing the offset
error by the respective change in temperature. The
specification given is the larger of the two, representing
worst case drift.
C3
D3
+10V
1
4
5
8
9
10
11
12
16
17
18
19
20
21
22
23
24
15
14
13
2
3
6
7
NC
C1
D1
+15V
C2
D2
-15V
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
NC
VCC
REF GND
REF OUT
REF IN
-VEE
BIP OFF
OUT
10V SPAN
20V SPAN
PWR GND
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
+15V
1
4
5
8
9
10
11
12
16
17
18
19
20
21
22
23
24
15
14
13
2
3
6
7
NC
NC
VCC
REF GND
REF OUT
REF IN
-VEE
BIP OFF
OUT
10V SPAN
20V SPAN
PWR GND
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
-15V
+10V
+5V
DIGITAL
INPUT
ANALOG OUTPUT
STRAIGHT
BINARY
OFFSET
BINARY
(NOTE)
TWO'S
COMPLEMENT
MSB...LSB
000.... 000
Zero
-FS (Full Scale)
Zero
100.... 000
0.50
FS
Zero
-FS
111.... 111
+FS - 1LSB
+FS - 1LSB
Zero - 1LSB
011.... 111
0.50
FS - 1LSB
Zero - 1LSB
+FS - 1LSB
NOTE: Invert MSB with external inverter to obtain Two's
Complement Coding
HS-565BRH
4
Power Supply Sensitivity
Power Supply Sensitivity is a measure of the change in gain
and offset of the D/A converter resulting from a change in -
15V or +15V supplies. It is specified under DC conditions
and expressed as parts per million of full scale range per
percent of change in power supply (ppm of FSR/%).
Compliance
Compliance Voltage is the maximum output voltage range
that can be tolerated and still maintain its specified accuracy.
Compliance Limit implies functional operation only and
makes no claims to accuracy.
Glitch
A glitch on the output of a D/A converter is a transient spike
resulting from unequal internal ON-OFF switching times.
Worst case glitches usually occur at half scale or the major
carry code transition from 011 . . . 1 to 100 . . . 0 or vice
versa. For example, if turn ON is greater than turn OFF for
011 . . . 1 to 100 . . . 0, an intermediate state of 000 . . . 0
exists, such that, the output momentarily glitches toward
zero output. Matched switching times and fast switching will
reduce glitches considerably.
Applying the HS-565BRH
OP AMP Selection
The HS-565BRH's current output may be converted to
voltage using the standard connections shown in Figures 1
and 2. The choice of operational amplifier should be
reviewed for each application, since a significant trade-off
may be made between speed and accuracy. Remember
settling time for the DAC-amplifier combination is
where t
D
, t
A
are settling times for the DAC and amplifier.
No Trim Operation
The HS-565BRH will perform as specified without calibration
adjustments. To operate without calibration, substitute 50
resistors for the 100
trimming potentiometers: In Figure 1
replace R2 with 50
; also remove the network on pin 8 and
connect 50
to ground. For bipolar operation in Figure 2,
replace R3 and R4 with 50
resistors.
With these changes, performance is guaranteed as shown
under Specifications, "External Adjustments". Typical
unipolar zero will be
0.50
LSB plus the op amp offset.
The feedback capacitor C must be selected to minimize
settling time.
Calibration
Calibration provides the maximum accuracy from a
converter by adjusting its gain and offset errors to zero, For
the HS-565BRH, these adjustments are similar whether the
current output is used, or whether an external op amp is
added to convert this current to a voltage. Refer to Table 7
for the voltage output case, along with Figure 1 or 2.
Calibration is a two step process for each of the five output
ranges shown in Table 7. First adjust the negative full scale
(zero for unipolar ranges). This is an offset adjust which
translates the output characteristic, i.e. affects each code by
the same amount.
Next adjust positive FS. This is a gain error adjustment, which
rotates the output characteristic about the negative FS value.
For the bipolar ranges, this approach leaves an error at the
zero code, whose maximum values is the same as for
integral nonlinearity error. In general, only two values of
output may be calibrated exactly; all others must tolerate
some error. Choosing the extreme end points (plus and
minus full scale) minimizes this distributed error for all other
codes.
tD
(
)
2
tA
( )
2
+
VO
-
+
R (SEE
TABLE 7)
DAC
OUT
9
10
11
20V SPAN
10V SPAN
2.5K
5K
5K
C
9.95K
IO
24
13
MSB
LSB
. . . . .
CODE
INPUT
DAC
(4 x IREF
-VEE
PWR
GND
7
x CODE)
IREF
0.5mA
HS-565BRH
3K
3.5K
19.95
K
+
-
10V
3
4
VCC
+
-
6
5
REF
GND
REF
IN
REF OUT
R2
100
8
BIP.
OFF.
+15V
-15V
R1
50k
100k
100
FIGURE 1. UNIPOLAR VOLTAGE OUTPUT
VO
-
+
R (SEE
TABLE 7)
DAC
OUT
9
10
11
20V SPAN
10V SPAN
2.5K
5K
5K
C
9.95K
IO
24
13
MSB
LSB
. . . . .
CODE
INPUT
DAC
(4 x IREF
-VEE
PWR
GND
7
x CODE)
IREF
0.5mA
HS-565BRH
3K
3.5K
19.95K
+
-
10V
3
4
VCC
+
-
6
5
REF
GND
REF
IN
REF OUT
R4
100
8
BIP.
OFF.
R3
100
FIGURE 2. BIPOLAR VOLTAGE OUTPUT
HS-565BRH
5
Settling Time
This is a challenging measurement, in which the result
depends on the method chosen, the precision and quality of
test equipment and the operating configuration of the DAC
(test conditions). As a result, the different techniques in use
by converter manufacturers can lead to consistently different
results. An engineer should understand the advantage and
limitations of a given test methods before using the specified
settling time as a basis for design.
The approach used for several years at Intersil calls for a
strobed comparator to sense final perturbations of the DAC
output waveform. This gives the LSB a reasonable
magnitude (814mV for the HS-565BRH, which provides the
comparator with enough overdrive to establish an accurate
0.50
LSB window about the final settled value. Also, the
required test conditions simulate the DACs environment for
a common application - use in a successive approximation
A/D converter. Considerable experience has shown this to
be a reliable and repeatable way to measure settling time.
The usual specification is based on a 10V step, produced by
simultaneously switching all bits from off-to-on (tON) or on-
to-off (tOFF). The slower of the two cases is specified, as
measured from 50% of the digital input transition to the final
entry within a window of 0.50 LSB about the settled value.
Four measurements characterize a given type of DAC:
(Cases (b) and (c) may be eliminated unless the overshoot
exceeds 0.50
LSB). For example, refer to Figures 3A and 3B
for the measurement of case (d).
Procedure
As shown in Figure 3B, settling time equals tX plus the
comparator delay (tD = 15ns). To measure tX,
Adjust the delay on generator number 2 for a tX of several
microseconds. This assures that the DAC output has
settled to its final wave.
Switch on the LSB (+5V)
Adjust the VLSB supply for 50% triggering at
COMPARATOR OUT. This is indicated by traces of equal
brightness on the oscilloscope display as shown in Figure
3B. Note DVM reading.
Switch to LSB to Pulse (P)
Readjust the VLSB supply for 50% triggering as before,
and note DVM reading. One LSB equals one tenth the
difference in the DVM readings noted above.
Adjust the VLSB supply to reduce the DVM reading by 5
LSBs (DVM reads 10X, so this sets the comparator to
sense the final settled value minus 0.50 LSB). Comparator
output disappears.
Reduce generator number 2 delay until comparator output
reappears, and adjust for "equal brightness".
Measure tX from scope as shown in Figure 3B. Settling
time equals tX + tD, i.e. tX + 15ns.
(a) tON, to final value +0.50
LSB
(b) tON, to final value -0.50 LSB
(c) tOFF, to final value +0.50
LSB
(d) OFF, to final value -0.50
LSB
TABLE 1. OPERATING MODES AND CALIBRATION
MODE
CIRCUIT CONNECTIONS
CALIBRATION
OUTPUT
RANGE
PIN 10
TO
PIN 11
TO
RESISTOR
(R)
APPLY
INPUT CODE
ADJUST
TO SET VO
Unipolar (See Figure 1)
0 to +10V
VO
Pin 10
1.43K
All 0's
All 1's
R1
R2
0V
+9.99756V
0 to +5V
VO
Pin 9
1.1K
All 0's
All 1's
R1
R2
0V
+4.99878V
Bipolar (See Figure 2)
10V
NC
VO
1.69K
All 0's
All 1's
R3
R4
-10V
+9.99512V
5V
VO
Pin 10
1.43K
All 0's
All 1's
R3
R4
-5V
+4.99756V
2.5V
VO
Pin 9
1.1K
All 0's
All 1's
R3
R4
-2.5V
+2.49878V
HS-565BRH
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