ChipFind - документация

Электронный компонент: HS1-82C55ARH-Q

Скачать:  PDF   ZIP
970
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
HS-82C55ARH
Radiation Hardened
CMOS Programmable Peripheral Interface
Pinout
40 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T40
TOP VIEW
Pin Description
PIN
DESCRIPTION
D7 - D0
Data Bus (Bi-Directional
RESET
Reset Input
CS
Chip Select
RD
Read Input
WR
Write Input
A0 - A1
Port Address
PA7 - PA0
Port A (Bit)
PB& - PB0
Port B (Bit)
PC7 - PC0
Port C (Bit)
VDD
+5 volts
GND
0 volts
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
PA3
PA2
PA1
PA0
RD
CS
GND
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
PB0
PB1
PB2
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
PA4
PA5
PA6
PA7
WR
RESET
D0
D1
D2
D3
D4
D5
D6
D7
VDD
PB7
PB6
PB5
PB4
PB3
Features
Radiation Hardened
- Total Dose >10
5
RAD (Si)
- Transient Upset <10
8
RAD (Si)/s
- Latch Up Free EPI-CMOS
Low Power Consumption
- IDDSB = 20
A
Pin Compatible with NMOS 8255A and the Intersil 82C55A
High Speed, No "Wait State" Operation with 5MHz HS-80C86RH
24 Programmable I/O Pins
Bus-Hold Circuitry on All I/O Ports Eliminates Pull-Up Resistors
Direct Bit Set/Reset Capability
Enhanced Control Word Read Capability
Hardened Field, Self-Aligned, Junction Isolated CMOS Process
Single 5V Supply
2.0mA Drive Capability on All I/O Port Outputs
Military Temperature Range: -55
o
C to +125
o
C
Description
The Intersil HS-82C55ARH is a high performance, radiation hardened
CMOS version of the industry standard 8255A and is manufactured using a
hardened field, self-aligned silicongate CMOS process. It is a general
purpose programmable I/O device which may be used with many different
microprocessors. There are 24 I/O pins which are organized into two 8-bit
and two 4-bit ports. Each port may be programmed to function as either an
input or an output. Additionally, one of the 8-bit ports may be programmed
for bi-directional operation,and the two 4-bit ports can be programmed to
provide handshaking capabilities. The high performance, radiation
hardness, and industry standard configuration of the HS-82C55ARH make
it compatible with the HS-80C86RH radiation hardened microprocessor.
Static CMOS circuit design insures low operating power. Bus hold circuitry
eliminates the need for pull-up resistors. The Intersil hardened field CMOS
process results in performance equal to or greater than existing radiation
resistant products at a fraction of the power.
Ordering Information
PART NUMBER
TEMPERATURE
PACKAGE
HS1-82C55ARH-Q
-55
o
C to +125
o
C
40 Lead SBDIP
HS1-82C55ARH-8
-55
o
C to +125
o
C
40 Lead SBDIP
HS1-82C55ARH/Sample
+25
o
C
40 Lead SBDIP
September 1995
Spec Number
518060
File Number
3191.1
DB NA
971
HS-82C55ARH
Pin Description
SYMBOL
PIN
NUMBERS
TYPE
DESCRIPTION
PA0-7
1-4, 37-40
I/O
Port A: General purpose I/O Port. Data direction and mode is determined by the contents
of the Control Word.
PB0-7
18-25
I/O
Port B: General purpose I/O port. See Port A.
PC0-3
14-17
I/O
Port C (Lower): Combination I/O port and control port associated with Port B. See Port A.
PC4-7
10-13
I/O
Port C (Upper): Combination I/O Port and control port associated with Port A. See Port A.
D0-7
27-34
I/O
Bidirectional Data Bus: Three-State data bus enabled as an input when CS and WR are
low and as an output when CS and RD are low.
VDD
26
I
VDD: The +5V power supply pin. A 0.1
F capacitor between pins 26 and 7 is recommend-
ed for decoupling.
GND
7
I
Ground.
CS
6
I
Chip Select: A "low" on this input pin enables the communication between the
HS-82C55ARH and the CPU.
RD
5
I
Read: A "low" on this input pin enables the HS-82C55ARH to send the data or status
information to the CPU on the data bus. In essence, it allows the CPU to "read from" the
HS-82C55ARH.
WR
36
I
Write: A "low" on this input pin enables the CPU to write data or control words into the
HS-82C55ARH.
A0 and A1
8, 9
I
Port Select 0 and Port Select 1: These input signals, in conjunction with the RD and WR
inputs, control the selection of one of the three ports or the control word registers. They are
normally connected to the Least Significant Bits of the address bus (A0 and A1).
Reset
35
I
Reset: A "high" on this input clears the control register and all ports (A, B, C) are set to the
input mode. "Bus hold" devices internal to the HS-82C55ARH will hold the I/O port inputs
to a logic "1" state with a maximum hold current of 400
A.
Functional Diagram
GROUP A
CONTROL
POWER
SUPPLIES
DATA
BUS
BUFFER
GROUP B
CONTROL
READ/WRITE
CONTROL
LOGIC
RD
WR
A1
A0
RESET
CS
D7 - D0
BIDIRECTIONAL
DATA BUS
+5V
GND
8-BIT INTERNAL
DATA BUS
GROUP B
PORT B
(8)
GROUP B
PORT C
LOWER (4)
GROUP A
PORT C
UPPER (4)
GROUP A
PORT A
(8)
I/O
PA7 - PA0
I/O
PC7 - PC4
I/O
PC3 - PC0
I/O
PB7 - PB0
Spec Number
518060
972
Specifications HS-82C55ARH
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . . .VSS-0.3V to VDD+0.3V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65
o
C to +150
o
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300
o
C
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
JA
JC
SBDIP Package. . . . . . . . . . . . . . . . . . . .
40
o
C/W
6
o
C/W
Maximum Package Power Dissipation at +125
o
C Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25.0mW/C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V
Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VDD -1.5V to VDD
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
GROUP A
SUBGROUP
TEMPERATURE
LIMITS
UNITS
MIN
MAX
TTL Output High Voltage
VOH1
VDD = 4.5V, IO = -2.5mA,
VIN = 0V, 4.5V
1, 2, 3
-55
o
C, +25
o
C,
+125
o
C
3.0
-
V
CMOS Output High Volt-
age
VOH2
VDD = 4.5V, IO = -100
A,
VIN = 0V, 4.5V
1, 2, 3
-55
o
C, +25
o
C,
+125
o
C
VDD-
0.4
-
V
Output Low Voltage
VOL
VDD = 4.5V, IO = 2.5mA,
VIN = 0V, 4.5V
1, 2, 3
-55
o
C, +25
o
C,
+125
o
C
-
0.4
V
Input Leakage Current
IIL or IIH
VDD = 5.5V, VIN = 0V, 5.5V
1, 2, 3
-55
o
C, +25
o
C,
+125
o
C
-1.0
1.0
A
Output Leakage Current
IOZL or
IOZH
VDD = 5.5V, VIN = 0V, 5.5V
1, 2, 3
-55
o
C, +25
o
C,
+125
o
C
-10
10
A
Input Current Bus Hold
High
IBHH
VDD = 4.5V or 5.5V,
VIN = 3.0V (See Note 1)
Ports A, B, C
1, 2, 3
-55
o
C, +25
o
C,
+125
o
C
-800
-60
A
Input Current Bus Hold
Low
IBHL
VDD = 4.5V or 5.5V,
VIN = 1.0V (See Note 2)
Port A
1, 2, 3
-55
o
C, +25
o
C,
+125
o
C
60
800
A
Standby Power Supply
Current
IDDSB
VDD = 5.5V, IO = 0mA,
VIN =GND or VDD
1, 2, 3
-55
o
C, +25
o
C,
+125
o
C
-
20
A
Darlington Drive Voltage
VDAR
VDD = 4.5V, IO = -2.0mA,
VIN = GND or VDD
1, 2, 3
-55
o
C, +25
o
C,
+125
o
C
3.9
-
V
Functional Tests
FT
VDD = 4.5V and 5.5V,
VIN = GND or VDD,
f = 1MHz
7, 8A, 8B
-55
o
C, +25
o
C,
+125
o
C
-
-
-
Noise Immunity Functional
Test (Note 4)
FN
VDD = 5.5V, VIN = GND or
VDD - 1.5V and
VDD = 4.5V, VIN = 0.8V or
VDD
7, 8A, 8B
-55
o
C, +25
o
C,
+125
o
C
-
-
-
NOTES:
1. IBHH should be measured after raising VIN and then lowering to 3.0V.
2. IBHL should be measured after lowering VIN to VSS and then raising to 0.8V.
3. No internal current limiting exists on the Port Outputs. A resistor must be added externally to limit the current.
4. For VIH (VDD = 5.5V) and VIL (VDD = 4.5V) each of the following groups is tested separately with all other inputs using VIH = 2.6V,
VIL = 0.4V: PA, PB, PC, Control Pins (Pins 5, 6, 8, 9, 35, 36).
Spec Number
518060
973
Specifications HS-82C55ARH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS T
A
= -55
o
C to +125
o
C
PARAMETER
SYMBOL
CONDITIONS
SUB-
GROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
READ
Address Stable Before
RD
TAVRL
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
0
-
ns
Address Stable After RD
TRHAX
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
0
-
ns
RD Pulse Width
TRLRH
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
250
-
ns
Data Valid From RD
TRLDV
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
200
ns
Data Float After RD
TRHDX
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
10
-
ns
Time Between RDs and/
or WRs
TRWHRWL
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
300
-
ns
WRITE
Address Stable Before
WR
TAVWL
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
0
-
ns
Address Stable After WR
TWHAX
VDD = 4.5, 5.5V,
Ports A and B
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
20
-
ns
VDD = 4.5, 5.5V,
Port C
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
100
-
ns
WR Pulse Width
TWLWH
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
100
-
ns
Data Valid to WR High
TDVWH
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
100
-
ns
Data Valid After WR High
TWHDX
VDD = 4.5, 5.5V,
Ports A and B
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
30
-
ns
VDD = 4.5, 5.5V,
Port C
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
100
-
OTHER TIMINGS
WR = 1 to Output
TWHPV
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
350
ns
Peripheral Data Before
RD
TPVRL
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
0
-
ns
Peripheral Data After RD
TRHPX
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
0
-
ns
ACK Pulse Width
TKLKH
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
200
-
ns
STB Pulse Width
TSLSH
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
100
-
ns
Peripheral Data Before
STB High
TPVSH
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
20
-
ns
Peripheral Data After
STB High
TSHPX
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
50
-
ns
ACK = 0 to Output
TKLPV
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
175
ns
ACK = 1 to output Float
TKHPZ
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
10
-
ns
Spec Number
518060
974
Specifications HS-82C55ARH
WR = 1 to OBF = 0
TWHOL
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
150
ns
ACK = 0 to OBF = 1
TKLOH
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
150
ns
STB = 0 to IBF = 1
TSLIH
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
150
ns
RD = 1 to IBF = 0
TRHIL
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
150
ns
RD = 0 to INTR = 1
TRLNL
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
200
ns
STB = 1 t INTR = 1
TSHNH
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
150
ns
ACK = 1 to INTR = 1
TKHNH
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
150
ns
WR = 0 to INTR = 0
TWLNL
VDD = 4.5, 5.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
200
ns
RESET Pulse Width
TRSHRSL
VDD = 4.5, 5.5V
(Note 2)
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
500
-
ns
NOTES:
1. AC's tested at worst case VDD, guaranteed over full operating range.
2. Period of initial RESET pulse after power-on must be at least 50
s. Subsequenct RESET pulses may be 500ns minimum.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Input Capacitance
CIN
VDD = Open, f = 1MHz, All
measurements referenced to
device ground
T
A
= +25
o
C
-
10
pF
I/O Capacitance
CI/O
VDD = Open, f = 1MHz, All
measurements referenced to
device ground
T
A
= +25
o
C
-
20
pF
Data Float After RD
TRHDX
VDD = 4.5V and 5.5V
-55
o
C < T
A
< +125
o
C
-
75
ns
ACK = 1 to Output Float
TKHPZ
VDD = 4.5V and 5.5V
-55
o
C < T
A
< +125
o
C
-
250
ns
NOTE: The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design release and upon design changes which would affect these characteristics
TALBE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS
See +25
o
C limits in Table 1 and Table 2 for Post RAD limits (Subgroups 1, 7, 9)
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS T
A
= -55
o
C to +125
o
C (Continued)
PARAMETER
SYMBOL
CONDITIONS
SUB-
GROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Spec Number
518060