File Number

3555.6

HSP43124

Serial I/O Filter

The Serial I/O Filter is a high performance filter engine that is
ideal for off loading the burden of filter processing from a
DSP microprocessor. It supports a variety of multistage filter
configurations based on a user programmable filter and fixed
coefficient halfband filters. These configurations include a
programmable FIR filter of up to 256 taps, a cascade of from
one to five halfband filters, or a cascade of halfband filters
followed by a programmable FIR. The half band filters each
decimate by a factor of two, and the FIR filter decimates from
one to eight. When all six filters are selected, a maximum
decimation of 256 is provided.

For digital tuning applications, a separate multiplier is
provided which allows the incoming data stream to be
multiplied, or mixed, by a user supplied mix factor. A two pin
interface is provided for serially loading the mix factor from
an external source or selecting the mix factor from an on-
board ROM. The on-board ROM contains samples of a
sinusoid capable of spectrally shifting the input data by one
quarter of the sample rate, F

/4. This allows the chip to

function as a digital down converter when the filter stages
are configured as a low-pass filter.

The serial interface for

3- input and output data is compatible

with the serial ports of common DSP microprocessors.
Coefficients and configuration data are loaded over a
bidirectional eight bit interface.

Features

· 45MHz Clock Rate

· 256 Tap Programmable FIR Filter

· 24-Bit Data, 32-Bit Coefficients

· Cascade of up to 5 Half Band Filters

· Decimation from 1 to 256

· Two Pin Interface for Down Conversion by F

· Multiplier for Mixing or Scaling Input with an External

Source

· Serial I/O Compatible with Most DSP Microprocessors

Applications

· Low Cost FIR Filter

· Filter Co-Processor

· Digital Tuner

Block Diagram

Ordering Information

PART NUMBER

TEMP.

RANGE (

PACKAGE

PKG.

NO.

HSP43124PC-45

0 to 70

28 Ld PDIP

E28.6

HSP43124PC-33

0 to 70

28 Ld PDIP

E28.6

HSP43124SC-45

0 to 70

28 Ld SOIC

M28.3

HSP43124SC-33

0 to 70

28 Ld SOIC

M28.3

HSP43124SI-40

-40 to 85

28 Ld SOIC

M28.3

OGRAMMABLE

FIR

FIL

TER

INPUT

FORMA

TTER

DIN

SCLK

SYNCIN

MXIN

SYNCMX

OUTPUT

FORMA

TTER

DOUT

SYNCOUT

CLKOUT

A0-2

C0-7

CONTROL

INTERFACE

FSYNC

FCLK

HALF

BAND

FILTER

HALF

BAND

FILTER

HALF

BAND

FILTER

Data Sheet

May 1999

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

Intersil Corporation 1999

Pin Description

NAME

TYPE

DESCRIPTION

+5V Power Supply

GND

Ground

DIN

Serial Data Input. The bit value present on this input is sampled on the rising edge of SCLK. A "HIGH" on this input
represents a "1", and a low on this input represents "0". The word format and operation of serial interface are con-
tained in the Data Input Section.

SYNCIN

Data Sync. The HSP43124 is synchronized to the beginning of a new data word on DIN when SCLK samples SYN-
CIN "HIGH" one SCLK before the first bit of the new word.

NOTE: SYNCIN should not maintain a "HIGH" state

for longer than one SCLK cycle.

SCLK

Serial Input CLK. The rising edge of SCLK clocks data on DIN and MXIN into the part. The following signals are
synchronous to this clock: DIN, SYNCIN, MXIN, SYNCMX.

MXIN

Mix Factor Input. MXIN is the serial input for the mix factor. It is sampled on the rising edge of SCLK. A "HIGH" on
this input represents a "1", and a low on this input represents "0". Also used to specify the Weaver Modulator ROM
output as a part of the two pin F

4 down conversion interface. Details on word format and operation are contained

in the Mix Factor Section.

SYNCMX

Mix Factor Sync. The HSP43124 is synchronized to the beginning of a serially input mix factor when SCLK samples
SYNCMX "HIGH" one SCLK before the first bit of the new mix factor.

NOTE: SYNCMX should only pulse "HIGH" for

one SCLK cycle. Also used to specify Weaver Modulator ROM output as a part of the two pin F

/4 down con-

version interface.

FCLK

Filter Clock. The filter clock determines the processing speed of the Filter Compute Engine. Clock rate require-
ments on FCLK for particular filter configurations is discussed in the Filter Compute Engine Section. This clock
may be asynchronous to the serial input clock (SCLK). FSYNC is synchronous to this clock.

FSYNC

Filter Sync. This input, when sampled low by the rising edge of FCLK, resets the filter compute engine so that the
data sample following the next SYNCIN cycle is the first data sample into the filter structure. If a data stream is
currently being input, the current sum of products and the input data are "canceled" and the DIN pin is ignored until
the next SYNCIN cycle occurs.

Write. The falling edge of WR loads data present on C0-7 into the configuration or coefficient register specified by
the address on A0-2. The WR signal is asynchronous to all other clocks.

NOTE: WR should not be low when

RD is low.

Read. The falling edge of RD accesses the control registers or coefficient RAM addressed by A0-2 and places
the contents of that memory location on C0-7. When RD returns "HIGH" the C0-7 bus functions as an input bus.
The RD pin is asynchronous to all other clocks.

NOTE: RD should not be low when WR is low.

A0-2

Address Bus. The A0-2 inputs are decoded on the falling edge of both RD and WR. Table 1 shows the address
map for the control registers.

C0-7

I/O

Control and Coefficient bus. This bidirectional bus is used to access the control registers and coefficient RAM.

CLKOUT

Output Clock. Programmable bit clock for serial output.

NOTE: Assertion of FSYNC initializes CLKOUT to a

high state.

SYNCOUT

Output Data Sync. SYNYOUT is asserted HIGH for one CLKOUT cycle before the first bit of a new output sample
is available on DOUT.

DOUT

Serial Data Output. The bit stream is synchronous to the rising edge of CLKOUT. (See the Serial Output Formatter
section for additional details.)

HSP43124

Functional Descriptions

The HSP43124 is a high performance digital filter designed to
process a serial input data stream. A second serial interface is
provided for mix factor inputs, which are multiplied by the input
samples as shown in Figure 1. The multiplier result is passed
to the Filter Compute Engine for processing.

The Filter Compute Engine centers around a single
multiply/accumulator (MAC). The MAC performs the sum-of-
products required by a particular filter configuration. The
processing rate of the MAC is determined by the filter clock,
FCLK. Increasing FCLK relative to the input sample rate
increases the length of filter that can be realized.

The filtered results are passed to the Output Formatter where
they are rounded or truncated to a user defined bit width. The
Output Formatter then generates the timing and
synchronization signals required to serially transmit the data
to an external device.

Filter Configuration

The HSP43124 is configured for operation by loading a set of
eight control registers. These registers are written through a
bidirectional interface which is also used for reading the
control registers. The interface consists of an 8-bit data bus,
C0-7, a 3-bit address bus, A0-2, and read/write lines, RD and
WR. The address map for the control registers is shown in
Table 1.

Data is written to the configuration control registers on the
falling edge of the WR input. This requires that the address,
A0-2, and data, C0-7, be stable and valid on the falling edge
of the WR, as shown in Figure 2.

NOTE: WR should not be

active low when RD is active low.

Data is read from the configuration control registers on the
falling edge of the RD input. The contents of a particular
register are accessed by setting up an address, A0-2, to the
falling edge of RD as shown in Figure 2. The data is output on
C0-7. The data on C0-7 remains valid until RD returns HIGH,
at which point the C0-7 bus is Three-Stated and functions as
an input. For proper operation, the address on A0-2 must be
held until RD returns "high" as shown in Figure 2.

NOTE: RD

should not be active low when WR is active low.

M
U
X

MUX

HOLDING

REG

MIX FACTOR

HOLDING

SERIAL

MULTIPLIER

ROUND/

SATURATE

COEFFICIENT

RAM

R
E
G

VARIABLE LENGTH

SHIFT REGISTER

(8 TO 24 BITS)

ROUND/

SATURATE

WEAVER

MODULATOR

ROM

MUX

CONTROL

MXIN

SYNCIN

HALFBAND

COEFFICIENT

ROM

REG

REGISTER

FILE

VARIABLE LENGTH

SHIFT REGISTER

(8-24-BITS)

DIN

SYNCIN

SYNCMX

MXIN

A0-2
C0-7

FSYNC

FCLK

SCLK

MULTIPLY/

INPUT FORMATTER

FILTER COMPUTE ENGINE

SYNCMX

OUTPUT

FORMATTER

ACCUMULATOR

DOUT

SYNCOUT

CLKOUT

FIGURE 1. SERIAL FILTER BLOCK DIAGRAM

INPUT

# BITS

MSB F/2

FORMAT

MIX
SEL

# BITS

FORMAT

FILT EN

# HBs

DECIMATION

RATE

FIR SYM

RD EN

FILTER LENGTH

RAM ACCESS

ROUND

FORMAT

GAIN COR

# BITS

FCLK

MSB F/L

CLKOUT

Indicates configuration control word data parameter.

CONTROL

PARAMETERS

A0-2

WRITE TIMING

C0-7

A0-2

READ TIMING

C0-7

FIGURE 2. READ/WRITE TIMING

HSP43124

Writing Coefficients

The HSP43124 provides a register bank to store filter
coefficients for configurations which use the programmable
filter. The register bank consists of 128 thirty-two-bit
registers. Each register is loaded by 4 one byte writes to the
bidirectional interface used for loading the configuration
registers. The coefficients are loaded in order from least
significant byte (LSB) to most significant byte (MSB).

The coefficient registers are loaded by first setting the
coefficient read enable bit to "0" (bit 4 of the Filter
Configuration Register). Next, coefficients are loaded by
setting the A2-0 address to 010 (binary) and writing one byte
at a time as shown in Figure 3. The down loaded bytes are
stored in a holding register until the 4th write cycle. On
completion of the fourth write cycle, the contents of the
holding register are loaded into the Coefficient RAM, and the
write pointer is incremented to the next register. If the user
attempts to write more than 128 coefficients, the pointer

TABLE 1. CONFIGURATION CONTROL REGISTER FUNCTIONAL DESCRIPTION

ADDRESS

REGISTER DESCRIPTION

BIT

POSITIONS

BIT FUNCTION

000

Filter Configuration

2-0

Specifies the number of halfbands to use. Number ranges from 0 to 5. Other
values are invalid.

Filter Enable bit. 1 = Enable. 0 = Minimum filter bypass (either the FIR or
HBF must be enabled to get an output).

Coefficient read enable. When set to 1, enables reading and disables writing
of coefficient RAM.

NOTE: This bit must be set to 0 prior to writing the

Coefficient RAM.

7-5

FIR Decimation Rate. Range is 1-8 (8 = 000).

001

Programmable FIR Filter Length

7-0

Number of Taps in the Programmable FIR Filter. For even or odd symmetric
filters, values range from 4- 256, 1 to 3 are invalid, and 0000000 = 256. For
asymmetric filters, the value loaded in this register must be two times the ac-
tual number of coefficients.

010

Coefficient RAM Access

7-0

Coefficient RAM is loaded by multiple writes to this address. (See Writing
Coefficients section for additional details.)

011

Input Format

4-0

Number of bits in input data word, from 8 (01000) to 24 (11000). Values out-
side the range of 8 - 24 are invalid.

Number System. 0 = Two's Complement, 1 = Offset Binary.

Serial Format. 1 = MSB First, 0 = LSB First.

Unused

100

Output Timing

4-0

Number of FCLKS per CLKOUT. Range 1 to 32. (00000 = 32 FCLKS)

1 = MSB First, 0 = LSB First.

6-7

Unused

101

Output Format

4-0

Number of bits in output data word, from 8 to 32. A value of 32 is represented
by 00000, and values from 1 to 7 are invalid.

Round Select. 1 = Round to Selected Number of Bits, 0 = Truncate.

Number System. 0 = Two's Complement, 1 = Offset Binary.

Gain Correction. 1 = Apply scale factor of 2 to data. 0 = No Scaling.

110

Filter Symmetry

1-0

00 = Even Symmetric FIR Coefficients
01 = Non-Symmetric Coefficients
10 = Odd Symmetric FIR

7-2

Reserved: Must be 0.

111

Mix Factor Format

4-0

Number of bits in mix factor, from 8 (01000) to 24 (11000). Values outside
the range of 8 - 24 are invalid.

Serial Format. 1 = MSB First, 0 = LSB First.

Mix Factor Select. 1 = Serial Input, 0 = Weaver modulator look-up-table.

Unused

HSP43124

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