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3-193
HSP43216
Halfband Filter
The HSP43216 Halfband Filter addresses a wide variety of
applications by combining f
S
/4 (f
S
= sample frequency)
quadrature up/down convert circuitry with a fixed coefficient
halfband filter processor as shown in the block diagram.
These elements may be configured to operate in one of the
four following modes: decimate by 2 filtering of a real input
signal; interpolate by 2 filtering of a real input signal; f
S
/4
quadrature down conversion of a real input signal followed
by decimate-by-2 filtering to produce a complex analytic
signal; interpolate-by-2 filtering of a complex analytic signal
followed by f
S
/4 quadrature up conversion to produce a real
valued output.
The frequency response of the HSP43216's halfband filter
has a shape factor, (passband+transition band)/passband,
of 1.24:1 with 90dB of stopband attenuation. The passband
has less than 0.0003dB of ripple from 0f
S
to 0.2f
S
with
stopband attenuation of greater than 90dB from 0.3f
S
to
Nyquist. At 0.25f
S
the filter provides 6dB of attenuation.
The HSP43216 processes data streams with word widths up
to 16 bits and data rates up to 52 MSPS. The processing
throughput of the part is easily doubled to rates of up to 104
MSPS by using the part together with an external multiplexer
or demultiplexer. Programmable rounding is provided to
support output precisions from 8 bits to 16 bits.
Features
Sample Rates to 52 MSPS
Architected to Support Sample Rates to 104 MSPS Using
External Multiplexer
Four Modes of Operation:
- Interpolate by 2 Filtering
- Decimate by 2 Filtering
- Quadrature to Real Signal Conversion
- f
S
/4 Quadrature Down Conversion Followed by
Decimate by 2 Filtering
16-Bit Inputs and Outputs
67-Tap Halfband FIR Filter with 20-Bit Coefficients
Two's Complement or Offset Binary Outputs
Programmable Rounding on Outputs
1.24:1 Filter Shape Factor
>90dB Stopband Attenuation
<0.0003dB Passband Ripple
Saturation Logic on Output
Applications
Digital Down Conversion
D/A and A/D pre/post Filtering
Tuning Bandwidth Expansion for HSP45116 and
HSP45106
Block Diagram
Ordering Information
PART
NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
TYPE
PKG. NO.
HSP43216GC-52
0 to 70
85 Ld CPGA
G85.A
HSP43216JC-52
0 to 70
84 Ld PLCC
N84.1.15
HSP43216VC-52
0 to 70
100 Ld MQFP
Q100.14x20
INPUT DATA
FLOW
CONTROLLER
f
S
/4
QUADRATURE
PROCESSOR
67-TAP
PROCESSOR
f
S
/4
QUADRATURE
UP CONVERT
PROCESSOR
OUTPUT DATA
FLOW
CONTROLLER/
FORMATTER
AIN0-15
BIN0-15
AOUT0-15
BOUT0-15
MODE0-1
SYNC
USB/LSB
INT/EXT
RND0-2
FMT
DOWN
CONVERT
HALFBAND
FILTER
OEA
OEB
CLK
Data Sheet
January 1999
File Number
3365.7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
3-194
Pinouts
85 PIN PGA
TOP VIEW
85 PIN PGA
BOTTOM VIEW
BOUT
BOUT
BOUT
BOUT
AOUT AOUT
BOUT
BOUT
BOUT
BOUT
BOUT
GND
BOUT
BOUT
BOUT
BOUT
BOUT
BOUT
BOUT
V
CC
OEB
GND
RND2
RND1
BIN15
BIN14
BIN12
BIN9
BIN11
BIN5
BIN2
BIN0
INT/
V
CC
RND0
BIN13
BIN10
BIN6
BIN4
BIN1
USB/
SYNC
GND
BIN8
BIN7
BIN3
INDEX
PIN
CLK
MODE1
AIN15
AIN12
AIN11
AIN8
AIN5
AIN3
AIN2
FMT
V
CC
AIN0
AIN1
AIN4
AIN7
AIN6
AIN13
MODE
AIN10
AIN14
AOUT8
AOUT9
AOUT
AOUT6
AOUT5
AOUT7
AOUT
AOUT AOUT
AOUT
AOUT
GND
OEA
AOUT
AOUT
GND
AOUT4
A
B
C
D
E
F
G
H
J
K
L
11
10
9
8
7
6
5
4
3
2
1
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
LSB
PIN `A1'
ID
EXT
AIN9
10
15
13
12
10
8
4
1
2
0
14
11
9
5
3
0
3
1
7
6
2
11
12
13
14
15
0
BOUT
BOUT
BOUT
BOUT
AOUT2
AOUT0
BOUT
BOUT
BOUT9
BOUT7
BOUT8
GND
BOUT5
BOUT6
BOUT4
BOUT3
BOUT2
BOUT1
BOUT0
V
CC
OEB
GND
RND2
RND1
BIN15
BIN14
BIN12
BIN9
BIN11
BIN5
BIN2
BIN0
INT/
V
CC
RND0
BIN13
BIN10
BIN6
BIN4
BIN1
USB/
SYNC
GND
BIN8
BIN7
BIN3
INDEX
PIN
CLK
MODE1
AIN15
AIN12
AIN11
AIN8
AIN5
AIN3
AIN2
FMT
V
CC
AIN0
AIN1
AIN4
AIN7
AIN6
AIN13
AIN9
AIN10
AIN14
AOUT8
AOUT9
AOUT
AOUT6
AOUT5
AOUT7
AOUT
AOUT
AOUT
AOUT
GND
OEA
AOUT3
AOUT1
GND
AOUT4
A
B
C
D
E
F
G
H
J
K
L
11
10
9
8
7
6
5
4
3
2
1
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
LSB
EXT
PIN `A1'
ID
10
12
13
15
11
14
10
12
13
AOUT
11
15
14
MODE
HSP43216
3-195
100 LEAD MQFP
TOP VIEW
Pinouts
(Continued)
99 98 97 96 95 94 93
91
89
87
85 84 83
81
82
86
88
90
92
100
79
80
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
32 33 34 35 36 37 38
40
42
44
46 47 48
50
49
45
43
41
39
31
V
CC
NC
NC
NC
NC
SYNC
USB/LSB
INT/EXT
BIN0
BIN1
BIN2
BIN3
BIN4
BIN5
BIN6
BIN7
BIN8
BIN9
BIN10
BIN11
BIN12
BIN13
BIN14
BIN15
RND0
RND1
NC
NC
NC
NC
BOUT14
BOUT13
BOUT12
BOUT11
BOUT10
GND
BOUT9
BOUT8
BOUT7
BOUT6
BOUT5
BOUT4
BOUT3
BOUT2
BOUT1
BOUT0
V
CC
GND
OEB
RND2
V
CC
FMT
OEA
GND
AOUT15
AOUT14
AOUT13
AOUT12
AOUT11
AOUT10
AOUT9
AOUT8
AOUT7
AOUT6
AOUT5
AOUT4
AOUT3
AOUT2
AOUT1
AOUT0
GND
NC
NC
NC
NC
BOUT15
NC
NC
NC
NC
AIN0
AIN1
AIN2
AIN3
AIN4
AIN9
AIN8
AIN7
AIN6
AIN5
AIN15
AIN14
AIN13
AIN12
AIN11
AIN10
GND
MODE1
MODE0
CLK
HSP43216
3-196
84 LEAD PLCC
TOP VIEW
Pinouts
(Continued)
AIN0
AIN1
AIN2
AIN3
AIN4
AIN9
AIN8
AIN7
AIN6
AIN5
AIN15
AIN14
AIN13
AIN12
AIN11
AIN10
GND
MODE1
MODE0
BOUT15
BOUT14
BOUT13
BOUT12
BOUT11
BOUT10
GND
BOUT9
BOUT8
BOUT7
BOUT6
BOUT5
BOUT4
BOUT3
BOUT2
BOUT1
BOUT0
V
CC
GND
OEB
RND2
SYNC
USB/LSB
INT/EXT
BIN0
BIN1
BIN2
BIN3
BIN4
BIN5
BIN6
BIN7
BIN8
BIN9
BIN10
BIN11
BIN12
BIN13
BIN14
BIN15
RND0
RND1
V
CC
FMT
OEA
GND
AOUT15
AOUT14
AOUT13
AOUT12
AOUT11
AOUT10
AOUT9
AOUT8
AOUT7
AOUT6
AOUT5
AOUT4
AOUT3
AOUT2
AOUT1
AOUT0
GND
V
CC
CLK
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
Pin Description
NAME
TYPE
DESCRIPTION
V
CC
-
+5V Power.
GND
-
Ground.
CLK
I
Clock Input. (CMOS LEVEL). f
S
is the frequency of CLK
AIN0-15
I
Input Data Bus A. AIN0 is the LSB. Input data format is 16-bit Two's Complement.
BIN0-15
I
Input Data Bus B. BIN0 is the LSB. Input data format is 16-bit Two's Complement.
MODE0-1
I
The Mode Select Inputs set one of four operational modes as highlighted in Table 1.
INT/EXT
I
The Internal\External multiplexer select inputs set whether the data multiplex/demultiplex function required in the various
operational modes is performed internally (High State) or externally to the chip (Low State).
SYNC
I
This input is used to synchronize the input sample stream with the zero degree phase of the up or down convert Local
Oscillators. In the straight decimate modes, this input can be use to synchronize the input sample stream with a particular
phase of the halfband filter. (See the Operational Modes Section for additional information).
USB/LSB
I
The Upper and Lower Sideband select line is used to specify the direction of frequency translation imparted on the data
stream in the Down Convert and Decimate Mode and in the Quadrature to Real Convert Mode. (See Operational Modes
Section for additional information).
RND0-2
I
The Round Select inputs set the number of output bits from eight (RND = 000) to sixteen (RND = 110). Least significant
output bits are zeroed. See Table 4.
OEA
I
Three-State Control Output Bus A, OUTA0-15. Active Low.
OEB
I
Three-State Control Output Bus B, OUTB0-15. Active Low.
FMT
I
The Format select input is used to convert the two's complement output to offset binary (unsigned). When asserted high,
the AOUT15 and BOUT15 bits are inverted from the normal two's complement representation.
AOUT0-15
O
Output Bus A. AOUT0 is the LSB.
BOUT0-15
O
Output Bus B. BOUT0 is the LSB.
HSP43216
3-197
Functional Description
The operation of the HSP43216 centers around a fixed
coefficient, 67-Tap, Halfband Filter Processor as shown in
Figure 1. The Halfband Filter Processor operates stand
alone to provide two fundamental modes of operation:
interpolate or decimate by two filtering of a real signal. In two
other modes, the Quadrature Up/Down Convert circuitry
operates together with the Filter Processor block to provide
f
S
/4 Down Conversion with decimate by 2 filtering or
Quadrature to Real Conversion.
In Down Convert and Decimate mode, a real input sample
stream is spectrally shifted by f
S
/4. Each component of the
resulting complex signal is then halfband filtered and
decimated by 2 to produce real and imaginary output
samples at half of the input data rate.
In Quadrature to Real Conversion mode, the real and
imaginary components of a quadrature input are interpolated
by two and halfband filtered. The filtered result is then
spectrally shifted by f
S
/4 and the real component of this
operation is output at twice the input sample rate.The
HSP43216 is configured for different operational modes by
setting the state of the mode control pins, MODE1-0 as
shown in Table 1.
Input Data Flow Controller
The Input Data Flow Controller routes data samples from the
AIN0-15 and BIN0-15 inputs to the internal processing
elements of the Halfband. The data routing paths are based
on mode of operation and are more fully discussed in the
Operational Modes section.
f
S
/4 Quadrature Down Convert Processor
The f
S
/4 Quadrature Down Convert Processor operates as a
Quadrature LO which provides the negative f
S
/4 spectral
shift required to center the upper sideband of a real input
signal at DC. This operation is equivalent to multiplying the
real sample stream, x(n), by the quadrature components of
the complex exponential e
-j(
/2)n
as given below:
R
E
G
M
U
X
f
S
/4
L.O.
MUX
MUX
1,-1,1,..
-1,1,-1,.
1
1
EVEN TAP
FILTER
MUX
MUX
1
1
...,2,-2,2
..,-2,2,-2
M
U
X
ODD TAP
FILTER
AIN0-15
BIN0-15
BOUT0-15
AOUT0-15
OEA
OEB
USB/LSB
R
E
G
R
E
G
R
E
G
R
E
G
R
E
G
R
E
G
R
E
G
R
E
G
R
N
D
F
M
T
R
E
G
R
E
G
R
N
D
F
M
T
R
E
G
R
E
G
R
E
G
R
E
G
2
2
Indicates elements which operate at CLK/2 when the INT/EXT control input is high.
SYNC
INT/EXT
RND0-2
FMT
MODE0-1
INPUT DATA FLOW
CONTROLLER
f
S
/4 QUADRATURE
DOWN CONVERT
67-TAP HALFBAND
FILTER
f
S
/4 QUADRATURE
UP CONVERT
OUTPUT DATA FLOW
CONTROLLER
PROCESSOR
PROCESSOR
DELAY 19
DELAY 2 - 35
SYNC
PROCESSOR
+
FIGURE 1. HALFBAND BLOCK DIAGRAM
CLK
USB/LSB
PIPELINE
PIPELINE
TABLE 1. MODE SELECT TABLE
MODE1-0
MODE
00
Decimate by Two
01
Interpolate by Two
10
Down Convert and Decimate
11
Quadrature to Real Conversion
x n
( )
e j
n 2
/
(
)
x n
( )
n 2
/
(
)
jx n
( )
n 2
/
(
)
sin
+
cos
=
(EQ. 1)
HSP43216
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