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Электронный компонент: X1228V14-2.7A

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1
FN8100.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
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Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X1228
4K (512 x 8), 2-Wire
TM
RTC
Real Time Clock/Calendar/CPU
Supervisor with EEPROM
FEATURES
Real Time Clock/Calendar
-- Tracks time in Hours, Minutes, and Seconds
-- Day of the Week, Day, Month, and Year
2 Polled Alarms (Non-volatile)
-- Settable on the Second, Minute, Hour, Day of the
Week, Day, or Month
-- Repeat Mode (periodic interrupts)
Oscillator Compensation on chip
-- Internal feedback resistor and compensation
capacitors
-- 64 position Digitally Controlled Trim Capacitor
-- 6 digital frequency adjustment settings to
30ppm
CPU Supervisor Functions
-- Power-on Reset, Low Voltage Sense
-- Watchdog Timer (SW Selectable: 0.25s, 0.75s,
1.75s, off)
Battery Switch or Super Cap Input
512 x 8 Bits of EEPROM
-- 64-Byte Page Write Mode
-- 8 modes of Block LockTM Protection
-- Single Byte Write Capability
High Reliability
-- Data Retention: 100 years
-- Endurance: 100,000 cycles per byte
2-WireTM Interface interoperable with I2C*
-- 400kHz data transfer rate
Frequency Output (SW Selectable: Off, 1Hz,
4096Hz, or 32.768kHz)
Low Power CMOS
-- 1.25A Operating Current (Typical)
Small Package Options
-- 14 Ld SOIC and 14 Ld TSSOP
Repetitive Alarms
Temperature Compensation
Pb-Free Plus Anneal Available (RoHS Compliant)
APPLICATIONS
Utility Meters
HVAC Equipment
Audio/Video Components
Set Top Box/Television
Modems
Network Routers, Hubs, Switches, Bridges
Cellular Infrastructure Equipment
Fixed Broadband Wireless Equipment
Pagers/PDA
POS Equipment
Test Meters/Fixtures
Office Automation (Copiers, Fax)
Home Appliances
Computer Products
Other Industrial/Medical/Automotive
BLOCK DIAGRAM
X1
X2
Oscillator
Frequency
Timer
Logic
Divider
Calendar
8
Control/
Registers
1Hz
Time
Keeping
Registers
Alarm Regs
Compare
Ma
s
k
RESET
Control
Decode
Logic
Alarm
(EEPROM)
(EEPROM)
SCL
SDA
Serial
Interface
Decoder
4K
EEPROM
ARRAY
Watchdog
Timer
Low Voltage
Reset
Registers
Status
(SRAM)
Select
PHZ/IRQ
V
CC
V
BACK
32.768kHz
(SRAM)
Battery
Circuitry
Switch
OSC Compensation
Data Sheet
October 17, 2005
2
FN8100.2
October 17, 2005
Ordering Information
PART NUMBER
PART MARKING
V
CC
RANGE
(V)
V
TRIP
TEMP RANGE
(C)
PACKAGE
X1228S14-4.5A
X1228S AL
2.7 to 5.5
4.63V 112mV
0 to 70
14 Ld SOIC
X1228S14Z-4.5A (Note) X1228S Z AL
0 to 70
14 Ld SOIC (Pb-free)
X1228S14I-4.5A
X1228S AM
-40 to 85
14 Ld SOIC
X1228S14IZ-4.5A (Note) X1228S Z AM
-40 to 85
14 Ld SOIC (Pb-free)
X1228V14-4.5A
X1228V AL
0 to 70
14 Ld TSSOP
X1228V14Z-4.5A (Note) X1228V Z AL
0 to 70
14 Ld TSSOP (Pb-free)
X1228V14I-4.5A
X1228V AM
-40 to 85
14 Ld TSSOP
X1228V14IZ-4.5A (Note) X1228V Z AM
-40 to 85
14 Ld TSSOP (Pb-free)
X1228S14
X1228S
4.38V 112mV
0 to 70
14 Ld SOIC
X1228S14Z (Note)
X1228S Z
0 to 70
14 Ld SOIC (Pb-free)
X1228S14I
X1228S I
-40 to 85
14 Ld SOIC
X1228S14IZ (Note)
X1228S Z I
-40 to 85
14 Ld SOIC (Pb-free)
X1228V14
X1228V
0 to 70
14 Ld TSSOP
X1228V14Z (Note)
X1228V Z
0 to 70
14 Ld TSSOP (Pb-free)
X1228V14I
X1228V I
-40 to 85
14 Ld TSSOP
X1228V14IZ (Note)
X1228V Z I
-40 to 85
14 Ld TSSOP (Pb-free)
X1228S14-2.7A
X1228S AN
2.85V 100mV
0 to 70
14 Ld SOIC
X1228S14Z-2.7A (Note) X1228S Z AN
0 to 70
14 Ld SOIC (Pb-free)
X1228S14I-2.7A
X1228S AP
-40 to 85
14 Ld SOIC
X1228S14IZ-2.7A (Note) X1228S Z AP
-40 to 85
14 Ld SOIC (Pb_free)
X1228V14-2.7A
X1228V AN
0 to 70
14 Ld TSSOP
X1228V14Z-2.7A (Note) X1228V Z AN
0 to 70
14 Ld TSSOP (Pb-free)
X1228V14I-2.7A
X1228V AP
-40 to 85
14 Ld TSSOP
X1228V14IZ-2.7A (Note) X1228V Z AP
-40 to 85
14 Ld TSSOP (Pb-free)
X1228S14-2.7*
X1228S F
2.65V 100mV
0 to 70
14 Ld SOIC
X1228S14Z-2.7* (Note) X1228S Z F
0 to 70
14 Ld SOIC (Pb-free)
X1228S14I-2.7
X1228S G
-40 to 85
14 Ld SOIC
X1228S14IZ-2.7 (Note)
X1228S Z G
-40 to 85
14 Ld SOIC (Pb-free)
X1228V14-2.7
X1228V F
0 to 70
14 Ld TSSOP
X1228V14Z-2.7 (Note)
X1228V Z F
0 to 70
14 Ld TSSOP (Pb-free)
X1228V14I-2.7
X1228V G
-40 to 85
14 Ld TSSOP
X1228V14IZ-2.7 (Note)
X1228V Z G
-40 to 85
14 Ld TSSOP (Pb-free)
*Add "T1" suffix for tape and reel.
Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
X1228
3
FN8100.2
October 17, 2005
PIN DESCRIPTIONS
PIN ASSIGNMENTS
Pin Number
SOIC/TSSOP
Symbol
Brief Description
1
X1
X1. The X1 pin is the input of an inverting amplifier. An external 32.768kHz quartz crystal
is used with the X1228 to supply a timebase for the real time clock. The recommended crystal
is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is included to form a
complete oscillator circuit. Care should be taken in the placement of the crystal and the layout
of the circuit. Plenty of ground plane around the device and short traces to X1 are highly
recommended. See Application section for more recommendations.
2
X2
X2. The X2 pin is the output of an inverting amplifier. An external 32.768kHz quartz crystal
is used with the X1228 to supply a timebase for the real time clock. The recommended crystal
is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is included to form a
complete oscillator circuit. Care should be taken in the placement of the crystal and the layout
of the circuit. Plenty of ground plane around the device and short traces to X2 are highly
recommended. See Application section for more recommendations.
6
RESET
RESET Output RESET. This is a reset signal output. This signal notifies a host
processor that the watchdog time period has expired or that the voltage has dropped below
a fixed V
TRIP
threshold. It is an open drain active LOW output. Recommended value for the
pullup resistor is 5k
. If unused, tie to ground.
7
V
SS
V
SS
.
8
SDA
Serial Data (SDA). SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain or open
collector outputs. The input buffer is always active (not gated).
An open drain output requires the use of a pull-up resistor. The output circuitry controls the
fall time of the output signal with the use of a slope controlled pull-down. The circuit is
designed for 400kHz 2-wire interface speeds.
9
SCL
Serial Clock (SCL). The SCL input is used to clock all data into and out of the device. The
input buffer on this pin is always active (not gated).
12
PHZ/IRQ
Programmable Frequency/Interrupt Output PHZ/IRQ. This is either an output from the
internal oscillator or an interrupt signal output. It is a CMOS output.
When used as frequency output, this signal has a frequency of 32.768kHz, 4096Hz, 1Hz
or inactive.
When used as interrupt output, this signal notifies a host processor that an alarm has
occurred and an action is required. It is an active LOW output.
The control bits for this function are FO1 and FO0 and are found in address 0011h of the
Clock Control Memory map. See "Programmable Frequency Output Bits--FO1, FO0" on
page 14.
13
V
BACK
V
BACK
. This input provides a backup supply voltage to the device. V
BACK
supplies power
to the device in the event the V
CC
supply fails. This pin can be connected to a battery, a
Supercap or tied to ground if not used.
14
V
CC
V
CC
.
NC = No internal connection
NC
NC
X1
X2
1
2
3
4
13
14
12
11
14 Ld TSSOP/SOIC
5
6
7
10
9
8
RESET
V
SS
V
CC
V
BACK
PHZ/IRQ
NC
SCL
NC
SDA
NC
X1228
4
FN8100.2
October 17, 2005
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ................... -65C to +135C
Storage Temperature ........................ -65C to +150C
Voltage on V
CC
, V
BACK
and PHZ/IRQ
pin (respect to ground) ............................-0.5V to 7.0V
Voltage on SCL, SDA, X1 and X2
pin (respect to ground) ............... -0.5V to 7.0V or 0.5V
above V
CC
or V
BACK
(whichever is higher)
DC Output Current .............................................. 5 mA
Lead Temperature (Soldering, 10 sec).............. 300C
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute max-
imum rating conditions for extended periods may
affect device reliability.
DC OPERATING CHARACTERISTICS (Temperature = -40C to +85C, unless otherwise stated.)
OPERATING CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Notes
V
CC
Main Power Supply
2.7
5.5
V
V
BACK
Backup Power Supply
1.8
5.5
V
V
CB
Switch to Backup Supply
V
BACK
-0.2
V
BACK
-0.1
V
V
BC
Switch to Main Supply
V
BACK
V
BACK
+0.2
V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Notes
I
CC1
Read Active Supply
Current
V
CC
= 2.7V
400
A
1, 5, 7, 14
V
CC
= 5.0V
800
A
I
CC2
Program Supply Current
(nonvolatile)
V
CC
= 2.7V
2.5
mA
2, 5, 7, 14
V
CC
= 5.0V
3.0
mA
I
CC3
Main Timekeeping
Current
V
CC
= 2.7V
10
A
3, 7, 8, 14, 15
V
CC
= 5.0V
20
A
I
BACK
Timekeeping Current
(Low Voltage Sense and
Watchdog Timer
disabled
V
BACK
= 1.8V
1.25
A
3, 6, 9, 14, 15
"See Perfor-
mance Data"
V
BACK
= 3.3V
1.5
A
I
LI
Input Leakage Current
10
A
10
I
LO
Output Leakage Current
10
A
10
V
IL
Input LOW Voltage
-0.5
V
CC
x 0.2 or
V
BACK
x 0.2
V
13
V
IH
Input HIGH Voltage
V
CC
x 0.7 or
V
BACK
x 0.7
V
CC
+ 0.5 or
V
BACK
+ 0.5
V
13
V
HYS
Schmitt Trigger Input
Hysteresis
V
CC
related level
.05 x V
CC
or
.05 x V
BACK
V
13
V
OL1
Output LOW Voltage for
SDA and RESET
V
CC
= 2.7V
0.4
V
11
V
CC
= 5.5V
0.4
V
OL2
Output LOW Voltage for
PHZ/IRQ
V
CC
= 2.7V
V
CC
x 0.3
V
11
V
CC
= 5.5V
V
CC
x 0.3
V
OH2
Output HIGH Voltage for
PHZ/IRQ
V
CC
= 2.7V
V
CC
x 0.7
V
12
V
CC
= 5.5V
V
CC
x 0.7
X1228
5
FN8100.2
October 17, 2005
Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave Address
Byte are incorrect or until 200nS after a stop ending a read or write operation.
(2) The device enters the Program state 200nS after a stop ending a write operation and continues for t
WC
.
(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiate a nonvolatile write cycle; t
WC
after a stop
that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave
Address Byte.
(4) For reference only and not tested.
(5) V
IL
= V
CC
x 0.1, V
IH
= V
CC
x 0.9, f
SCL
= 400kHz
(6) V
CC
= 0V
(7) V
BACK
= 0V
(8) V
SDA
= V
SCL
=V
CC
, Others = GND or V
CC
(9) V
SDA
=V
SCL
=V
BACK
, Others = GND or V
BACK
(10) V
SDA
= GND or V
CC
,
V
SCL
= GND or V
CC
,
V
RESET
= V
CC
or GND
(11) I
OL
= 3.0mA at 5.5V, 1.5mA at 2.7V
(12) I
OH
= -1.0mA at 5.5V, -0.4mA at 2.7V
(13) Threshold voltages based on the higher of Vcc or Vback.
(14) Using recommended crystal and oscillator network applied to X1 and X2 (25C).
(15) Typical values are for T
A
= 25C
Capacitance T
A
= 25C, f = 1.0 MHz, V
CC
= 5V
Notes: (1) This parameter is not 100% tested.
(2) The input capacitance between x1 and x2 pins can be varied between 5pF and 19.75pF by using analog trimming registers
AC CHARACTERISTICS
AC Test Conditions
Figure 18. Standard Output Load for testing the device with V
CC
= 5.0V
Symbol
Parameter
Max.
Units
Test Conditions
C
OUT
(1)
Output Capacitance (SDA, PHZ/IRQ, RESET)
10
pF
V
OUT
= 0V
C
IN
(1)
Input Capacitance (SCL)
10
pF
V
IN
= 0V
Input Pulse Levels
V
CC
x 0.1 to V
CC
x 0.9
Input Rise and Fall Times
10ns
Input and Output Timing
Levels
V
CC
x 0.5
Output Load
Standard Output Load
SDA
1533
100pF
5.0V
For V
OL
= 0.4V
and I
OL
= 3 mA
Equivalent AC Output Load Circuit for V
CC
= 5V
1316
5.0V
PHZ/IRQ
100pF
806
X1228